# L-bit-CPU_isdowning

**Repository Path**: chla/L-bit-CPU_isdowning

## Basic Information

- **Project Name**: L-bit-CPU_isdowning
- **Description**: Design with Logisim a 32-bit two-cycle processor
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 1
- **Created**: 2020-09-18
- **Last Updated**: 2020-12-19

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# 32-bit-CPU
Design with Logisim a 32-bit two-cycle processor

I did this project for CS61C at UC Berkeley (Spring 2015):
http://www-inst.eecs.berkeley.edu/~cs61c/sp15/projs/02/index.html

The processor contains four major parts: register files, arithmetic logical unit (ALU), CPU and memory. The instruction set architecture (ISA) is specified in the above link.