# mips-cpu-1_isdowning

**Repository Path**: chla/mips-cpu-1_isdowning

## Basic Information

- **Project Name**: mips-cpu-1_isdowning
- **Description**: MIPS CPU Implemented in Logisim
- **Primary Language**: Unknown
- **License**: MIT
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 2
- **Created**: 2020-09-18
- **Last Updated**: 2020-12-19

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# MIPS CPU

### Basic Information
This is a two-stage pipelined MIPS CPU supporting a subset of MIPS instruction set.

### Usage
1. Open `run.circ` in logisim
2. Load the binary instruction code into instruction memory
3. Use tick to execute instructions

### Currently Supported Instructions
- `add`
- `addi`
- `addiu`
- `addu`
- `and`
- `andi`
- `beq`
- `bne`
- `bov`
- `j`
- `jal`
- `jr`
- `jalr`
- `lui`
- `lw`
- `or`
- `ori`
- `slt`
- `slti`
- `sltiu`
- `sltu`
- `sll`
- `sra`
- `srl`
- `sw`
- `sub`
- `subu`

## License
Code released under the [MIT license](https://github.com/VVVFO/mips-cpu/blob/master/LICENSE).