# Logisim-CPU

**Repository Path**: dongfenga/Logisim-CPU

## Basic Information

- **Project Name**: Logisim-CPU
- **Description**: A 32-bit CPU wired according to the RISC-V ISA under the guidance of Carnegie Mellon PhD student Sol Boucher
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 1
- **Created**: 2020-07-01
- **Last Updated**: 2020-12-19

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# Logisim-CPU