# Logisim-Regfile-ALU-CPU

**Repository Path**: dongfenga/Logisim-Regfile-ALU-CPU

## Basic Information

- **Project Name**: Logisim-Regfile-ALU-CPU
- **Description**: Register File, ALU, and 32 bit 2-cycle (Pipelined) CPU in Logisim
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 2
- **Created**: 2020-06-22
- **Last Updated**: 2023-04-30

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# Logisim-Regfile-ALU-CPU
CS 61C project 3 (Spring 2016)

Created Register File, ALU, and 32 bit 2-cycle (Pipelined) CPU in Logisim.