# udp **Repository Path**: kduant/udp ## Basic Information - **Project Name**: udp - **Description**: fpga udp protocol - **Primary Language**: Verilog - **License**: Apache-2.0 - **Default Branch**: master - **Homepage**: None - **GVP Project**: No ## Statistics - **Stars**: 1 - **Forks**: 1 - **Created**: 2018-08-24 - **Last Updated**: 2023-02-01 ## Categories & Tags **Categories**: Uncategorized **Tags**: None ## README # 项目介绍 fpga udp protocol # 软件环境 * vivado2018.3 * questsim2021.2 * xc7k325t-2ffg900 * Tri Mode Ethernet MAC 9.0 # Tri Mode Ethernet Mac(9.0) 配置 - Name: mac_core ## Page 1 - Data Rate: 1Gbps ## Page 2 - PHY Interface: GMII - MAC Speed : 1000MHz - Management Type: Configuration Vector ## Page 3 - Shared Logic: Include Shared Logic in example design # 硬件架构 1. phy芯片 88E1111 2. 接口 GMII 3. 引脚配置 ```verilog set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports phy_resetn] set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports gmii_rxd[7]] set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports gmii_rxd[6]] set_property -dict {PACKAGE_PIN L30 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports gmii_rxd[5]] set_property -dict {PACKAGE_PIN K25 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports gmii_rxd[4]] set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports gmii_rxd[3]] set_property -dict {PACKAGE_PIN L28 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports gmii_rxd[2]] set_property -dict {PACKAGE_PIN H29 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports gmii_rxd[1]] set_property -dict {PACKAGE_PIN N30 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports gmii_rxd[0]] set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports gmii_txd[7]] set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports gmii_txd[6]] set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports gmii_txd[5]] set_property -dict {PACKAGE_PIN K24 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports gmii_txd[4]] set_property -dict {PACKAGE_PIN L23 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports gmii_txd[3]] set_property -dict {PACKAGE_PIN J26 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports gmii_txd[2]] set_property -dict {PACKAGE_PIN K26 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports gmii_txd[1]] set_property -dict {PACKAGE_PIN L27 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports gmii_txd[0]] set_property -dict {PACKAGE_PIN J28 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports gmii_tx_en] set_property -dict {PACKAGE_PIN J27 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports gmii_tx_er] set_property -dict {PACKAGE_PIN M28 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports gmii_tx_clk] set_property -dict {PACKAGE_PIN K30 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports gmii_rx_dv] set_property -dict {PACKAGE_PIN J29 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports gmii_rx_er] set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports gmii_rx_clk] ``` # IP结构修改 将example工程封装为适合重用的模块 1. 从example工程里复制import文件夹 * 删除`imports/mac_core_example_design_clocks.v` * 删除`imports/mac_core_clk_wiz.v` * 删除`imports/mac_core_basic_pat_gen.v` `imports/mac_core_address_swap.v` `imports/mac_core_axi_mux.v` `imports/mac_core_axi_pat_check.v` `imports/mac_core_axi_pipe.v` * 删除`imports/demo_tb.v`, `imports/mac_core_frame_typ.v` * 删除`imports/*.xdc` 2. 修改`mac_core_example_design.v`，将输入输出端口连接到模块顶层 * 修改发送数据端口 注释掉wire声明，添加到端口里去 ```verilog wire tx_fifo_clock; wire [7:0] tx_axis_fifo_tdata; wire tx_axis_fifo_tvalid; wire tx_axis_fifo_tlast; wire tx_axis_fifo_tready; ``` * 修改接收数据端口 ```verilog wire rx_fifo_clock; wire [7:0] rx_axis_fifo_tdata; wire rx_axis_fifo_tvalid; wire rx_axis_fifo_tlast; wire rx_axis_fifo_tready; ``` * 注释掉`mac_core_basic_pat_gen` * 注释掉`mac_core_example_design_clocks` , `refclk_buf`声明, 添加`input wire refclk_buf`端口 * 注释掉 ```verilog input clk_in_p, input clk_in_n, wire gtx_clk_bufg; ``` 添加 `input wire gtx_clk_bufg,` * 添加`assign dcm_locked = 1'b1;` # 例化 ```verilog enthernet_top # ( .C_CLK_FREQ_HZ ( 125_000_000 ), .LOCAL_MAC_ADDR ( 48'hC400C4010102 ), .LOCAL_IP_ADDR ( {8'd192, 8'd168, 8'd1, 8'd102} ), .LOCAL_UDP_PORT ( 16'd4444 ), .REMOTE_UDP_PORT ( 16'd6666 ) ) enthernet_topEx01 ( .clk ( clk ), .clk_200m ( clk_200m ), .rst ( rst ), .load_parameter ( load_parameter ), .load_m_axi_tdata ( load_m_axi_tdata ), .load_m_axi_tvalid ( load_m_axi_tvalid ), .load_m_axi_tready ( load_m_axi_tready ), .load_m_axi_tlast ( load_m_axi_tlast ), .update_paramter ( update_paramter ), .update_m_axi_tdata ( update_m_axi_tdata ), .update_m_axi_tvalid ( update_m_axi_tvalid ), .update_m_axi_tready ( update_m_axi_tready ), .update_m_axi_tlast ( update_m_axi_tlast ), .phy_resetn ( phy_resetn ), .gmii_tx_clk ( gmii_tx_clk ), .gmii_txd ( gmii_txd ), .gmii_tx_en ( gmii_tx_en ), .gmii_tx_er ( gmii_tx_er ), .gmii_rx_clk ( gmii_rx_clk ), .gmii_rxd ( gmii_rxd ), .gmii_rx_dv ( gmii_rx_dv ), .gmii_rx_er ( gmii_rx_er ) ); ```