From 865094b8d4fc2c8a1ea636d92dc744fe33bad8cb Mon Sep 17 00:00:00 2001 From: LeoLiu-oc Date: Fri, 14 Nov 2025 16:24:39 +0800 Subject: [PATCH] ata: zhaoxin: update for rename symbols zhaoxin inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/ID6NYN CVE: NA -------------------- apply non-functional renames and style cleanups for the Zhaoxin SATA driver Changes grouped: - Symbol/API renames: szx_* -> zx_*, cnd001 -> zx100s; update pci_device_id, pci_driver, scsi_host_template, port ops/info and core functions. - Data/format: consolidate/rename BAR arrays, use ARRAY_SIZE, whitespace and printk/dev_dbg formatting fixes. No behavioral or algorithmic changes; PCI IDs and hardware support unchanged. Reviewed-by: Tony W. Wang Tested-by: Lyle Li Signed-off-by: LeoLiu-oc --- drivers/ata/Kconfig | 9 +- drivers/ata/Makefile | 2 +- drivers/ata/sata_zhaoxin.c | 213 +++++++++++++++++-------------------- 3 files changed, 103 insertions(+), 121 deletions(-) diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 5f62dcdc546b..3dd828c3edf8 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -553,10 +553,13 @@ config SATA_VITESSE If unsure, say N. config SATA_ZHAOXIN - tristate "ZhaoXin SATA support" - depends on PCI + tristate "Zhaoxin SATA support" + depends on PCI && (CPU_SUP_ZHAOXIN || CPU_SUP_CENTAUR) help - This option enables support for ZhaoXin Serial ATA. + This option enables support for Zhaoxin Serial ATA. + + To compile this driver as a module, choose M here: the + module will be called sata-zhaoxin. If unsure, say N. diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index 9a3ce171d9e8..8f784544eb5b 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -46,7 +46,7 @@ obj-$(CONFIG_SATA_SVW) += sata_svw.o obj-$(CONFIG_SATA_ULI) += sata_uli.o obj-$(CONFIG_SATA_VIA) += sata_via.o obj-$(CONFIG_SATA_VITESSE) += sata_vsc.o -obj-$(CONFIG_SATA_ZHAOXIN) += sata_zhaoxin.o +obj-$(CONFIG_SATA_ZHAOXIN) += sata_zhaoxin.o # SFF PATA w/ BMDMA obj-$(CONFIG_PATA_ALI) += pata_ali.o diff --git a/drivers/ata/sata_zhaoxin.c b/drivers/ata/sata_zhaoxin.c index 8e30a6525f54..12253c1c1e1f 100644 --- a/drivers/ata/sata_zhaoxin.c +++ b/drivers/ata/sata_zhaoxin.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * sata_zhaoxin.c - ZhaoXin Serial ATA controllers + * sata_zhaoxin.c - Zhaoxin Serial ATA controllers */ #include @@ -14,82 +14,79 @@ #include #include -#define DRV_NAME "sata_zx" -#define DRV_VERSION "2.6.1" +#define DRV_NAME "sata_zx" +#define DRV_VERSION "2.6.1" enum board_ids_enum { - cnd001, + zx100s, }; enum { - SATA_CHAN_ENAB = 0x40, /* SATA channel enable */ - SATA_INT_GATE = 0x41, /* SATA interrupt gating */ - SATA_NATIVE_MODE = 0x42, /* Native mode enable */ - PATA_UDMA_TIMING = 0xB3, /* PATA timing for DMA/ cable detect */ - PATA_PIO_TIMING = 0xAB, /* PATA timing register */ + SATA_CHAN_ENAB = 0x40, /* SATA channel enable */ + SATA_INT_GATE = 0x41, /* SATA interrupt gating */ + SATA_NATIVE_MODE = 0x42, /* Native mode enable */ + PATA_UDMA_TIMING = 0xB3, /* PATA timing for DMA/ cable detect */ + PATA_PIO_TIMING = 0xAB, /* PATA timing register */ - PORT0 = (1 << 1), - PORT1 = (1 << 0), - ALL_PORTS = PORT0 | PORT1, + PORT0 = (1 << 1), + PORT1 = (1 << 0), + ALL_PORTS = PORT0 | PORT1, - NATIVE_MODE_ALL = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4), + NATIVE_MODE_ALL = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4), - SATA_EXT_PHY = (1 << 6), /* 0==use PATA, 1==ext phy */ + SATA_EXT_PHY = (1 << 6), /* 0==use PATA, 1==ext phy */ }; -static int szx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); -static int cnd001_scr_read(struct ata_link *link, unsigned int scr, u32 *val); -static int cnd001_scr_write(struct ata_link *link, unsigned int scr, u32 val); -static int szx_hardreset(struct ata_link *link, unsigned int *class, - unsigned long deadline); +static int zx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); +static int zx_scr_read(struct ata_link *link, unsigned int scr, u32 *val); +static int zx_scr_write(struct ata_link *link, unsigned int scr, u32 val); +static int zx_hardreset(struct ata_link *link, unsigned int *class, unsigned long deadline); -static void szx_tf_load(struct ata_port *ap, const struct ata_taskfile *tf); +static void zx_tf_load(struct ata_port *ap, const struct ata_taskfile *tf); -static const struct pci_device_id szx_pci_tbl[] = { - { PCI_VDEVICE(ZHAOXIN, 0x9002), cnd001 }, - { PCI_VDEVICE(ZHAOXIN, 0x9003), cnd001 }, +static const struct pci_device_id zx_pci_tbl[] = { + { PCI_VDEVICE(ZHAOXIN, 0x9002), zx100s }, + { PCI_VDEVICE(ZHAOXIN, 0x9003), zx100s }, - { } /* terminate list */ + {} /* terminate list */ }; -static struct pci_driver szx_pci_driver = { - .name = DRV_NAME, - .id_table = szx_pci_tbl, - .probe = szx_init_one, +static struct pci_driver zx_pci_driver = { + .name = DRV_NAME, + .id_table = zx_pci_tbl, + .probe = zx_init_one, #ifdef CONFIG_PM_SLEEP - .suspend = ata_pci_device_suspend, - .resume = ata_pci_device_resume, + .suspend = ata_pci_device_suspend, + .resume = ata_pci_device_resume, #endif - .remove = ata_pci_remove_one, + .remove = ata_pci_remove_one, }; -static struct scsi_host_template szx_sht = { +static struct scsi_host_template zx_sht = { ATA_BMDMA_SHT(DRV_NAME), }; -static struct ata_port_operations szx_base_ops = { - .inherits = &ata_bmdma_port_ops, - .sff_tf_load = szx_tf_load, +static struct ata_port_operations zx_base_ops = { + .inherits = &ata_bmdma_port_ops, + .sff_tf_load = zx_tf_load, }; -static struct ata_port_operations cnd001_ops = { - .inherits = &szx_base_ops, - .hardreset = szx_hardreset, - .scr_read = cnd001_scr_read, - .scr_write = cnd001_scr_write, +static struct ata_port_operations zx_ops = { + .inherits = &zx_base_ops, + .hardreset = zx_hardreset, + .scr_read = zx_scr_read, + .scr_write = zx_scr_write, }; -static struct ata_port_info cnd001_port_info = { - .flags = ATA_FLAG_SATA | ATA_FLAG_SLAVE_POSS, - .pio_mask = ATA_PIO4, - .mwdma_mask = ATA_MWDMA2, - .udma_mask = ATA_UDMA6, - .port_ops = &cnd001_ops, +static struct ata_port_info zx100s_port_info = { + .flags = ATA_FLAG_SATA | ATA_FLAG_SLAVE_POSS, + .pio_mask = ATA_PIO4, + .mwdma_mask = ATA_MWDMA2, + .udma_mask = ATA_UDMA6, + .port_ops = &zx_ops, }; - -static int szx_hardreset(struct ata_link *link, unsigned int *class, - unsigned long deadline) +static int zx_hardreset(struct ata_link *link, unsigned int *class, unsigned long deadline) { int rc; @@ -105,22 +102,22 @@ static int szx_hardreset(struct ata_link *link, unsigned int *class, } else { tmprc = ata_sff_wait_ready(link, deadline); } + if (tmprc) - ata_link_err(link, "COMRESET failed for wait (errno=%d)\n", - rc); + ata_link_err(link, "COMRESET failed for wait (errno=%d)\n", rc); else ata_link_err(link, "wait for bsy success\n"); - ata_link_err(link, "COMRESET success (errno=%d) ap=%d link %d\n", - rc, link->ap->port_no, link->pmp); + ata_link_err(link, "COMRESET success (errno=%d) ap=%d link %d\n", rc, + link->ap->port_no, link->pmp); } else { - ata_link_err(link, "COMRESET failed (errno=%d) ap=%d link %d\n", - rc, link->ap->port_no, link->pmp); + ata_link_err(link, "COMRESET failed (errno=%d) ap=%d link %d\n", rc, + link->ap->port_no, link->pmp); } return rc; } -static int cnd001_scr_read(struct ata_link *link, unsigned int scr, u32 *val) +static int zx_scr_read(struct ata_link *link, unsigned int scr, u32 *val) { static const u8 ipm_tbl[] = { 1, 2, 6, 0 }; struct pci_dev *pdev = to_pci_dev(link->ap->host->dev); @@ -139,7 +136,7 @@ static int cnd001_scr_read(struct ata_link *link, unsigned int scr, u32 *val) v |= raw & 0x30; /* read the IPM field, bit2 and 3 of the config byte */ - v |= ((ipm_tbl[(raw >> 2) & 0x3])<<8); + v |= ((ipm_tbl[(raw >> 2) & 0x3]) << 8); break; case SCR_ERROR: @@ -168,7 +165,7 @@ static int cnd001_scr_read(struct ata_link *link, unsigned int scr, u32 *val) return 0; } -static int cnd001_scr_write(struct ata_link *link, unsigned int scr, u32 val) +static int zx_scr_write(struct ata_link *link, unsigned int scr, u32 val) { struct pci_dev *pdev = to_pci_dev(link->ap->host->dev); int slot = 2 * link->ap->port_no + link->pmp; @@ -191,10 +188,8 @@ static int cnd001_scr_write(struct ata_link *link, unsigned int scr, u32 val) /* set the IPM field */ v |= ((val >> 8) & 0x3) << 2; - pci_write_config_byte(pdev, 0xA4 + slot, v); - return 0; default: @@ -202,23 +197,22 @@ static int cnd001_scr_write(struct ata_link *link, unsigned int scr, u32 val) } } - /** - * szx_tf_load - send taskfile registers to host controller - * @ap: Port to which output is sent - * @tf: ATA taskfile register set + * zx_tf_load - send taskfile registers to host controller + * @ap: Port to which output is sent + * @tf: ATA taskfile register set * - * Outputs ATA taskfile to standard ATA host controller. + * Outputs ATA taskfile to standard ATA host controller. * - * This is to fix the internal bug of zx chipsets, which will - * reset the device register after changing the IEN bit on ctl - * register. + * This is to fix the internal bug of zx chipsets, which will + * reset the device register after changing the IEN bit on ctl + * register. */ -static void szx_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) +static void zx_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) { struct ata_taskfile ttf; - if (tf->ctl != ap->last_ctl) { + if (tf->ctl != ap->last_ctl) { ttf = *tf; ttf.flags |= ATA_TFLAG_DEVICE; tf = &ttf; @@ -226,26 +220,16 @@ static void szx_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) ata_sff_tf_load(ap, tf); } -static const unsigned int szx_bar_sizes[] = { - 8, 4, 8, 4, 16, 256 -}; +static const unsigned int zx_bar_sizes[] = { 8, 4, 8, 4, 16, 256 }; -static const unsigned int cnd001_bar_sizes0[] = { - 8, 4, 8, 4, 16, 0 -}; +static const unsigned int zx100s_bar_sizes0[] = { 8, 4, 8, 4, 16, 0 }; -static const unsigned int cnd001_bar_sizes1[] = { - 8, 4, 0, 0, 16, 0 -}; +static const unsigned int zx100s_bar_sizes1[] = { 8, 4, 0, 0, 16, 0 }; -static int cnd001_prepare_host(struct pci_dev *pdev, struct ata_host **r_host) +static int zx_prepare_host(struct pci_dev *pdev, struct ata_host **r_host) { - const struct ata_port_info *ppi0[] = { - &cnd001_port_info, NULL - }; - const struct ata_port_info *ppi1[] = { - &cnd001_port_info, &ata_dummy_port_info - }; + const struct ata_port_info *ppi0[] = { &zx100s_port_info, NULL }; + const struct ata_port_info *ppi1[] = { &zx100s_port_info, &ata_dummy_port_info }; struct ata_host *host; int i, rc; @@ -261,27 +245,28 @@ static int cnd001_prepare_host(struct pci_dev *pdev, struct ata_host **r_host) *r_host = host; - /* cnd001 9002 hosts four sata ports as M/S of the two channels */ - /* cnd001 9003 hosts two sata ports as M/S of the one channel */ + /* + * 9002 hosts four sata ports as M/S of the two channels + * 9003 hosts two sata ports as M/S of the one channel + */ for (i = 0; i < host->n_ports; i++) ata_slave_link_init(host->ports[i]); return 0; } -static void szx_configure(struct pci_dev *pdev, int board_id) +static void zx_configure(struct pci_dev *pdev, int board_id) { u8 tmp8; pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &tmp8); dev_info(&pdev->dev, "routed to hard irq line %d\n", - (int) (tmp8 & 0xf0) == 0xf0 ? 0 : tmp8 & 0x0f); + (int)(tmp8 & 0xf0) == 0xf0 ? 0 : tmp8 & 0x0f); /* make sure SATA channels are enabled */ pci_read_config_byte(pdev, SATA_CHAN_ENAB, &tmp8); if ((tmp8 & ALL_PORTS) != ALL_PORTS) { - dev_dbg(&pdev->dev, "enabling SATA channels (0x%x)\n", - (int)tmp8); + dev_dbg(&pdev->dev, "enabling SATA channels (0x%x)\n", (int)tmp8); tmp8 |= ALL_PORTS; pci_write_config_byte(pdev, SATA_CHAN_ENAB, tmp8); } @@ -289,8 +274,7 @@ static void szx_configure(struct pci_dev *pdev, int board_id) /* make sure interrupts for each channel sent to us */ pci_read_config_byte(pdev, SATA_INT_GATE, &tmp8); if ((tmp8 & ALL_PORTS) != ALL_PORTS) { - dev_dbg(&pdev->dev, "enabling SATA channel interrupts (0x%x)\n", - (int) tmp8); + dev_dbg(&pdev->dev, "enabling SATA channel interrupts (0x%x)\n", (int)tmp8); tmp8 |= ALL_PORTS; pci_write_config_byte(pdev, SATA_INT_GATE, tmp8); } @@ -298,20 +282,18 @@ static void szx_configure(struct pci_dev *pdev, int board_id) /* make sure native mode is enabled */ pci_read_config_byte(pdev, SATA_NATIVE_MODE, &tmp8); if ((tmp8 & NATIVE_MODE_ALL) != NATIVE_MODE_ALL) { - dev_dbg(&pdev->dev, - "enabling SATA channel native mode (0x%x)\n", - (int) tmp8); + dev_dbg(&pdev->dev, "enabling SATA channel native mode (0x%x)\n", (int)tmp8); tmp8 |= NATIVE_MODE_ALL; pci_write_config_byte(pdev, SATA_NATIVE_MODE, tmp8); } } -static int szx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) +static int zx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) { unsigned int i; int rc; struct ata_host *host = NULL; - int board_id = (int) ent->driver_data; + int board_id = (int)ent->driver_data; const unsigned int *bar_sizes; int legacy_mode = 0; @@ -335,22 +317,20 @@ static int szx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) if (rc) return rc; - if (board_id == cnd001 && pdev->device == 0x9002) - bar_sizes = &cnd001_bar_sizes0[0]; - else if (board_id == cnd001 && pdev->device == 0x9003) - bar_sizes = &cnd001_bar_sizes1[0]; + if (board_id == zx100s && pdev->device == 0x9002) + bar_sizes = &zx100s_bar_sizes0[0]; + else if (board_id == zx100s && pdev->device == 0x9003) + bar_sizes = &zx100s_bar_sizes1[0]; else - bar_sizes = &szx_bar_sizes[0]; + bar_sizes = &zx_bar_sizes[0]; - for (i = 0; i < ARRAY_SIZE(szx_bar_sizes); i++) { + for (i = 0; i < ARRAY_SIZE(zx_bar_sizes); i++) { if ((pci_resource_start(pdev, i) == 0) || - (pci_resource_len(pdev, i) < bar_sizes[i])) { + (pci_resource_len(pdev, i) < bar_sizes[i])) { if (bar_sizes[i] == 0) continue; - dev_err(&pdev->dev, - "invalid PCI BAR %u (sz 0x%llx, val 0x%llx)\n", - i, + dev_err(&pdev->dev, "invalid PCI BAR %u (sz 0x%llx, val 0x%llx)\n", i, (unsigned long long)pci_resource_start(pdev, i), (unsigned long long)pci_resource_len(pdev, i)); @@ -359,8 +339,8 @@ static int szx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) } switch (board_id) { - case cnd001: - rc = cnd001_prepare_host(pdev, &host); + case zx100s: + rc = zx_prepare_host(pdev, &host); break; default: rc = -EINVAL; @@ -368,17 +348,16 @@ static int szx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) if (rc) return rc; - szx_configure(pdev, board_id); + zx_configure(pdev, board_id); pci_set_master(pdev); - return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, - IRQF_SHARED, &szx_sht); + return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, IRQF_SHARED, &zx_sht); } -module_pci_driver(szx_pci_driver); +module_pci_driver(zx_pci_driver); -MODULE_AUTHOR("Yanchen:YanchenSun@zhaoxin.com"); +MODULE_AUTHOR("Yanchen "); MODULE_DESCRIPTION("SCSI low-level driver for ZX SATA controllers"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(pci, szx_pci_tbl); +MODULE_DEVICE_TABLE(pci, zx_pci_tbl); MODULE_VERSION(DRV_VERSION); -- Gitee