diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 0ae04fb660069003a582ccfd28be93a492e6d64e..2bede86a0e9848b9e6c4502033a1730ae0bb1de3 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -54,7 +54,8 @@ config CRYPTO_DEV_PADLOCK_SHA
 
 config CRYPTO_DEV_ZHAOXIN
 	tristate "Support for Zhaoxin ACE"
-	depends on X86 && !UML
+	depends on X86 && !UML && (CPU_SUP_ZHAOXIN || CPU_SUP_CENTAUR)
+	default m
 	help
 	  Some Zhaoxin processors come with an integrated crypto engine
 	  (so called Zhaoxin ACE, Advanced Cryptography Engine)
@@ -67,6 +68,7 @@ config CRYPTO_DEV_ZHAOXIN
 config CRYPTO_DEV_ZHAOXIN_AES
 	tristate "Zhaoxin ACE driver for AES algorithm"
 	depends on CRYPTO_DEV_ZHAOXIN
+	default CRYPTO_DEV_ZHAOXIN
 	select CRYPTO_BLKCIPHER
 	select CRYPTO_AES
 	help
@@ -80,6 +82,7 @@ config CRYPTO_DEV_ZHAOXIN_AES
 config CRYPTO_DEV_ZHAOXIN_SHA
 	tristate "Zhaoxin ACE driver for SHA1 and SHA256 algorithms"
 	depends on CRYPTO_DEV_ZHAOXIN
+	default CRYPTO_DEV_ZHAOXIN
 	select CRYPTO_HASH
 	select CRYPTO_SHA1
 	select CRYPTO_SHA256
diff --git a/drivers/crypto/padlock-aes.c b/drivers/crypto/padlock-aes.c
index f0c3127941ae2f5cea71a4041aafc3e617af2df9..eb5f9ede109083a4c55f11cd277f91e81cdf94ba 100644
--- a/drivers/crypto/padlock-aes.c
+++ b/drivers/crypto/padlock-aes.c
@@ -475,7 +475,7 @@ static struct skcipher_alg cbc_aes_alg = {
 };
 
 static const struct x86_cpu_id padlock_cpu_id[] = {
-	{ X86_VENDOR_CENTAUR, 6, X86_MODEL_ANY, X86_FEATURE_XCRYPT },
+	X86_MATCH_VENDOR_FAM_FEATURE(CENTAUR, 6, X86_FEATURE_XCRYPT, NULL),
 	{}
 };
 MODULE_DEVICE_TABLE(x86cpu, padlock_cpu_id);
diff --git a/drivers/crypto/padlock-sha.c b/drivers/crypto/padlock-sha.c
index 04858dc8b59794beabd98dbdfe59a2b1e1305a1a..2e82c5e77f7ac655b6914f77cd18fe03817b7672 100644
--- a/drivers/crypto/padlock-sha.c
+++ b/drivers/crypto/padlock-sha.c
@@ -491,7 +491,7 @@ static struct shash_alg sha256_alg_nano = {
 };
 
 static const struct x86_cpu_id padlock_sha_ids[] = {
-	{ X86_VENDOR_CENTAUR, 6, X86_MODEL_ANY, X86_FEATURE_PHE },
+	X86_MATCH_VENDOR_FAM_FEATURE(CENTAUR, 6, X86_FEATURE_PHE, NULL),
 	{}
 };
 MODULE_DEVICE_TABLE(x86cpu, padlock_sha_ids);
diff --git a/drivers/crypto/zhaoxin-aes.c b/drivers/crypto/zhaoxin-aes.c
index 5135f23e150b93cb31d28e4b2d515451b49f2bbb..be9656455e2d82f06ec5dc36fd9f12e50bbb2b48 100644
--- a/drivers/crypto/zhaoxin-aes.c
+++ b/drivers/crypto/zhaoxin-aes.c
@@ -62,7 +62,7 @@ struct aes_ctx {
 	u32 *D;
 };
 
-static DEFINE_PER_CPU(struct cword *, paes_last_cword);
+static DEFINE_PER_CPU(struct cword *, zx_paes_last_cword);
 
 /* Tells whether the ACE is capable to generate the extended key for a given key_len. */
 static inline int aes_hw_extkey_available(uint8_t key_len)
@@ -142,9 +142,9 @@ static int aes_set_key(struct crypto_tfm *tfm, const u8 *in_key, unsigned int ke
 
 ok:
 	for_each_online_cpu(cpu)
-		if (&ctx->cword.encrypt == per_cpu(paes_last_cword, cpu) ||
-			&ctx->cword.decrypt == per_cpu(paes_last_cword, cpu))
-			per_cpu(paes_last_cword, cpu) = NULL;
+		if (&ctx->cword.encrypt == per_cpu(zx_paes_last_cword, cpu) ||
+			&ctx->cword.decrypt == per_cpu(zx_paes_last_cword, cpu))
+			per_cpu(zx_paes_last_cword, cpu) = NULL;
 
 	return 0;
 }
@@ -162,7 +162,7 @@ static inline void padlock_reset_key(struct cword *cword)
 {
 	int cpu = raw_smp_processor_id();
 
-	if (cword != per_cpu(paes_last_cword, cpu))
+	if (cword != per_cpu(zx_paes_last_cword, cpu))
 #ifndef CONFIG_X86_64
 		asm volatile ("pushfl; popfl");
 #else
@@ -172,7 +172,7 @@ static inline void padlock_reset_key(struct cword *cword)
 
 static inline void padlock_store_cword(struct cword *cword)
 {
-	per_cpu(paes_last_cword, raw_smp_processor_id()) = cword;
+	per_cpu(zx_paes_last_cword, raw_smp_processor_id()) = cword;
 }
 
 /*
@@ -460,18 +460,19 @@ static struct skcipher_alg cbc_aes_alg = {
 	.decrypt		=	cbc_aes_decrypt,
 };
 
-static const struct x86_cpu_id zhaoxin_cpu_id[] = {
-	{ X86_VENDOR_CENTAUR, 7, X86_MODEL_ANY, X86_STEPPING_ANY, X86_FEATURE_XCRYPT },
-	{ X86_VENDOR_ZHAOXIN, 7, X86_MODEL_ANY, X86_STEPPING_ANY, X86_FEATURE_XCRYPT },
+static const struct x86_cpu_id zhaoxin_aes_cpu_ids[] = {
+	X86_MATCH_VENDOR_FAM_FEATURE(CENTAUR, 7, X86_FEATURE_XCRYPT, NULL),
+	X86_MATCH_VENDOR_FAM_FEATURE(ZHAOXIN, 7, X86_FEATURE_XCRYPT, NULL),
+	X86_MATCH_VENDOR_FAM_FEATURE(ZHAOXIN, 6, X86_FEATURE_XCRYPT, NULL),
 	{}
 };
-MODULE_DEVICE_TABLE(x86cpu, zhaoxin_cpu_id);
+MODULE_DEVICE_TABLE(x86cpu, zhaoxin_aes_cpu_ids);
 
 static int __init padlock_init(void)
 {
 	int ret;
 
-	if (!x86_match_cpu(zhaoxin_cpu_id))
+	if (!x86_match_cpu(zhaoxin_aes_cpu_ids))
 		return -ENODEV;
 
 	if (!boot_cpu_has(X86_FEATURE_XCRYPT_EN)) {
diff --git a/drivers/crypto/zhaoxin-sha.c b/drivers/crypto/zhaoxin-sha.c
index 840805f36838e5a2bf6791684e67f35d8698da90..9e5809cf519f75eb5c112a5e86b1412862083ef4 100644
--- a/drivers/crypto/zhaoxin-sha.c
+++ b/drivers/crypto/zhaoxin-sha.c
@@ -245,12 +245,13 @@ static struct shash_alg sha256_alg_zhaoxin = {
 	}
 };
 
-static const struct x86_cpu_id zhaoxin_sha_ids[] = {
-	{ X86_VENDOR_CENTAUR, 7, X86_MODEL_ANY, X86_STEPPING_ANY, X86_FEATURE_PHE },
-	{ X86_VENDOR_ZHAOXIN, 7, X86_MODEL_ANY, X86_STEPPING_ANY, X86_FEATURE_PHE },
+static const struct x86_cpu_id zhaoxin_sha_cpu_ids[] = {
+	X86_MATCH_VENDOR_FAM_FEATURE(CENTAUR, 7, X86_FEATURE_PHE, NULL),
+	X86_MATCH_VENDOR_FAM_FEATURE(ZHAOXIN, 7, X86_FEATURE_PHE, NULL),
+	X86_MATCH_VENDOR_FAM_FEATURE(ZHAOXIN, 6, X86_FEATURE_PHE, NULL),
 	{}
 };
-MODULE_DEVICE_TABLE(x86cpu, zhaoxin_sha_ids);
+MODULE_DEVICE_TABLE(x86cpu, zhaoxin_sha_cpu_ids);
 
 static int __init padlock_init(void)
 {
@@ -258,7 +259,7 @@ static int __init padlock_init(void)
 	struct shash_alg *sha1;
 	struct shash_alg *sha256;
 
-	if (!x86_match_cpu(zhaoxin_sha_ids) || !boot_cpu_has(X86_FEATURE_PHE_EN))
+	if (!x86_match_cpu(zhaoxin_sha_cpu_ids) || !boot_cpu_has(X86_FEATURE_PHE_EN))
 		return -ENODEV;
 
 	sha1 = &sha1_alg_zhaoxin;