From a5f99081c357e74a2446628d0f1e3464bc184716 Mon Sep 17 00:00:00 2001 From: ge_nan Date: Fri, 14 Mar 2025 12:08:25 +0800 Subject: [PATCH] kernel.patch update for dayu210 Signed-off-by: ge_nan --- .../linux-5.10/dayu210_patch/kernel.patch | 1778 +++++++++++++---- 1 file changed, 1339 insertions(+), 439 deletions(-) diff --git a/dayu210/kernel/kernel_patch/linux-5.10/dayu210_patch/kernel.patch b/dayu210/kernel/kernel_patch/linux-5.10/dayu210_patch/kernel.patch index 85b00fd..11fc7cc 100755 --- a/dayu210/kernel/kernel_patch/linux-5.10/dayu210_patch/kernel.patch +++ b/dayu210/kernel/kernel_patch/linux-5.10/dayu210_patch/kernel.patch @@ -70952,445 +70952,1345 @@ index 000000000..09a6a54ae +#define ARMCLK_B01 11 +#define ARMCLK_B23 12 + - static inline bool gic_enable_sre(void) - { - u32 val; -@@ -708,6 +722,8 @@ static inline bool gic_enable_sre(void) - return !!(val & ICC_SRE_EL1_SRE); - } - -+void gic_resume(void); -+ - #endif - - #endif -diff --git a/include/linux/irqchip/arm-gic-v4.h b/include/linux/irqchip/arm-gic-v4.h -index 6976b8331..943c3411c 100644 ---- a/include/linux/irqchip/arm-gic-v4.h -+++ b/include/linux/irqchip/arm-gic-v4.h -@@ -39,6 +39,8 @@ struct its_vpe { - irq_hw_number_t vpe_db_lpi; - /* VPE resident */ - bool resident; -+ /* VPT parse complete */ -+ bool ready; - union { - /* GICv4.0 implementations */ - struct { -@@ -104,6 +106,7 @@ enum its_vcpu_info_cmd_type { - PROP_UPDATE_AND_INV_VLPI, - SCHEDULE_VPE, - DESCHEDULE_VPE, -+ COMMIT_VPE, - INVALL_VPE, - PROP_UPDATE_VSGI, - }; -@@ -129,6 +132,7 @@ int its_alloc_vcpu_irqs(struct its_vm *vm); - void its_free_vcpu_irqs(struct its_vm *vm); - int its_make_vpe_resident(struct its_vpe *vpe, bool g0en, bool g1en); - int its_make_vpe_non_resident(struct its_vpe *vpe, bool db); -+int its_commit_vpe(struct its_vpe *vpe); - int its_invall_vpe(struct its_vpe *vpe); - int its_map_vlpi(int irq, struct its_vlpi_map *map); - int its_get_vlpi(int irq, struct its_vlpi_map *map); -diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h -index e07f6e61c..7cdc5dfa4 100644 ---- a/include/linux/mfd/rk808.h -+++ b/include/linux/mfd/rk808.h -@@ -113,6 +113,235 @@ enum rk808_reg { - #define RK808_INT_STS_MSK_REG2 0x4f - #define RK808_IO_POL_REG 0x50 - -+/* RK816 */ -+enum rk816_reg { -+ RK816_ID_DCDC1, -+ RK816_ID_DCDC2, -+ RK816_ID_DCDC3, -+ RK816_ID_DCDC4, -+ RK816_ID_LDO1, -+ RK816_ID_LDO2, -+ RK816_ID_LDO3, -+ RK816_ID_LDO4, -+ RK816_ID_LDO5, -+ RK816_ID_LDO6, -+}; -+ -+/*VERSION REGISTER*/ -+#define RK816_CHIP_NAME_REG 0x17 -+#define RK816_CHIP_VER_REG 0x18 -+#define RK816_OTP_VER_REG 0x19 -+#define RK816_NUM_REGULATORS 10 -+ -+/*POWER ON/OFF REGISTER*/ -+#define RK816_VB_MON_REG 0x21 -+#define RK816_THERMAL_REG 0x22 -+#define RK816_PWRON_LP_INT_TIME_REG 0x47 -+#define RK816_PWRON_DB_REG 0x48 -+#define RK816_DEV_CTRL_REG 0x4B -+#define RK816_ON_SOURCE_REG 0xAE -+#define RK816_OFF_SOURCE_REG 0xAF -+ -+/*POWER CHANNELS ENABLE REGISTER*/ -+#define RK816_DCDC_EN_REG1 0x23 -+#define RK816_DCDC_EN_REG2 0x24 -+#define RK816_SLP_DCDC_EN_REG 0x25 -+#define RK816_SLP_LDO_EN_REG 0x26 -+#define RK816_LDO_EN_REG1 0x27 -+#define RK816_LDO_EN_REG2 0x28 -+ -+/*BUCK AND LDO CONFIG REGISTER*/ -+#define RK816_BUCK1_CONFIG_REG 0x2E -+#define RK816_BUCK1_ON_VSEL_REG 0x2F -+#define RK816_BUCK1_SLP_VSEL_REG 0x30 -+#define RK816_BUCK2_CONFIG_REG 0x32 -+#define RK816_BUCK2_ON_VSEL_REG 0x33 -+#define RK816_BUCK2_SLP_VSEL_REG 0x34 -+#define RK816_BUCK3_CONFIG_REG 0x36 -+#define RK816_BUCK4_CONFIG_REG 0x37 -+#define RK816_BUCK4_ON_VSEL_REG 0x38 -+#define RK816_BUCK4_SLP_VSEL_REG 0x39 -+#define RK816_LDO1_ON_VSEL_REG 0x3B -+#define RK816_LDO1_SLP_VSEL_REG 0x3C -+#define RK816_LDO2_ON_VSEL_REG 0x3D -+#define RK816_LDO2_SLP_VSEL_REG 0x3E -+#define RK816_LDO3_ON_VSEL_REG 0x3F -+#define RK816_LDO3_SLP_VSEL_REG 0x40 -+#define RK816_LDO4_ON_VSEL_REG 0x41 -+#define RK816_LDO4_SLP_VSEL_REG 0x42 -+#define RK816_LDO5_ON_VSEL_REG 0x43 -+#define RK816_LDO5_SLP_VSEL_REG 0x44 -+#define RK816_LDO6_ON_VSEL_REG 0x45 -+#define RK816_LDO6_SLP_VSEL_REG 0x46 -+#define RK816_GPIO_IO_POL_REG 0x50 -+ -+/*CHARGER BOOST AND OTG REGISTER*/ -+#define RK816_OTG_BUCK_LDO_CONFIG_REG 0x2A -+#define RK816_CHRG_CONFIG_REG 0x2B -+#define RK816_BOOST_ON_VESL_REG 0x54 -+#define RK816_BOOST_SLP_VSEL_REG 0x55 -+#define RK816_CHRG_BOOST_CONFIG_REG 0x9A -+#define RK816_SUP_STS_REG 0xA0 -+#define RK816_USB_CTRL_REG 0xA1 -+#define RK816_CHRG_CTRL_REG1 0xA3 -+#define RK816_CHRG_CTRL_REG2 0xA4 -+#define RK816_CHRG_CTRL_REG3 0xA5 -+#define RK816_BAT_CTRL_REG 0xA6 -+#define RK816_BAT_HTS_TS_REG 0xA8 -+#define RK816_BAT_LTS_TS_REG 0xA9 -+ -+#define RK816_TS_CTRL_REG 0xAC -+#define RK816_ADC_CTRL_REG 0xAD -+#define RK816_GGCON_REG 0xB0 -+#define RK816_GGSTS_REG 0xB1 -+#define RK816_ZERO_CUR_ADC_REGH 0xB2 -+#define RK816_ZERO_CUR_ADC_REGL 0xB3 -+#define RK816_GASCNT_CAL_REG3 0xB4 -+#define RK816_GASCNT_CAL_REG2 0xB5 -+#define RK816_GASCNT_CAL_REG1 0xB6 -+#define RK816_GASCNT_CAL_REG0 0xB7 -+#define RK816_GASCNT_REG3 0xB8 -+#define RK816_GASCNT_REG2 0xB9 -+#define RK816_GASCNT_REG1 0xBA -+#define RK816_GASCNT_REG0 0xBB -+#define RK816_BAT_CUR_AVG_REGH 0xBC -+#define RK816_BAT_CUR_AVG_REGL 0xBD -+#define RK816_TS_ADC_REGH 0xBE -+#define RK816_TS_ADC_REGL 0xBF -+#define RK816_USB_ADC_REGH 0xC0 -+#define RK816_USB_ADC_REGL 0xC1 -+#define RK816_BAT_OCV_REGH 0xC2 -+#define RK816_BAT_OCV_REGL 0xC3 -+#define RK816_BAT_VOL_REGH 0xC4 -+#define RK816_BAT_VOL_REGL 0xC5 -+#define RK816_RELAX_ENTRY_THRES_REGH 0xC6 -+#define RK816_RELAX_ENTRY_THRES_REGL 0xC7 -+#define RK816_RELAX_EXIT_THRES_REGH 0xC8 -+#define RK816_RELAX_EXIT_THRES_REGL 0xC9 -+#define RK816_RELAX_VOL1_REGH 0xCA -+#define RK816_RELAX_VOL1_REGL 0xCB -+#define RK816_RELAX_VOL2_REGH 0xCC -+#define RK816_RELAX_VOL2_REGL 0xCD -+#define RK816_RELAX_CUR1_REGH 0xCE -+#define RK816_RELAX_CUR1_REGL 0xCF -+#define RK816_RELAX_CUR2_REGH 0xD0 -+#define RK816_RELAX_CUR2_REGL 0xD1 -+#define RK816_CAL_OFFSET_REGH 0xD2 -+#define RK816_CAL_OFFSET_REGL 0xD3 -+#define RK816_NON_ACT_TIMER_CNT_REG 0xD4 -+#define RK816_VCALIB0_REGH 0xD5 -+#define RK816_VCALIB0_REGL 0xD6 -+#define RK816_VCALIB1_REGH 0xD7 -+#define RK816_VCALIB1_REGL 0xD8 -+#define RK816_FCC_GASCNT_REG3 0xD9 -+#define RK816_FCC_GASCNT_REG2 0xDA -+#define RK816_FCC_GASCNT_REG1 0xDB -+#define RK816_FCC_GASCNT_REG0 0xDC -+#define RK816_IOFFSET_REGH 0xDD -+#define RK816_IOFFSET_REGL 0xDE -+#define RK816_SLEEP_CON_SAMP_CUR_REG 0xDF -+ -+/*DATA REGISTER*/ -+#define RK816_SOC_REG 0xE0 -+#define RK816_REMAIN_CAP_REG3 0xE1 -+#define RK816_REMAIN_CAP_REG2 0xE2 -+#define RK816_REMAIN_CAP_REG1 0xE3 -+#define RK816_REMAIN_CAP_REG0 0xE4 -+#define RK816_UPDATE_LEVE_REG 0xE5 -+#define RK816_NEW_FCC_REG3 0xE6 -+#define RK816_NEW_FCC_REG2 0xE7 -+#define RK816_NEW_FCC_REG1 0xE8 -+#define RK816_NEW_FCC_REG0 0xE9 -+#define RK816_NON_ACT_TIMER_CNT_REG_SAVE 0xEA -+#define RK816_OCV_VOL_VALID_REG 0xEB -+#define RK816_REBOOT_CNT_REG 0xEC -+#define RK816_PCB_IOFFSET_REG 0xED -+#define RK816_MISC_MARK_REG 0xEE -+#define RK816_HALT_CNT_REG 0xEF -+#define RK816_CALC_REST_REGH 0xF0 -+#define RK816_CALC_REST_REGL 0xF1 -+#define DATA18_REG 0xF2 -+ -+/*INTERRUPT REGISTER*/ -+#define RK816_INT_STS_REG1 0x49 -+#define RK816_INT_STS_MSK_REG1 0x4A -+#define RK816_INT_STS_REG2 0x4C -+#define RK816_INT_STS_MSK_REG2 0x4D -+#define RK816_INT_STS_REG3 0x4E -+#define RK816_INT_STS_MSK_REG3 0x4F -+#define RK816_GPIO_IO_POL_REG 0x50 -+ -+#define RK816_DATA18_REG 0xF2 -+ -+/* IRQ Definitions */ -+#define RK816_IRQ_PWRON_FALL 0 -+#define RK816_IRQ_PWRON_RISE 1 -+#define RK816_IRQ_VB_LOW 2 -+#define RK816_IRQ_PWRON 3 -+#define RK816_IRQ_PWRON_LP 4 -+#define RK816_IRQ_HOTDIE 5 -+#define RK816_IRQ_RTC_ALARM 6 -+#define RK816_IRQ_RTC_PERIOD 7 -+#define RK816_IRQ_USB_OV 8 -+#define RK816_IRQ_PLUG_IN 9 -+#define RK816_IRQ_PLUG_OUT 10 -+#define RK816_IRQ_CHG_OK 11 -+#define RK816_IRQ_CHG_TE 12 -+#define RK816_IRQ_CHG_TS 13 -+#define RK816_IRQ_CHG_CVTLIM 14 -+#define RK816_IRQ_DISCHG_ILIM 15 -+ -+#define RK816_IRQ_PWRON_FALL_MSK BIT(5) -+#define RK816_IRQ_PWRON_RISE_MSK BIT(6) -+#define RK816_IRQ_VB_LOW_MSK BIT(1) -+#define RK816_IRQ_PWRON_MSK BIT(2) -+#define RK816_IRQ_PWRON_LP_MSK BIT(3) -+#define RK816_IRQ_HOTDIE_MSK BIT(4) -+#define RK816_IRQ_RTC_ALARM_MSK BIT(5) -+#define RK816_IRQ_RTC_PERIOD_MSK BIT(6) -+#define RK816_IRQ_USB_OV_MSK BIT(7) -+#define RK816_IRQ_PLUG_IN_MSK BIT(0) -+#define RK816_IRQ_PLUG_OUT_MSK BIT(1) -+#define RK816_IRQ_CHG_OK_MSK BIT(2) -+#define RK816_IRQ_CHG_TE_MSK BIT(3) -+#define RK816_IRQ_CHG_TS_MSK BIT(4) -+#define RK816_IRQ_CHG_CVTLIM_MSK BIT(6) -+#define RK816_IRQ_DISCHG_ILIM_MSK BIT(7) -+ -+#define RK816_VBAT_LOW_2V8 0x00 -+#define RK816_VBAT_LOW_2V9 0x01 -+#define RK816_VBAT_LOW_3V0 0x02 -+#define RK816_VBAT_LOW_3V1 0x03 -+#define RK816_VBAT_LOW_3V2 0x04 -+#define RK816_VBAT_LOW_3V3 0x05 -+#define RK816_VBAT_LOW_3V4 0x06 -+#define RK816_VBAT_LOW_3V5 0x07 -+#define RK816_PWR_FALL_INT_STATUS (0x1 << 5) -+#define RK816_PWR_RISE_INT_STATUS (0x1 << 6) -+#define RK816_ALARM_INT_STATUS (0x1 << 5) -+#define EN_VBAT_LOW_IRQ (0x1 << 4) -+#define VBAT_LOW_ACT_MASK (0x1 << 4) -+#define RTC_TIMER_ALARM_INT_MSK (0x3 << 2) -+#define RTC_TIMER_ALARM_INT_DIS (0x0 << 2) -+#define RTC_PERIOD_ALARM_INT_MSK (0x3 << 5) -+#define RTC_PERIOD_ALARM_INT_ST (0x3 << 5) -+#define RTC_PERIOD_ALARM_INT_DIS (0x3 << 5) -+#define RTC_PERIOD_ALARM_INT_EN (0x9f) -+#define REG_WRITE_MSK 0xff -+#define BUCK4_MAX_ILIMIT 0x2c -+#define BUCK_RATE_MSK (0x3 << 3) -+#define BUCK_RATE_12_5MV_US (0x2 << 3) -+#define ALL_INT_FLAGS_ST 0xff -+#define PLUGIN_OUT_INT_EN 0xfc -+#define RK816_PWRON_FALL_RISE_INT_EN 0x9f -+#define BUCK1_2_IMAX_MAX (0x3 << 6) -+#define BUCK3_4_IMAX_MAX (0x3 << 3) -+#define BOOST_DISABLE ((0x1 << 5) | (0x0 << 1)) -+#define BUCK4_VRP_3PERCENT 0xc0 -+#define RK816_BUCK_DVS_CONFIRM (0x1 << 7) -+#define RK816_TYPE_ES2 0x05 -+#define RK816_CHIP_VERSION_MASK 0x0f -+ - /* RK818 */ - #define RK818_DCDC1 0 - #define RK818_LDO1 4 -@@ -138,6 +367,8 @@ enum rk818_reg { - RK818_ID_OTG_SWITCH, - }; - -+#define RK818_VB_MON_REG 0x21 -+#define RK818_THERMAL_REG 0x22 - #define RK818_DCDC_EN_REG 0x23 - #define RK818_LDO_EN_REG 0x24 - #define RK818_SLEEP_SET_OFF_REG1 0x25 -@@ -190,7 +421,84 @@ enum rk818_reg { - #define RK818_BOOST_LDO9_SLP_VSEL_REG 0x55 - #define RK818_BOOST_CTRL_REG 0x56 - #define RK818_DCDC_ILMAX 0x90 -+#define RK818_CHRG_COMP_REG 0x9a -+#define RK818_SUP_STS_REG 0xa0 - #define RK818_USB_CTRL_REG 0xa1 -+#define RK818_CHRG_CTRL_REG1 0xa3 -+#define RK818_CHRG_CTRL_REG2 0xa4 -+#define RK818_CHRG_CTRL_REG3 0xa5 -+#define RK818_BAT_CTRL_REG 0xa6 -+#define RK818_BAT_HTS_TS1_REG 0xa8 -+#define RK818_BAT_LTS_TS1_REG 0xa9 -+#define RK818_BAT_HTS_TS2_REG 0xaa -+#define RK818_BAT_LTS_TS2_REG 0xab -+#define RK818_TS_CTRL_REG 0xac -+#define RK818_ADC_CTRL_REG 0xad -+#define RK818_ON_SOURCE_REG 0xae -+#define RK818_OFF_SOURCE_REG 0xaf -+#define RK818_GGCON_REG 0xb0 -+#define RK818_GGSTS_REG 0xb1 -+#define RK818_FRAME_SMP_INTERV_REG 0xb2 -+#define RK818_AUTO_SLP_CUR_THR_REG 0xb3 -+#define RK818_GASCNT_CAL_REG3 0xb4 -+#define RK818_GASCNT_CAL_REG2 0xb5 -+#define RK818_GASCNT_CAL_REG1 0xb6 -+#define RK818_GASCNT_CAL_REG0 0xb7 -+#define RK818_GASCNT3_REG 0xb8 -+#define RK818_GASCNT2_REG 0xb9 -+#define RK818_GASCNT1_REG 0xba -+#define RK818_GASCNT0_REG 0xbb -+#define RK818_BAT_CUR_AVG_REGH 0xbc -+#define RK818_BAT_CUR_AVG_REGL 0xbd -+#define RK818_TS1_ADC_REGH 0xbe -+#define RK818_TS1_ADC_REGL 0xbf -+#define RK818_TS2_ADC_REGH 0xc0 -+#define RK818_TS2_ADC_REGL 0xc1 -+#define RK818_BAT_OCV_REGH 0xc2 -+#define RK818_BAT_OCV_REGL 0xc3 -+#define RK818_BAT_VOL_REGH 0xc4 -+#define RK818_BAT_VOL_REGL 0xc5 -+#define RK818_RELAX_ENTRY_THRES_REGH 0xc6 -+#define RK818_RELAX_ENTRY_THRES_REGL 0xc7 -+#define RK818_RELAX_EXIT_THRES_REGH 0xc8 -+#define RK818_RELAX_EXIT_THRES_REGL 0xc9 -+#define RK818_RELAX_VOL1_REGH 0xca -+#define RK818_RELAX_VOL1_REGL 0xcb -+#define RK818_RELAX_VOL2_REGH 0xcc -+#define RK818_RELAX_VOL2_REGL 0xcd -+#define RK818_BAT_CUR_R_CALC_REGH 0xce -+#define RK818_BAT_CUR_R_CALC_REGL 0xcf -+#define RK818_BAT_VOL_R_CALC_REGH 0xd0 -+#define RK818_BAT_VOL_R_CALC_REGL 0xd1 -+#define RK818_CAL_OFFSET_REGH 0xd2 -+#define RK818_CAL_OFFSET_REGL 0xd3 -+#define RK818_NON_ACT_TIMER_CNT_REG 0xd4 -+#define RK818_VCALIB0_REGH 0xd5 -+#define RK818_VCALIB0_REGL 0xd6 -+#define RK818_VCALIB1_REGH 0xd7 -+#define RK818_VCALIB1_REGL 0xd8 -+#define RK818_IOFFSET_REGH 0xdd -+#define RK818_IOFFSET_REGL 0xde -+#define RK818_SOC_REG 0xe0 -+#define RK818_REMAIN_CAP_REG3 0xe1 -+#define RK818_REMAIN_CAP_REG2 0xe2 -+#define RK818_REMAIN_CAP_REG1 0xe3 -+#define RK818_REMAIN_CAP_REG0 0xe4 -+#define RK818_UPDAT_LEVE_REG 0xe5 -+#define RK818_NEW_FCC_REG3 0xe6 -+#define RK818_NEW_FCC_REG2 0xe7 -+#define RK818_NEW_FCC_REG1 0xe8 -+#define RK818_NEW_FCC_REG0 0xe9 -+#define RK818_NON_ACT_TIMER_CNT_SAVE_REG 0xea -+#define RK818_OCV_VOL_VALID_REG 0xeb -+#define RK818_REBOOT_CNT_REG 0xec -+#define RK818_POFFSET_REG 0xed -+#define RK818_MISC_MARK_REG 0xee -+#define RK818_HALT_CNT_REG 0xef -+#define RK818_CALC_REST_REGH 0xf0 -+#define RK818_CALC_REST_REGL 0xf1 -+#define RK818_SAVE_DATA19 0xf2 -+#define RK818_NUM_REGULATOR 17 - - #define RK818_H5V_EN BIT(0) - #define RK818_REF_RDY_CTRL BIT(1) -@@ -255,14 +563,22 @@ enum rk805_reg { - #define RK805_PWRON_FALL_RISE_INT_MSK 0x81 - - /* RK805 IRQ Definitions */ --#define RK805_IRQ_PWRON_RISE 0 - #define RK805_IRQ_VB_LOW 1 - #define RK805_IRQ_PWRON 2 - #define RK805_IRQ_PWRON_LP 3 - #define RK805_IRQ_HOTDIE 4 - #define RK805_IRQ_RTC_ALARM 5 - #define RK805_IRQ_RTC_PERIOD 6 --#define RK805_IRQ_PWRON_FALL 7 -+ -+/* -+ * When PMIC irq occurs, regmap-irq.c will traverse all PMIC child -+ * interrupts from low index 0 to high index, we give fall interrupt -+ * high priority to be called earlier than rise, so that it can be -+ * override by late rise event. This can helps to solve key release -+ * glitch which make a wrongly fall event immediately after rise. -+ */ -+#define RK805_IRQ_PWRON_FALL 0 -+#define RK805_IRQ_PWRON_RISE 7 - - #define RK805_IRQ_PWRON_RISE_MSK BIT(0) - #define RK805_IRQ_VB_LOW_MSK BIT(1) -@@ -289,6 +605,16 @@ enum rk805_reg { - #define RK805_INT_ALARM_EN (1 << 3) - #define RK805_INT_TIMER_EN (1 << 2) - -+#define RK805_SLP_LDO_EN_OFFSET -1 -+#define RK805_SLP_DCDC_EN_OFFSET 2 -+ -+#define RK805_RAMP_RATE_OFFSET 3 -+#define RK805_RAMP_RATE_MASK (3 << RK805_RAMP_RATE_OFFSET) -+#define RK805_RAMP_RATE_3MV_PER_US (0 << RK805_RAMP_RATE_OFFSET) -+#define RK805_RAMP_RATE_6MV_PER_US (1 << RK805_RAMP_RATE_OFFSET) -+#define RK805_RAMP_RATE_12_5MV_PER_US (2 << RK805_RAMP_RATE_OFFSET) -+#define RK805_RAMP_RATE_25MV_PER_US (3 << RK805_RAMP_RATE_OFFSET) -+ - /* RK808 IRQ Definitions */ - #define RK808_IRQ_VOUT_LO 0 - #define RK808_IRQ_VB_LO 1 -@@ -348,6 +674,107 @@ enum rk805_reg { - - #define RK818_NUM_IRQ 16 - -+/*RK818_DCDC_EN_REG*/ -+#define BUCK1_EN_MASK BIT(0) -+#define BUCK2_EN_MASK BIT(1) -+#define BUCK3_EN_MASK BIT(2) -+#define BUCK4_EN_MASK BIT(3) -+#define BOOST_EN_MASK BIT(4) -+#define LDO9_EN_MASK BIT(5) -+#define SWITCH_EN_MASK BIT(6) -+#define OTG_EN_MASK BIT(7) -+ -+#define BUCK1_EN_ENABLE BIT(0) -+#define BUCK2_EN_ENABLE BIT(1) -+#define BUCK3_EN_ENABLE BIT(2) -+#define BUCK4_EN_ENABLE BIT(3) -+#define BOOST_EN_ENABLE BIT(4) -+#define LDO9_EN_ENABLE BIT(5) -+#define SWITCH_EN_ENABLE BIT(6) -+#define OTG_EN_ENABLE BIT(7) ++/* cru clocks */ ++#define PCLK_BIGCORE0_ROOT 20 ++#define PCLK_BIGCORE0_PVTM 21 ++#define PCLK_BIGCORE1_ROOT 22 ++#define PCLK_BIGCORE1_PVTM 23 ++#define PCLK_DSU_S_ROOT 24 ++#define PCLK_DSU_ROOT 25 ++#define PCLK_DSU_NS_ROOT 26 ++#define PCLK_LITCORE_PVTM 27 ++#define PCLK_DBG 28 ++#define PCLK_DSU 29 ++#define PCLK_S_DAPLITE 30 ++#define PCLK_M_DAPLITE 31 ++#define MBIST_MCLK_PDM1 32 ++#define MBIST_CLK_ACDCDIG 33 ++#define HCLK_I2S2_2CH 34 ++#define HCLK_I2S3_2CH 35 ++#define CLK_I2S2_2CH_SRC 36 ++#define CLK_I2S2_2CH_FRAC 37 ++#define CLK_I2S2_2CH 38 ++#define MCLK_I2S2_2CH 39 ++#define I2S2_2CH_MCLKOUT 40 ++#define CLK_DAC_ACDCDIG 41 ++#define CLK_I2S3_2CH_SRC 42 ++#define CLK_I2S3_2CH_FRAC 43 ++#define CLK_I2S3_2CH 44 ++#define MCLK_I2S3_2CH 45 ++#define I2S3_2CH_MCLKOUT 46 ++#define PCLK_ACDCDIG 47 ++#define HCLK_I2S0_8CH 48 ++#define CLK_I2S0_8CH_TX_SRC 49 ++#define CLK_I2S0_8CH_TX_FRAC 50 ++#define MCLK_I2S0_8CH_TX 51 ++#define CLK_I2S0_8CH_TX 52 ++#define CLK_I2S0_8CH_RX_SRC 53 ++#define CLK_I2S0_8CH_RX_FRAC 54 ++#define MCLK_I2S0_8CH_RX 55 ++#define CLK_I2S0_8CH_RX 56 ++#define I2S0_8CH_MCLKOUT 57 ++#define HCLK_PDM1 58 ++#define MCLK_PDM1 59 ++#define HCLK_AUDIO_ROOT 60 ++#define PCLK_AUDIO_ROOT 61 ++#define HCLK_SPDIF0 62 ++#define CLK_SPDIF0_SRC 63 ++#define CLK_SPDIF0_FRAC 64 ++#define MCLK_SPDIF0 65 ++#define CLK_SPDIF0 66 ++#define CLK_SPDIF1 67 ++#define HCLK_SPDIF1 68 ++#define CLK_SPDIF1_SRC 69 ++#define CLK_SPDIF1_FRAC 70 ++#define MCLK_SPDIF1 71 ++#define ACLK_AV1_ROOT 72 ++#define ACLK_AV1 73 ++#define PCLK_AV1_ROOT 74 ++#define PCLK_AV1 75 ++#define PCLK_MAILBOX0 76 ++#define PCLK_MAILBOX1 77 ++#define PCLK_MAILBOX2 78 ++#define PCLK_PMU2 79 ++#define PCLK_PMUCM0_INTMUX 80 ++#define PCLK_DDRCM0_INTMUX 81 ++#define PCLK_TOP 82 ++#define PCLK_PWM1 83 ++#define CLK_PWM1 84 ++#define CLK_PWM1_CAPTURE 85 ++#define PCLK_PWM2 86 ++#define CLK_PWM2 87 ++#define CLK_PWM2_CAPTURE 88 ++#define PCLK_PWM3 89 ++#define CLK_PWM3 90 ++#define CLK_PWM3_CAPTURE 91 ++#define PCLK_BUSTIMER0 92 ++#define PCLK_BUSTIMER1 93 ++#define CLK_BUS_TIMER_ROOT 94 ++#define CLK_BUSTIMER0 95 ++#define CLK_BUSTIMER1 96 ++#define CLK_BUSTIMER2 97 ++#define CLK_BUSTIMER3 98 ++#define CLK_BUSTIMER4 99 ++#define CLK_BUSTIMER5 100 ++#define CLK_BUSTIMER6 101 ++#define CLK_BUSTIMER7 102 ++#define CLK_BUSTIMER8 103 ++#define CLK_BUSTIMER9 104 ++#define CLK_BUSTIMER10 105 ++#define CLK_BUSTIMER11 106 ++#define PCLK_WDT0 107 ++#define TCLK_WDT0 108 ++#define PCLK_CAN0 111 ++#define CLK_CAN0 112 ++#define PCLK_CAN1 113 ++#define CLK_CAN1 114 ++#define PCLK_CAN2 115 ++#define CLK_CAN2 116 ++#define ACLK_DECOM 117 ++#define PCLK_DECOM 118 ++#define DCLK_DECOM 119 ++#define ACLK_DMAC0 120 ++#define ACLK_DMAC1 121 ++#define ACLK_DMAC2 122 ++#define ACLK_BUS_ROOT 123 ++#define ACLK_GIC 124 ++#define PCLK_GPIO1 125 ++#define DBCLK_GPIO1 126 ++#define PCLK_GPIO2 127 ++#define DBCLK_GPIO2 128 ++#define PCLK_GPIO3 129 ++#define DBCLK_GPIO3 130 ++#define PCLK_GPIO4 131 ++#define DBCLK_GPIO4 132 ++#define PCLK_I2C1 133 ++#define PCLK_I2C2 134 ++#define PCLK_I2C3 135 ++#define PCLK_I2C4 136 ++#define PCLK_I2C5 137 ++#define PCLK_I2C6 138 ++#define PCLK_I2C7 139 ++#define PCLK_I2C8 140 ++#define CLK_I2C1 141 ++#define CLK_I2C2 142 ++#define CLK_I2C3 143 ++#define CLK_I2C4 144 ++#define CLK_I2C5 145 ++#define CLK_I2C6 146 ++#define CLK_I2C7 147 ++#define CLK_I2C8 148 ++#define PCLK_OTPC_NS 149 ++#define CLK_OTPC_NS 150 ++#define CLK_OTPC_ARB 151 ++#define CLK_OTPC_AUTO_RD_G 152 ++#define CLK_OTP_PHY_G 153 ++#define PCLK_SARADC 156 ++#define CLK_SARADC 157 ++#define PCLK_SPI0 158 ++#define PCLK_SPI1 159 ++#define PCLK_SPI2 160 ++#define PCLK_SPI3 161 ++#define PCLK_SPI4 162 ++#define CLK_SPI0 163 ++#define CLK_SPI1 164 ++#define CLK_SPI2 165 ++#define CLK_SPI3 166 ++#define CLK_SPI4 167 ++#define ACLK_SPINLOCK 168 ++#define PCLK_TSADC 169 ++#define CLK_TSADC 170 ++#define PCLK_UART1 171 ++#define PCLK_UART2 172 ++#define PCLK_UART3 173 ++#define PCLK_UART4 174 ++#define PCLK_UART5 175 ++#define PCLK_UART6 176 ++#define PCLK_UART7 177 ++#define PCLK_UART8 178 ++#define PCLK_UART9 179 ++#define CLK_UART1_SRC 180 ++#define CLK_UART1_FRAC 181 ++#define CLK_UART1 182 ++#define SCLK_UART1 183 ++#define CLK_UART2_SRC 184 ++#define CLK_UART2_FRAC 185 ++#define CLK_UART2 186 ++#define SCLK_UART2 187 ++#define CLK_UART3_SRC 188 ++#define CLK_UART3_FRAC 189 ++#define CLK_UART3 190 ++#define SCLK_UART3 191 ++#define CLK_UART4_SRC 192 ++#define CLK_UART4_FRAC 193 ++#define CLK_UART4 194 ++#define SCLK_UART4 195 ++#define CLK_UART5_SRC 196 ++#define CLK_UART5_FRAC 197 ++#define CLK_UART5 198 ++#define SCLK_UART5 199 ++#define CLK_UART6_SRC 200 ++#define CLK_UART6_FRAC 201 ++#define CLK_UART6 202 ++#define SCLK_UART6 203 ++#define CLK_UART7_SRC 204 ++#define CLK_UART7_FRAC 205 ++#define CLK_UART7 206 ++#define SCLK_UART7 207 ++#define CLK_UART8_SRC 208 ++#define CLK_UART8_FRAC 209 ++#define CLK_UART8 210 ++#define SCLK_UART8 211 ++#define CLK_UART9_SRC 212 ++#define CLK_UART9_FRAC 213 ++#define CLK_UART9 214 ++#define SCLK_UART9 215 ++#define ACLK_CENTER_ROOT 216 ++#define ACLK_CENTER_LOW_ROOT 217 ++#define HCLK_CENTER_ROOT 218 ++#define PCLK_CENTER_ROOT 219 ++#define ACLK_DMA2DDR 220 ++#define ACLK_DDR_SHAREMEM 221 ++#define ACLK_CENTER_S200_ROOT 222 ++#define ACLK_CENTER_S400_ROOT 223 ++#define FCLK_DDR_CM0_CORE 224 ++#define CLK_DDR_TIMER_ROOT 225 ++#define CLK_DDR_TIMER0 226 ++#define CLK_DDR_TIMER1 227 ++#define TCLK_WDT_DDR 228 ++#define CLK_DDR_CM0_RTC 228 ++#define PCLK_WDT 230 ++#define PCLK_TIMER 231 ++#define PCLK_DMA2DDR 232 ++#define PCLK_SHAREMEM 233 ++#define CLK_50M_SRC 234 ++#define CLK_100M_SRC 235 ++#define CLK_150M_SRC 236 ++#define CLK_200M_SRC 237 ++#define CLK_250M_SRC 238 ++#define CLK_300M_SRC 239 ++#define CLK_350M_SRC 240 ++#define CLK_400M_SRC 241 ++#define CLK_450M_SRC 242 ++#define CLK_500M_SRC 243 ++#define CLK_600M_SRC 244 ++#define CLK_650M_SRC 245 ++#define CLK_700M_SRC 246 ++#define CLK_800M_SRC 247 ++#define CLK_1000M_SRC 248 ++#define CLK_1200M_SRC 249 ++#define ACLK_TOP_M300_ROOT 250 ++#define ACLK_TOP_M500_ROOT 251 ++#define ACLK_TOP_M400_ROOT 252 ++#define ACLK_TOP_S200_ROOT 253 ++#define ACLK_TOP_S400_ROOT 254 ++#define CLK_MIPI_CAMARAOUT_M0 255 ++#define CLK_MIPI_CAMARAOUT_M1 256 ++#define CLK_MIPI_CAMARAOUT_M2 257 ++#define CLK_MIPI_CAMARAOUT_M3 258 ++#define CLK_MIPI_CAMARAOUT_M4 259 ++#define MCLK_GMAC0_OUT 260 ++#define REFCLKO25M_ETH0_OUT 261 ++#define REFCLKO25M_ETH1_OUT 262 ++#define CLK_CIFOUT_OUT 263 ++#define PCLK_MIPI_DCPHY0 264 ++#define PCLK_MIPI_DCPHY1 265 ++#define PCLK_CSIPHY0 268 ++#define PCLK_CSIPHY1 269 ++#define ACLK_TOP_ROOT 270 ++#define PCLK_TOP_ROOT 271 ++#define ACLK_LOW_TOP_ROOT 272 ++#define PCLK_CRU 273 ++#define PCLK_GPU_ROOT 274 ++#define CLK_GPU_SRC 275 ++#define CLK_GPU 276 ++#define CLK_GPU_COREGROUP 277 ++#define CLK_GPU_STACKS 278 ++#define PCLK_GPU_PVTM 279 ++#define CLK_GPU_PVTM 280 ++#define CLK_CORE_GPU_PVTM 281 ++#define PCLK_GPU_GRF 282 ++#define ACLK_ISP1_ROOT 283 ++#define HCLK_ISP1_ROOT 284 ++#define CLK_ISP1_CORE 285 ++#define CLK_ISP1_CORE_MARVIN 286 ++#define CLK_ISP1_CORE_VICAP 287 ++#define ACLK_ISP1 288 ++#define HCLK_ISP1 289 ++#define ACLK_NPU1 290 ++#define HCLK_NPU1 291 ++#define ACLK_NPU2 292 ++#define HCLK_NPU2 293 ++#define HCLK_NPU_CM0_ROOT 294 ++#define FCLK_NPU_CM0_CORE 295 ++#define CLK_NPU_CM0_RTC 296 ++#define PCLK_NPU_PVTM 297 ++#define PCLK_NPU_GRF 298 ++#define CLK_NPU_PVTM 299 ++#define CLK_CORE_NPU_PVTM 300 ++#define ACLK_NPU0 301 ++#define HCLK_NPU0 302 ++#define HCLK_NPU_ROOT 303 ++#define CLK_NPU_DSU0 304 ++#define PCLK_NPU_ROOT 305 ++#define PCLK_NPU_TIMER 306 ++#define CLK_NPUTIMER_ROOT 307 ++#define CLK_NPUTIMER0 308 ++#define CLK_NPUTIMER1 309 ++#define PCLK_NPU_WDT 310 ++#define TCLK_NPU_WDT 311 ++#define HCLK_EMMC 312 ++#define ACLK_EMMC 313 ++#define CCLK_EMMC 314 ++#define BCLK_EMMC 315 ++#define TMCLK_EMMC 316 ++#define SCLK_SFC 317 ++#define HCLK_SFC 318 ++#define HCLK_SFC_XIP 319 ++#define HCLK_NVM_ROOT 320 ++#define ACLK_NVM_ROOT 321 ++#define CLK_GMAC0_PTP_REF 322 ++#define CLK_GMAC1_PTP_REF 323 ++#define CLK_GMAC_125M 324 ++#define CLK_GMAC_50M 325 ++#define ACLK_PHP_GIC_ITS 326 ++#define ACLK_MMU_PCIE 327 ++#define ACLK_MMU_PHP 328 ++#define ACLK_PCIE_4L_DBI 329 ++#define ACLK_PCIE_2L_DBI 330 ++#define ACLK_PCIE_1L0_DBI 331 ++#define ACLK_PCIE_1L1_DBI 332 ++#define ACLK_PCIE_1L2_DBI 333 ++#define ACLK_PCIE_4L_MSTR 334 ++#define ACLK_PCIE_2L_MSTR 335 ++#define ACLK_PCIE_1L0_MSTR 336 ++#define ACLK_PCIE_1L1_MSTR 337 ++#define ACLK_PCIE_1L2_MSTR 338 ++#define ACLK_PCIE_4L_SLV 339 ++#define ACLK_PCIE_2L_SLV 340 ++#define ACLK_PCIE_1L0_SLV 341 ++#define ACLK_PCIE_1L1_SLV 342 ++#define ACLK_PCIE_1L2_SLV 343 ++#define PCLK_PCIE_4L 344 ++#define PCLK_PCIE_2L 345 ++#define PCLK_PCIE_1L0 347 ++#define PCLK_PCIE_1L1 348 ++#define PCLK_PCIE_1L2 349 ++#define CLK_PCIE_AUX0 350 ++#define CLK_PCIE_AUX1 351 ++#define CLK_PCIE_AUX2 352 ++#define CLK_PCIE_AUX3 353 ++#define CLK_PCIE_AUX4 354 ++#define CLK_PIPEPHY0_REF 355 ++#define CLK_PIPEPHY1_REF 356 ++#define CLK_PIPEPHY2_REF 357 ++#define PCLK_PHP_ROOT 358 ++#define PCLK_GMAC0 359 ++#define PCLK_GMAC1 360 ++#define ACLK_PCIE_ROOT 361 ++#define ACLK_PHP_ROOT 362 ++#define ACLK_PCIE_BRIDGE 363 ++#define ACLK_GMAC0 364 ++#define ACLK_GMAC1 365 ++#define CLK_PMALIVE0 366 ++#define CLK_PMALIVE1 367 ++#define CLK_PMALIVE2 368 ++#define ACLK_SATA0 369 ++#define ACLK_SATA1 370 ++#define ACLK_SATA2 371 ++#define CLK_RXOOB0 372 ++#define CLK_RXOOB1 373 ++#define CLK_RXOOB2 374 ++#define ACLK_USB3OTG2 375 ++#define SUSPEND_CLK_USB3OTG2 376 ++#define REF_CLK_USB3OTG2 377 ++#define CLK_UTMI_OTG2 378 ++#define CLK_PIPEPHY0_PIPE_G 379 ++#define CLK_PIPEPHY1_PIPE_G 380 ++#define CLK_PIPEPHY2_PIPE_G 381 ++#define CLK_PIPEPHY0_PIPE_ASIC_G 382 ++#define CLK_PIPEPHY1_PIPE_ASIC_G 383 ++#define CLK_PIPEPHY2_PIPE_ASIC_G 384 ++#define CLK_PIPEPHY2_PIPE_U3_G 385 ++#define CLK_PCIE1L2_PIPE 386 ++#define CLK_PCIE4L_PIPE 387 ++#define CLK_PCIE2L_PIPE 388 ++#define PCLK_PCIE_COMBO_PIPE_PHY0 389 ++#define PCLK_PCIE_COMBO_PIPE_PHY1 390 ++#define PCLK_PCIE_COMBO_PIPE_PHY2 391 ++#define PCLK_PCIE_COMBO_PIPE_PHY 392 ++#define HCLK_RGA3_1 393 ++#define ACLK_RGA3_1 394 ++#define CLK_RGA3_1_CORE 395 ++#define ACLK_RGA3_ROOT 396 ++#define HCLK_RGA3_ROOT 397 ++#define ACLK_RKVDEC_CCU 398 ++#define HCLK_RKVDEC0 399 ++#define ACLK_RKVDEC0 400 ++#define CLK_RKVDEC0_CA 401 ++#define CLK_RKVDEC0_HEVC_CA 402 ++#define CLK_RKVDEC0_CORE 403 ++#define HCLK_RKVDEC1 404 ++#define ACLK_RKVDEC1 405 ++#define CLK_RKVDEC1_CA 406 ++#define CLK_RKVDEC1_HEVC_CA 407 ++#define CLK_RKVDEC1_CORE 408 ++#define HCLK_SDIO 409 ++#define CCLK_SRC_SDIO 410 ++#define ACLK_USB_ROOT 411 ++#define HCLK_USB_ROOT 412 ++#define HCLK_HOST0 413 ++#define HCLK_HOST_ARB0 414 ++#define HCLK_HOST1 415 ++#define HCLK_HOST_ARB1 416 ++#define ACLK_USB3OTG0 417 ++#define SUSPEND_CLK_USB3OTG0 418 ++#define REF_CLK_USB3OTG0 419 ++#define ACLK_USB3OTG1 420 ++#define SUSPEND_CLK_USB3OTG1 421 ++#define REF_CLK_USB3OTG1 422 ++#define UTMI_OHCI_CLK48_HOST0 423 ++#define UTMI_OHCI_CLK48_HOST1 424 ++#define HCLK_IEP2P0 425 ++#define ACLK_IEP2P0 426 ++#define CLK_IEP2P0_CORE 427 ++#define ACLK_JPEG_ENCODER0 428 ++#define HCLK_JPEG_ENCODER0 429 ++#define ACLK_JPEG_ENCODER1 430 ++#define HCLK_JPEG_ENCODER1 431 ++#define ACLK_JPEG_ENCODER2 432 ++#define HCLK_JPEG_ENCODER2 433 ++#define ACLK_JPEG_ENCODER3 434 ++#define HCLK_JPEG_ENCODER3 435 ++#define ACLK_JPEG_DECODER 436 ++#define HCLK_JPEG_DECODER 437 ++#define HCLK_RGA2 438 ++#define ACLK_RGA2 439 ++#define CLK_RGA2_CORE 440 ++#define HCLK_RGA3_0 441 ++#define ACLK_RGA3_0 442 ++#define CLK_RGA3_0_CORE 443 ++#define ACLK_VDPU_ROOT 444 ++#define ACLK_VDPU_LOW_ROOT 445 ++#define HCLK_VDPU_ROOT 446 ++#define ACLK_JPEG_DECODER_ROOT 447 ++#define ACLK_VPU 448 ++#define HCLK_VPU 449 ++#define HCLK_RKVENC0_ROOT 450 ++#define ACLK_RKVENC0_ROOT 451 ++#define HCLK_RKVENC0 452 ++#define ACLK_RKVENC0 453 ++#define CLK_RKVENC0_CORE 454 ++#define HCLK_RKVENC1_ROOT 455 ++#define ACLK_RKVENC1_ROOT 456 ++#define HCLK_RKVENC1 457 ++#define ACLK_RKVENC1 458 ++#define CLK_RKVENC1_CORE 459 ++#define ICLK_CSIHOST01 460 ++#define ICLK_CSIHOST0 461 ++#define ICLK_CSIHOST1 462 ++#define PCLK_CSI_HOST_0 463 ++#define PCLK_CSI_HOST_1 464 ++#define PCLK_CSI_HOST_2 465 ++#define PCLK_CSI_HOST_3 466 ++#define PCLK_CSI_HOST_4 467 ++#define PCLK_CSI_HOST_5 468 ++#define ACLK_FISHEYE0 469 ++#define HCLK_FISHEYE0 470 ++#define CLK_FISHEYE0_CORE 471 ++#define ACLK_FISHEYE1 472 ++#define HCLK_FISHEYE1 473 ++#define CLK_FISHEYE1_CORE 474 ++#define CLK_ISP0_CORE 475 ++#define CLK_ISP0_CORE_MARVIN 476 ++#define CLK_ISP0_CORE_VICAP 477 ++#define ACLK_ISP0 478 ++#define HCLK_ISP0 479 ++#define ACLK_VI_ROOT 480 ++#define HCLK_VI_ROOT 481 ++#define PCLK_VI_ROOT 482 ++#define DCLK_VICAP 483 ++#define ACLK_VICAP 484 ++#define HCLK_VICAP 485 ++#define PCLK_DP0 486 ++#define PCLK_DP1 487 ++#define PCLK_S_DP0 488 ++#define PCLK_S_DP1 489 ++#define CLK_DP0 490 ++#define CLK_DP1 491 ++#define HCLK_HDCP_KEY0 492 ++#define ACLK_HDCP0 493 ++#define HCLK_HDCP0 494 ++#define PCLK_HDCP0 495 ++#define HCLK_I2S4_8CH 496 ++#define ACLK_TRNG0 497 ++#define PCLK_TRNG0 498 ++#define ACLK_VO0_ROOT 499 ++#define HCLK_VO0_ROOT 500 ++#define HCLK_VO0_S_ROOT 501 ++#define PCLK_VO0_ROOT 502 ++#define PCLK_VO0_S_ROOT 503 ++#define PCLK_VO0GRF 504 ++#define CLK_I2S4_8CH_TX_SRC 505 ++#define CLK_I2S4_8CH_TX_FRAC 506 ++#define MCLK_I2S4_8CH_TX 507 ++#define CLK_I2S4_8CH_TX 508 ++#define HCLK_I2S8_8CH 510 ++#define CLK_I2S8_8CH_TX_SRC 511 ++#define CLK_I2S8_8CH_TX_FRAC 512 ++#define MCLK_I2S8_8CH_TX 513 ++#define CLK_I2S8_8CH_TX 514 ++#define HCLK_SPDIF2_DP0 516 ++#define CLK_SPDIF2_DP0_SRC 517 ++#define CLK_SPDIF2_DP0_FRAC 518 ++#define MCLK_SPDIF2_DP0 519 ++#define CLK_SPDIF2_DP0 520 ++#define MCLK_SPDIF2 521 ++#define HCLK_SPDIF5_DP1 522 ++#define CLK_SPDIF5_DP1_SRC 523 ++#define CLK_SPDIF5_DP1_FRAC 524 ++#define MCLK_SPDIF5_DP1 525 ++#define CLK_SPDIF5_DP1 526 ++#define MCLK_SPDIF5 527 ++#define PCLK_EDP0 528 ++#define CLK_EDP0_24M 529 ++#define CLK_EDP0_200M 530 ++#define PCLK_EDP1 531 ++#define CLK_EDP1_24M 532 ++#define CLK_EDP1_200M 533 ++#define HCLK_HDCP_KEY1 534 ++#define ACLK_HDCP1 535 ++#define HCLK_HDCP1 536 ++#define PCLK_HDCP1 537 ++#define ACLK_HDMIRX 538 ++#define PCLK_HDMIRX 539 ++#define CLK_HDMIRX_REF 540 ++#define CLK_HDMIRX_AUD_SRC 541 ++#define CLK_HDMIRX_AUD_FRAC 542 ++#define CLK_HDMIRX_AUD 543 ++#define CLK_HDMIRX_AUD_P_MUX 544 ++#define PCLK_HDMITX0 545 ++#define CLK_HDMITX0_EARC 546 ++#define CLK_HDMITX0_REF 547 ++#define PCLK_HDMITX1 548 ++#define CLK_HDMITX1_EARC 549 ++#define CLK_HDMITX1_REF 550 ++#define CLK_HDMITRX_REFSRC 551 ++#define ACLK_TRNG1 552 ++#define PCLK_TRNG1 553 ++#define ACLK_HDCP1_ROOT 554 ++#define ACLK_HDMIRX_ROOT 555 ++#define HCLK_VO1_ROOT 556 ++#define HCLK_VO1_S_ROOT 557 ++#define PCLK_VO1_ROOT 558 ++#define PCLK_VO1_S_ROOT 559 ++#define PCLK_S_EDP0 560 ++#define PCLK_S_EDP1 561 ++#define PCLK_S_HDMIRX 562 ++#define HCLK_I2S10_8CH 563 ++#define CLK_I2S10_8CH_RX_SRC 564 ++#define CLK_I2S10_8CH_RX_FRAC 565 ++#define CLK_I2S10_8CH_RX 566 ++#define MCLK_I2S10_8CH_RX 567 ++#define HCLK_I2S7_8CH 568 ++#define CLK_I2S7_8CH_RX_SRC 569 ++#define CLK_I2S7_8CH_RX_FRAC 570 ++#define CLK_I2S7_8CH_RX 571 ++#define MCLK_I2S7_8CH_RX 572 ++#define HCLK_I2S9_8CH 574 ++#define CLK_I2S9_8CH_RX_SRC 575 ++#define CLK_I2S9_8CH_RX_FRAC 576 ++#define CLK_I2S9_8CH_RX 577 ++#define MCLK_I2S9_8CH_RX 578 ++#define CLK_I2S5_8CH_TX_SRC 579 ++#define CLK_I2S5_8CH_TX_FRAC 580 ++#define CLK_I2S5_8CH_TX 581 ++#define MCLK_I2S5_8CH_TX 582 ++#define HCLK_I2S5_8CH 584 ++#define CLK_I2S6_8CH_TX_SRC 585 ++#define CLK_I2S6_8CH_TX_FRAC 586 ++#define CLK_I2S6_8CH_TX 587 ++#define MCLK_I2S6_8CH_TX 588 ++#define CLK_I2S6_8CH_RX_SRC 589 ++#define CLK_I2S6_8CH_RX_FRAC 590 ++#define CLK_I2S6_8CH_RX 591 ++#define MCLK_I2S6_8CH_RX 592 ++#define I2S6_8CH_MCLKOUT 593 ++#define HCLK_I2S6_8CH 594 ++#define HCLK_SPDIF3 595 ++#define CLK_SPDIF3_SRC 596 ++#define CLK_SPDIF3_FRAC 597 ++#define CLK_SPDIF3 598 ++#define MCLK_SPDIF3 599 ++#define HCLK_SPDIF4 600 ++#define CLK_SPDIF4_SRC 601 ++#define CLK_SPDIF4_FRAC 602 ++#define CLK_SPDIF4 603 ++#define MCLK_SPDIF4 604 ++#define HCLK_SPDIFRX0 605 ++#define MCLK_SPDIFRX0 606 ++#define HCLK_SPDIFRX1 607 ++#define MCLK_SPDIFRX1 608 ++#define HCLK_SPDIFRX2 609 ++#define MCLK_SPDIFRX2 610 ++#define ACLK_VO1USB_TOP_ROOT 611 ++#define HCLK_VO1USB_TOP_ROOT 612 ++#define CLK_HDMIHDP0 613 ++#define CLK_HDMIHDP1 614 ++#define PCLK_HDPTX0 615 ++#define PCLK_HDPTX1 616 ++#define PCLK_USBDPPHY0 617 ++#define PCLK_USBDPPHY1 618 ++#define ACLK_VOP_ROOT 619 ++#define ACLK_VOP_LOW_ROOT 620 ++#define HCLK_VOP_ROOT 621 ++#define PCLK_VOP_ROOT 622 ++#define HCLK_VOP 623 ++#define ACLK_VOP 624 ++#define DCLK_VOP0_SRC 625 ++#define DCLK_VOP1_SRC 626 ++#define DCLK_VOP2_SRC 627 ++#define DCLK_VOP0 628 ++#define DCLK_VOP1 629 ++#define DCLK_VOP2 630 ++#define DCLK_VOP3 631 ++#define PCLK_DSIHOST0 632 ++#define PCLK_DSIHOST1 633 ++#define CLK_DSIHOST0 634 ++#define CLK_DSIHOST1 635 ++#define CLK_VOP_PMU 636 ++#define ACLK_VOP_DOBY 637 ++#define ACLK_VOP_SUB_SRC 638 ++#define CLK_USBDP_PHY0_IMMORTAL 639 ++#define CLK_USBDP_PHY1_IMMORTAL 640 ++#define CLK_PMU0 641 ++#define PCLK_PMU0 642 ++#define PCLK_PMU0IOC 643 ++#define PCLK_GPIO0 644 ++#define DBCLK_GPIO0 645 ++#define PCLK_I2C0 646 ++#define CLK_I2C0 647 ++#define HCLK_I2S1_8CH 648 ++#define CLK_I2S1_8CH_TX_SRC 649 ++#define CLK_I2S1_8CH_TX_FRAC 650 ++#define CLK_I2S1_8CH_TX 651 ++#define MCLK_I2S1_8CH_TX 652 ++#define CLK_I2S1_8CH_RX_SRC 653 ++#define CLK_I2S1_8CH_RX_FRAC 654 ++#define CLK_I2S1_8CH_RX 655 ++#define MCLK_I2S1_8CH_RX 656 ++#define I2S1_8CH_MCLKOUT 657 ++#define CLK_PMU1_50M_SRC 658 ++#define CLK_PMU1_100M_SRC 659 ++#define CLK_PMU1_200M_SRC 660 ++#define CLK_PMU1_300M_SRC 661 ++#define CLK_PMU1_400M_SRC 662 ++#define HCLK_PMU1_ROOT 663 ++#define PCLK_PMU1_ROOT 664 ++#define PCLK_PMU0_ROOT 665 ++#define HCLK_PMU_CM0_ROOT 666 ++#define PCLK_PMU1 667 ++#define CLK_DDR_FAIL_SAFE 668 ++#define CLK_PMU1 669 ++#define HCLK_PDM0 670 ++#define MCLK_PDM0 671 ++#define HCLK_VAD 672 ++#define FCLK_PMU_CM0_CORE 673 ++#define CLK_PMU_CM0_RTC 674 ++#define PCLK_PMU1_IOC 675 ++#define PCLK_PMU1PWM 676 ++#define CLK_PMU1PWM 677 ++#define CLK_PMU1PWM_CAPTURE 678 ++#define PCLK_PMU1TIMER 679 ++#define CLK_PMU1TIMER_ROOT 680 ++#define CLK_PMU1TIMER0 681 ++#define CLK_PMU1TIMER1 682 ++#define CLK_UART0_SRC 683 ++#define CLK_UART0_FRAC 684 ++#define CLK_UART0 685 ++#define SCLK_UART0 686 ++#define PCLK_UART0 687 ++#define PCLK_PMU1WDT 688 ++#define TCLK_PMU1WDT 689 ++#define CLK_CR_PARA 690 ++#define CLK_USB2PHY_HDPTXRXPHY_REF 693 ++#define CLK_USBDPPHY_MIPIDCPPHY_REF 694 ++#define CLK_REF_PIPE_PHY0_OSC_SRC 695 ++#define CLK_REF_PIPE_PHY1_OSC_SRC 696 ++#define CLK_REF_PIPE_PHY2_OSC_SRC 697 ++#define CLK_REF_PIPE_PHY0_PLL_SRC 698 ++#define CLK_REF_PIPE_PHY1_PLL_SRC 699 ++#define CLK_REF_PIPE_PHY2_PLL_SRC 700 ++#define CLK_REF_PIPE_PHY0 701 ++#define CLK_REF_PIPE_PHY1 702 ++#define CLK_REF_PIPE_PHY2 703 ++#define SCLK_SDIO_DRV 704 ++#define SCLK_SDIO_SAMPLE 705 ++#define SCLK_SDMMC_DRV 706 ++#define SCLK_SDMMC_SAMPLE 707 ++#define CLK_PCIE1L0_PIPE 708 ++#define CLK_PCIE1L1_PIPE 709 ++#define CLK_BIGCORE0_PVTM 710 ++#define CLK_CORE_BIGCORE0_PVTM 711 ++#define CLK_BIGCORE1_PVTM 712 ++#define CLK_CORE_BIGCORE1_PVTM 713 ++#define CLK_LITCORE_PVTM 714 ++#define CLK_CORE_LITCORE_PVTM 715 ++#define CLK_AUX16M_0 716 ++#define CLK_AUX16M_1 717 ++#define CLK_PHY0_REF_ALT_P 718 ++#define CLK_PHY0_REF_ALT_M 719 ++#define CLK_PHY1_REF_ALT_P 720 ++#define CLK_PHY1_REF_ALT_M 721 ++ ++#define CLK_NR_CLKS (CLK_PHY1_REF_ALT_M + 1) ++ ++/********Name=SOFTRST_CON01,Offset=0xA04********/ ++#define SRST_A_TOP_BIU 19 ++#define SRST_P_TOP_BIU 20 ++#define SRST_P_CSIPHY0 22 ++#define SRST_CSIPHY0 23 ++#define SRST_P_CSIPHY1 24 ++#define SRST_CSIPHY1 25 ++#define SRST_A_TOP_M500_BIU 31 ++/********Name=SOFTRST_CON02,Offset=0xA08********/ ++#define SRST_A_TOP_M400_BIU 32 ++#define SRST_A_TOP_S200_BIU 33 ++#define SRST_A_TOP_S400_BIU 34 ++#define SRST_A_TOP_M300_BIU 35 ++#define SRST_USBDP_COMBO_PHY0_INIT 40 ++#define SRST_USBDP_COMBO_PHY0_CMN 41 ++#define SRST_USBDP_COMBO_PHY0_LANE 42 ++#define SRST_USBDP_COMBO_PHY0_PCS 43 ++#define SRST_USBDP_COMBO_PHY1_INIT 47 ++/********Name=SOFTRST_CON03,Offset=0xA0C********/ ++#define SRST_USBDP_COMBO_PHY1_CMN 48 ++#define SRST_USBDP_COMBO_PHY1_LANE 49 ++#define SRST_USBDP_COMBO_PHY1_PCS 50 ++#define SRST_DCPHY0 59 ++#define SRST_P_MIPI_DCPHY0 62 ++#define SRST_P_MIPI_DCPHY0_GRF 63 ++/********Name=SOFTRST_CON04,Offset=0xA10********/ ++#define SRST_DCPHY1 64 ++#define SRST_P_MIPI_DCPHY1 67 ++#define SRST_P_MIPI_DCPHY1_GRF 68 ++#define SRST_P_APB2ASB_SLV_CDPHY 69 ++#define SRST_P_APB2ASB_SLV_CSIPHY 70 ++#define SRST_P_APB2ASB_SLV_VCCIO3_5 71 ++#define SRST_P_APB2ASB_SLV_VCCIO6 72 ++#define SRST_P_APB2ASB_SLV_EMMCIO 73 ++#define SRST_P_APB2ASB_SLV_IOC_TOP 74 ++#define SRST_P_APB2ASB_SLV_IOC_RIGHT 75 ++/********Name=SOFTRST_CON05,Offset=0xA14********/ ++#define SRST_P_CRU 80 ++#define SRST_A_CHANNEL_SECURE2VO1USB 87 ++#define SRST_A_CHANNEL_SECURE2CENTER 88 ++#define SRST_H_CHANNEL_SECURE2VO1USB 94 ++#define SRST_H_CHANNEL_SECURE2CENTER 95 ++/********Name=SOFTRST_CON06,Offset=0xA18********/ ++#define SRST_P_CHANNEL_SECURE2VO1USB 96 ++#define SRST_P_CHANNEL_SECURE2CENTER 97 ++/********Name=SOFTRST_CON07,Offset=0xA1C********/ ++#define SRST_H_AUDIO_BIU 114 ++#define SRST_P_AUDIO_BIU 115 ++#define SRST_H_I2S0_8CH 116 ++#define SRST_M_I2S0_8CH_TX 119 ++#define SRST_M_I2S0_8CH_RX 122 ++#define SRST_P_ACDCDIG 123 ++#define SRST_H_I2S2_2CH 124 ++#define SRST_H_I2S3_2CH 125 ++/********Name=SOFTRST_CON08,Offset=0xA20********/ ++#define SRST_M_I2S2_2CH 128 ++#define SRST_M_I2S3_2CH 131 ++#define SRST_DAC_ACDCDIG 132 ++#define SRST_H_SPDIF0 142 ++/********Name=SOFTRST_CON09,Offset=0xA24********/ ++#define SRST_M_SPDIF0 145 ++#define SRST_H_SPDIF1 146 ++#define SRST_M_SPDIF1 149 ++#define SRST_H_PDM1 150 ++#define SRST_PDM1 151 ++/********Name=SOFTRST_CON10,Offset=0xA28********/ ++#define SRST_A_BUS_BIU 161 ++#define SRST_P_BUS_BIU 162 ++#define SRST_A_GIC 163 ++#define SRST_A_GIC_DBG 164 ++#define SRST_A_DMAC0 165 ++#define SRST_A_DMAC1 166 ++#define SRST_A_DMAC2 167 ++#define SRST_P_I2C1 168 ++#define SRST_P_I2C2 169 ++#define SRST_P_I2C3 170 ++#define SRST_P_I2C4 171 ++#define SRST_P_I2C5 172 ++#define SRST_P_I2C6 173 ++#define SRST_P_I2C7 174 ++#define SRST_P_I2C8 175 ++/********Name=SOFTRST_CON11,Offset=0xA2C********/ ++#define SRST_I2C1 176 ++#define SRST_I2C2 177 ++#define SRST_I2C3 178 ++#define SRST_I2C4 179 ++#define SRST_I2C5 180 ++#define SRST_I2C6 181 ++#define SRST_I2C7 182 ++#define SRST_I2C8 183 ++#define SRST_P_CAN0 184 ++#define SRST_CAN0 185 ++#define SRST_P_CAN1 186 ++#define SRST_CAN1 187 ++#define SRST_P_CAN2 188 ++#define SRST_CAN2 189 ++#define SRST_P_SARADC 190 ++/********Name=SOFTRST_CON12,Offset=0xA30********/ ++#define SRST_P_TSADC 192 ++#define SRST_TSADC 193 ++#define SRST_P_UART1 194 ++#define SRST_P_UART2 195 ++#define SRST_P_UART3 196 ++#define SRST_P_UART4 197 ++#define SRST_P_UART5 198 ++#define SRST_P_UART6 199 ++#define SRST_P_UART7 200 ++#define SRST_P_UART8 201 ++#define SRST_P_UART9 202 ++#define SRST_S_UART1 205 ++/********Name=SOFTRST_CON13,Offset=0xA34********/ ++#define SRST_S_UART2 208 ++#define SRST_S_UART3 211 ++#define SRST_S_UART4 214 ++#define SRST_S_UART5 217 ++#define SRST_S_UART6 220 ++#define SRST_S_UART7 223 ++/********Name=SOFTRST_CON14,Offset=0xA38********/ ++#define SRST_S_UART8 226 ++#define SRST_S_UART9 229 ++#define SRST_P_SPI0 230 ++#define SRST_P_SPI1 231 ++#define SRST_P_SPI2 232 ++#define SRST_P_SPI3 233 ++#define SRST_P_SPI4 234 ++#define SRST_SPI0 235 ++#define SRST_SPI1 236 ++#define SRST_SPI2 237 ++#define SRST_SPI3 238 ++#define SRST_SPI4 239 ++/********Name=SOFTRST_CON15,Offset=0xA3C********/ ++#define SRST_P_WDT0 240 ++#define SRST_T_WDT0 241 ++#define SRST_P_SYS_GRF 242 ++#define SRST_P_PWM1 243 ++#define SRST_PWM1 244 ++#define SRST_P_PWM2 246 ++#define SRST_PWM2 247 ++#define SRST_P_PWM3 249 ++#define SRST_PWM3 250 ++#define SRST_P_BUSTIMER0 252 ++#define SRST_P_BUSTIMER1 253 ++#define SRST_BUSTIMER0 255 ++/********Name=SOFTRST_CON16,Offset=0xA40********/ ++#define SRST_BUSTIMER1 256 ++#define SRST_BUSTIMER2 257 ++#define SRST_BUSTIMER3 258 ++#define SRST_BUSTIMER4 259 ++#define SRST_BUSTIMER5 260 ++#define SRST_BUSTIMER6 261 ++#define SRST_BUSTIMER7 262 ++#define SRST_BUSTIMER8 263 ++#define SRST_BUSTIMER9 264 ++#define SRST_BUSTIMER10 265 ++#define SRST_BUSTIMER11 266 ++#define SRST_P_MAILBOX0 267 ++#define SRST_P_MAILBOX1 268 ++#define SRST_P_MAILBOX2 269 ++#define SRST_P_GPIO1 270 ++#define SRST_GPIO1 271 ++/********Name=SOFTRST_CON17,Offset=0xA44********/ ++#define SRST_P_GPIO2 272 ++#define SRST_GPIO2 273 ++#define SRST_P_GPIO3 274 ++#define SRST_GPIO3 275 ++#define SRST_P_GPIO4 276 ++#define SRST_GPIO4 277 ++#define SRST_A_DECOM 278 ++#define SRST_P_DECOM 279 ++#define SRST_D_DECOM 280 ++#define SRST_P_TOP 281 ++#define SRST_A_GICADB_GIC2CORE_BUS 283 ++#define SRST_P_DFT2APB 284 ++#define SRST_P_APB2ASB_MST_TOP 285 ++#define SRST_P_APB2ASB_MST_CDPHY 286 ++#define SRST_P_APB2ASB_MST_BOT_RIGHT 287 ++/********Name=SOFTRST_CON18,Offset=0xA48********/ ++#define SRST_P_APB2ASB_MST_IOC_TOP 288 ++#define SRST_P_APB2ASB_MST_IOC_RIGHT 289 ++#define SRST_P_APB2ASB_MST_CSIPHY 290 ++#define SRST_P_APB2ASB_MST_VCCIO3_5 291 ++#define SRST_P_APB2ASB_MST_VCCIO6 292 ++#define SRST_P_APB2ASB_MST_EMMCIO 293 ++#define SRST_A_SPINLOCK 294 ++#define SRST_P_OTPC_NS 297 ++#define SRST_OTPC_NS 298 ++#define SRST_OTPC_ARB 299 ++/********Name=SOFTRST_CON19,Offset=0xA4C********/ ++#define SRST_P_BUSIOC 304 ++#define SRST_P_PMUCM0_INTMUX 308 ++#define SRST_P_DDRCM0_INTMUX 309 ++/********Name=SOFTRST_CON20,Offset=0xA50********/ ++#define SRST_P_DDR_DFICTL_CH0 320 ++#define SRST_P_DDR_MON_CH0 321 ++#define SRST_P_DDR_STANDBY_CH0 322 ++#define SRST_P_DDR_UPCTL_CH0 323 ++#define SRST_TM_DDR_MON_CH0 324 ++#define SRST_P_DDR_GRF_CH01 325 ++#define SRST_DFI_CH0 326 ++#define SRST_SBR_CH0 327 ++#define SRST_DDR_UPCTL_CH0 328 ++#define SRST_DDR_DFICTL_CH0 329 ++#define SRST_DDR_MON_CH0 330 ++#define SRST_DDR_STANDBY_CH0 331 ++#define SRST_A_DDR_UPCTL_CH0 332 ++#define SRST_P_DDR_DFICTL_CH1 333 ++#define SRST_P_DDR_MON_CH1 334 ++#define SRST_P_DDR_STANDBY_CH1 335 ++/********Name=SOFTRST_CON21,Offset=0xA54********/ ++#define SRST_P_DDR_UPCTL_CH1 336 ++#define SRST_TM_DDR_MON_CH1 337 ++#define SRST_DFI_CH1 338 ++#define SRST_SBR_CH1 339 ++#define SRST_DDR_UPCTL_CH1 340 ++#define SRST_DDR_DFICTL_CH1 341 ++#define SRST_DDR_MON_CH1 342 ++#define SRST_DDR_STANDBY_CH1 343 ++#define SRST_A_DDR_UPCTL_CH1 344 ++#define SRST_A_DDR01_MSCH0 349 ++#define SRST_A_DDR01_RS_MSCH0 350 ++#define SRST_A_DDR01_FRS_MSCH0 351 ++/********Name=SOFTRST_CON22,Offset=0xA58********/ ++#define SRST_A_DDR01_SCRAMBLE0 352 ++#define SRST_A_DDR01_FRS_SCRAMBLE0 353 ++#define SRST_A_DDR01_MSCH1 354 ++#define SRST_A_DDR01_RS_MSCH1 355 ++#define SRST_A_DDR01_FRS_MSCH1 356 ++#define SRST_A_DDR01_SCRAMBLE1 357 ++#define SRST_A_DDR01_FRS_SCRAMBLE1 358 ++#define SRST_P_DDR01_MSCH0 359 ++#define SRST_P_DDR01_MSCH1 360 ++/********Name=SOFTRST_CON23,Offset=0xA5C********/ ++#define SRST_P_DDR_DFICTL_CH2 368 ++#define SRST_P_DDR_MON_CH2 369 ++#define SRST_P_DDR_STANDBY_CH2 370 ++#define SRST_P_DDR_UPCTL_CH2 371 ++#define SRST_TM_DDR_MON_CH2 372 ++#define SRST_P_DDR_GRF_CH23 373 ++#define SRST_DFI_CH2 374 ++#define SRST_SBR_CH2 375 ++#define SRST_DDR_UPCTL_CH2 376 ++#define SRST_DDR_DFICTL_CH2 377 ++#define SRST_DDR_MON_CH2 378 ++#define SRST_DDR_STANDBY_CH2 379 ++#define SRST_A_DDR_UPCTL_CH2 380 ++#define SRST_P_DDR_DFICTL_CH3 381 ++#define SRST_P_DDR_MON_CH3 382 ++#define SRST_P_DDR_STANDBY_CH3 383 ++/********Name=SOFTRST_CON24,Offset=0xA60********/ ++#define SRST_P_DDR_UPCTL_CH3 384 ++#define SRST_TM_DDR_MON_CH3 385 ++#define SRST_DFI_CH3 386 ++#define SRST_SBR_CH3 387 ++#define SRST_DDR_UPCTL_CH3 388 ++#define SRST_DDR_DFICTL_CH3 389 ++#define SRST_DDR_MON_CH3 390 ++#define SRST_DDR_STANDBY_CH3 391 ++#define SRST_A_DDR_UPCTL_CH3 392 ++#define SRST_A_DDR23_MSCH2 397 ++#define SRST_A_DDR23_RS_MSCH2 398 ++#define SRST_A_DDR23_FRS_MSCH2 399 ++/********Name=SOFTRST_CON25,Offset=0xA64********/ ++#define SRST_A_DDR23_SCRAMBLE2 400 ++#define SRST_A_DDR23_FRS_SCRAMBLE2 401 ++#define SRST_A_DDR23_MSCH3 402 ++#define SRST_A_DDR23_RS_MSCH3 403 ++#define SRST_A_DDR23_FRS_MSCH3 404 ++#define SRST_A_DDR23_SCRAMBLE3 405 ++#define SRST_A_DDR23_FRS_SCRAMBLE3 406 ++#define SRST_P_DDR23_MSCH2 407 ++#define SRST_P_DDR23_MSCH3 408 ++/********Name=SOFTRST_CON26,Offset=0xA68********/ ++#define SRST_ISP1 419 ++#define SRST_ISP1_VICAP 420 ++#define SRST_A_ISP1_BIU 422 ++#define SRST_H_ISP1_BIU 424 ++/********Name=SOFTRST_CON27,Offset=0xA6C********/ ++#define SRST_A_RKNN1 432 ++#define SRST_A_RKNN1_BIU 433 ++#define SRST_H_RKNN1 434 ++#define SRST_H_RKNN1_BIU 435 ++/********Name=SOFTRST_CON28,Offset=0xA70********/ ++#define SRST_A_RKNN2 448 ++#define SRST_A_RKNN2_BIU 449 ++#define SRST_H_RKNN2 450 ++#define SRST_H_RKNN2_BIU 451 ++/********Name=SOFTRST_CON29,Offset=0xA74********/ ++#define SRST_A_RKNN_DSU0 467 ++#define SRST_P_NPUTOP_BIU 469 ++#define SRST_P_NPU_TIMER 470 ++#define SRST_NPUTIMER0 472 ++#define SRST_NPUTIMER1 473 ++#define SRST_P_NPU_WDT 474 ++#define SRST_T_NPU_WDT 475 ++#define SRST_P_NPU_PVTM 476 ++#define SRST_P_NPU_GRF 477 ++#define SRST_NPU_PVTM 478 ++/********Name=SOFTRST_CON30,Offset=0xA78********/ ++#define SRST_NPU_PVTPLL 480 ++#define SRST_H_NPU_CM0_BIU 482 ++#define SRST_F_NPU_CM0_CORE 483 ++#define SRST_T_NPU_CM0_JTAG 484 ++#define SRST_A_RKNN0 486 ++#define SRST_A_RKNN0_BIU 487 ++#define SRST_H_RKNN0 488 ++#define SRST_H_RKNN0_BIU 489 ++/********Name=SOFTRST_CON31,Offset=0xA7C********/ ++#define SRST_H_NVM_BIU 498 ++#define SRST_A_NVM_BIU 499 ++#define SRST_H_EMMC 500 ++#define SRST_A_EMMC 501 ++#define SRST_C_EMMC 502 ++#define SRST_B_EMMC 503 ++#define SRST_T_EMMC 504 ++#define SRST_S_SFC 505 ++#define SRST_H_SFC 506 ++#define SRST_H_SFC_XIP 507 ++/********Name=SOFTRST_CON32,Offset=0xA80********/ ++#define SRST_P_GRF 513 ++#define SRST_P_DEC_BIU 514 ++#define SRST_P_PHP_BIU 517 ++#define SRST_A_PCIE_GRIDGE 520 ++#define SRST_A_PHP_BIU 521 ++#define SRST_A_GMAC0 522 ++#define SRST_A_GMAC1 523 ++#define SRST_A_PCIE_BIU 524 ++#define SRST_PCIE0_POWER_UP 525 ++#define SRST_PCIE1_POWER_UP 526 ++#define SRST_PCIE2_POWER_UP 527 ++/********Name=SOFTRST_CON33,Offset=0xA84********/ ++#define SRST_PCIE3_POWER_UP 528 ++#define SRST_PCIE4_POWER_UP 529 ++#define SRST_P_PCIE0 540 ++#define SRST_P_PCIE1 541 ++#define SRST_P_PCIE2 542 ++#define SRST_P_PCIE3 543 ++/********Name=SOFTRST_CON34,Offset=0xA88********/ ++#define SRST_P_PCIE4 544 ++#define SRST_A_PHP_GIC_ITS 550 ++#define SRST_A_MMU_PCIE 551 ++#define SRST_A_MMU_PHP 552 ++#define SRST_A_MMU_BIU 553 ++/********Name=SOFTRST_CON35,Offset=0xA8C********/ ++#define SRST_A_USB3OTG2 567 ++/********Name=SOFTRST_CON37,Offset=0xA94********/ ++#define SRST_PMALIVE0 596 ++#define SRST_PMALIVE1 597 ++#define SRST_PMALIVE2 598 ++#define SRST_A_SATA0 599 ++#define SRST_A_SATA1 600 ++#define SRST_A_SATA2 601 ++#define SRST_RXOOB0 602 ++#define SRST_RXOOB1 603 ++#define SRST_RXOOB2 604 ++#define SRST_ASIC0 605 ++#define SRST_ASIC1 606 ++#define SRST_ASIC2 607 ++/********Name=SOFTRST_CON40,Offset=0xAA0********/ ++#define SRST_A_RKVDEC_CCU 642 ++#define SRST_H_RKVDEC0 643 ++#define SRST_A_RKVDEC0 644 ++#define SRST_H_RKVDEC0_BIU 645 ++#define SRST_A_RKVDEC0_BIU 646 ++#define SRST_RKVDEC0_CA 647 ++#define SRST_RKVDEC0_HEVC_CA 648 ++#define SRST_RKVDEC0_CORE 649 ++/********Name=SOFTRST_CON41,Offset=0xAA4********/ ++#define SRST_H_RKVDEC1 658 ++#define SRST_A_RKVDEC1 659 ++#define SRST_H_RKVDEC1_BIU 660 ++#define SRST_A_RKVDEC1_BIU 661 ++#define SRST_RKVDEC1_CA 662 ++#define SRST_RKVDEC1_HEVC_CA 663 ++#define SRST_RKVDEC1_CORE 664 ++/********Name=SOFTRST_CON42,Offset=0xAA8********/ ++#define SRST_A_USB_BIU 674 ++#define SRST_H_USB_BIU 675 ++#define SRST_A_USB3OTG0 676 ++#define SRST_A_USB3OTG1 679 ++#define SRST_H_HOST0 682 ++#define SRST_H_HOST_ARB0 683 ++#define SRST_H_HOST1 684 ++#define SRST_H_HOST_ARB1 685 ++#define SRST_A_USB_GRF 686 ++#define SRST_C_USB2P0_HOST0 687 ++/********Name=SOFTRST_CON43,Offset=0xAAC********/ ++#define SRST_C_USB2P0_HOST1 688 ++#define SRST_HOST_UTMI0 689 ++#define SRST_HOST_UTMI1 690 ++/********Name=SOFTRST_CON44,Offset=0xAB0********/ ++#define SRST_A_VDPU_BIU 708 ++#define SRST_A_VDPU_LOW_BIU 709 ++#define SRST_H_VDPU_BIU 710 ++#define SRST_A_JPEG_DECODER_BIU 711 ++#define SRST_A_VPU 712 ++#define SRST_H_VPU 713 ++#define SRST_A_JPEG_ENCODER0 714 ++#define SRST_H_JPEG_ENCODER0 715 ++#define SRST_A_JPEG_ENCODER1 716 ++#define SRST_H_JPEG_ENCODER1 717 ++#define SRST_A_JPEG_ENCODER2 718 ++#define SRST_H_JPEG_ENCODER2 719 ++/********Name=SOFTRST_CON45,Offset=0xAB4********/ ++#define SRST_A_JPEG_ENCODER3 720 ++#define SRST_H_JPEG_ENCODER3 721 ++#define SRST_A_JPEG_DECODER 722 ++#define SRST_H_JPEG_DECODER 723 ++#define SRST_H_IEP2P0 724 ++#define SRST_A_IEP2P0 725 ++#define SRST_IEP2P0_CORE 726 ++#define SRST_H_RGA2 727 ++#define SRST_A_RGA2 728 ++#define SRST_RGA2_CORE 729 ++#define SRST_H_RGA3_0 730 ++#define SRST_A_RGA3_0 731 ++#define SRST_RGA3_0_CORE 732 ++/********Name=SOFTRST_CON47,Offset=0xABC********/ ++#define SRST_H_RKVENC0_BIU 754 ++#define SRST_A_RKVENC0_BIU 755 ++#define SRST_H_RKVENC0 756 ++#define SRST_A_RKVENC0 757 ++#define SRST_RKVENC0_CORE 758 ++/********Name=SOFTRST_CON48,Offset=0xAC0********/ ++#define SRST_H_RKVENC1_BIU 770 ++#define SRST_A_RKVENC1_BIU 771 ++#define SRST_H_RKVENC1 772 ++#define SRST_A_RKVENC1 773 ++#define SRST_RKVENC1_CORE 774 ++/********Name=SOFTRST_CON49,Offset=0xAC4********/ ++#define SRST_A_VI_BIU 787 ++#define SRST_H_VI_BIU 788 ++#define SRST_P_VI_BIU 789 ++#define SRST_D_VICAP 790 ++#define SRST_A_VICAP 791 ++#define SRST_H_VICAP 792 ++#define SRST_ISP0 794 ++#define SRST_ISP0_VICAP 795 ++/********Name=SOFTRST_CON50,Offset=0xAC8********/ ++#define SRST_FISHEYE0 800 ++#define SRST_FISHEYE1 803 ++#define SRST_P_CSI_HOST_0 804 ++#define SRST_P_CSI_HOST_1 805 ++#define SRST_P_CSI_HOST_2 806 ++#define SRST_P_CSI_HOST_3 807 ++#define SRST_P_CSI_HOST_4 808 ++#define SRST_P_CSI_HOST_5 809 ++/********Name=SOFTRST_CON51,Offset=0xACC********/ ++#define SRST_CSIHOST0_VICAP 820 ++#define SRST_CSIHOST1_VICAP 821 ++#define SRST_CSIHOST2_VICAP 822 ++#define SRST_CSIHOST3_VICAP 823 ++#define SRST_CSIHOST4_VICAP 824 ++#define SRST_CSIHOST5_VICAP 825 ++#define SRST_CIFIN 829 ++/********Name=SOFTRST_CON52,Offset=0xAD0********/ ++#define SRST_A_VOP_BIU 836 ++#define SRST_A_VOP_LOW_BIU 837 ++#define SRST_H_VOP_BIU 838 ++#define SRST_P_VOP_BIU 839 ++#define SRST_H_VOP 840 ++#define SRST_A_VOP 841 ++#define SRST_D_VOP0 845 ++#define SRST_D_VOP2HDMI_BRIDGE0 846 ++#define SRST_D_VOP2HDMI_BRIDGE1 847 ++/********Name=SOFTRST_CON53,Offset=0xAD4********/ ++#define SRST_D_VOP1 848 ++#define SRST_D_VOP2 849 ++#define SRST_D_VOP3 850 ++#define SRST_P_VOPGRF 851 ++#define SRST_P_DSIHOST0 852 ++#define SRST_P_DSIHOST1 853 ++#define SRST_DSIHOST0 854 ++#define SRST_DSIHOST1 855 ++#define SRST_VOP_PMU 856 ++#define SRST_P_VOP_CHANNEL_BIU 857 ++/********Name=SOFTRST_CON55,Offset=0xADC********/ ++#define SRST_H_VO0_BIU 885 ++#define SRST_H_VO0_S_BIU 886 ++#define SRST_P_VO0_BIU 887 ++#define SRST_P_VO0_S_BIU 888 ++#define SRST_A_HDCP0_BIU 889 ++#define SRST_P_VO0GRF 890 ++#define SRST_H_HDCP_KEY0 891 ++#define SRST_A_HDCP0 892 ++#define SRST_H_HDCP0 893 ++#define SRST_HDCP0 895 ++/********Name=SOFTRST_CON56,Offset=0xAE0********/ ++#define SRST_P_TRNG0 897 ++#define SRST_DP0 904 ++#define SRST_DP1 905 ++#define SRST_H_I2S4_8CH 906 ++#define SRST_M_I2S4_8CH_TX 909 ++#define SRST_H_I2S8_8CH 910 ++/********Name=SOFTRST_CON57,Offset=0xAE4********/ ++#define SRST_M_I2S8_8CH_TX 913 ++#define SRST_H_SPDIF2_DP0 914 ++#define SRST_M_SPDIF2_DP0 918 ++#define SRST_H_SPDIF5_DP1 919 ++#define SRST_M_SPDIF5_DP1 923 ++/********Name=SOFTRST_CON59,Offset=0xAEC********/ ++#define SRST_A_HDCP1_BIU 950 ++#define SRST_A_HDMIRX_BIU 951 ++#define SRST_A_VO1_BIU 952 ++#define SRST_H_VOP1_BIU 953 ++#define SRST_H_VOP1_S_BIU 954 ++#define SRST_P_VOP1_BIU 955 ++#define SRST_P_VO1GRF 956 ++#define SRST_P_VO1_S_BIU 957 ++/********Name=SOFTRST_CON60,Offset=0xAF0********/ ++#define SRST_H_I2S7_8CH 960 ++#define SRST_M_I2S7_8CH_RX 963 ++#define SRST_H_HDCP_KEY1 964 ++#define SRST_A_HDCP1 965 ++#define SRST_H_HDCP1 966 ++#define SRST_HDCP1 968 ++#define SRST_P_TRNG1 970 ++#define SRST_P_HDMITX0 971 ++/********Name=SOFTRST_CON61,Offset=0xAF4********/ ++#define SRST_HDMITX0_REF 976 ++#define SRST_P_HDMITX1 978 ++#define SRST_HDMITX1_REF 983 ++#define SRST_A_HDMIRX 985 ++#define SRST_P_HDMIRX 986 ++#define SRST_HDMIRX_REF 987 ++/********Name=SOFTRST_CON62,Offset=0xAF8********/ ++#define SRST_P_EDP0 992 ++#define SRST_EDP0_24M 993 ++#define SRST_P_EDP1 995 ++#define SRST_EDP1_24M 996 ++#define SRST_M_I2S5_8CH_TX 1000 ++#define SRST_H_I2S5_8CH 1004 ++#define SRST_M_I2S6_8CH_TX 1007 ++/********Name=SOFTRST_CON63,Offset=0xAFC********/ ++#define SRST_M_I2S6_8CH_RX 1010 ++#define SRST_H_I2S6_8CH 1011 ++#define SRST_H_SPDIF3 1012 ++#define SRST_M_SPDIF3 1015 ++#define SRST_H_SPDIF4 1016 ++#define SRST_M_SPDIF4 1019 ++#define SRST_H_SPDIFRX0 1020 ++#define SRST_M_SPDIFRX0 1021 ++#define SRST_H_SPDIFRX1 1022 ++#define SRST_M_SPDIFRX1 1023 ++/********Name=SOFTRST_CON64,Offset=0xB00********/ ++#define SRST_H_SPDIFRX2 1024 ++#define SRST_M_SPDIFRX2 1025 ++#define SRST_LINKSYM_HDMITXPHY0 1036 ++#define SRST_LINKSYM_HDMITXPHY1 1037 ++#define SRST_VO1_BRIDGE0 1038 ++#define SRST_VO1_BRIDGE1 1039 ++/********Name=SOFTRST_CON65,Offset=0xB04********/ ++#define SRST_H_I2S9_8CH 1040 ++#define SRST_M_I2S9_8CH_RX 1043 ++#define SRST_H_I2S10_8CH 1044 ++#define SRST_M_I2S10_8CH_RX 1047 ++#define SRST_P_S_HDMIRX 1048 ++/********Name=SOFTRST_CON66,Offset=0xB08********/ ++#define SRST_GPU 1060 ++#define SRST_SYS_GPU 1061 ++#define SRST_A_S_GPU_BIU 1064 ++#define SRST_A_M0_GPU_BIU 1065 ++#define SRST_A_M1_GPU_BIU 1066 ++#define SRST_A_M2_GPU_BIU 1067 ++#define SRST_A_M3_GPU_BIU 1068 ++#define SRST_P_GPU_BIU 1070 ++#define SRST_P_GPU_PVTM 1071 ++/********Name=SOFTRST_CON67,Offset=0xB0C********/ ++#define SRST_GPU_PVTM 1072 ++#define SRST_P_GPU_GRF 1074 ++#define SRST_GPU_PVTPLL 1075 ++#define SRST_GPU_JTAG 1076 ++/********Name=SOFTRST_CON68,Offset=0xB10********/ ++#define SRST_A_AV1_BIU 1089 ++#define SRST_A_AV1 1090 ++#define SRST_P_AV1_BIU 1092 ++#define SRST_P_AV1 1093 ++/********Name=SOFTRST_CON69,Offset=0xB14********/ ++#define SRST_A_DDR_BIU 1108 ++#define SRST_A_DMA2DDR 1109 ++#define SRST_A_DDR_SHAREMEM 1110 ++#define SRST_A_DDR_SHAREMEM_BIU 1111 ++#define SRST_A_CENTER_S200_BIU 1114 ++#define SRST_A_CENTER_S400_BIU 1115 ++#define SRST_H_AHB2APB 1116 ++#define SRST_H_CENTER_BIU 1117 ++#define SRST_F_DDR_CM0_CORE 1118 ++/********Name=SOFTRST_CON70,Offset=0xB18********/ ++#define SRST_DDR_TIMER0 1120 ++#define SRST_DDR_TIMER1 1121 ++#define SRST_T_WDT_DDR 1122 ++#define SRST_T_DDR_CM0_JTAG 1123 ++#define SRST_P_CENTER_GRF 1125 ++#define SRST_P_AHB2APB 1126 ++#define SRST_P_WDT 1127 ++#define SRST_P_TIMER 1128 ++#define SRST_P_DMA2DDR 1129 ++#define SRST_P_SHAREMEM 1130 ++#define SRST_P_CENTER_BIU 1131 ++#define SRST_P_CENTER_CHANNEL_BIU 1132 ++/********Name=SOFTRST_CON72,Offset=0xB20********/ ++#define SRST_P_USBDPGRF0 1153 ++#define SRST_P_USBDPPHY0 1154 ++#define SRST_P_USBDPGRF1 1155 ++#define SRST_P_USBDPPHY1 1156 ++#define SRST_P_HDPTX0 1157 ++#define SRST_P_HDPTX1 1158 ++#define SRST_P_APB2ASB_SLV_BOT_RIGHT 1159 ++#define SRST_P_USB2PHY_U3_0_GRF0 1160 ++#define SRST_P_USB2PHY_U3_1_GRF0 1161 ++#define SRST_P_USB2PHY_U2_0_GRF0 1162 ++#define SRST_P_USB2PHY_U2_1_GRF0 1163 ++#define SRST_HDPTX0_ROPLL 1164 ++#define SRST_HDPTX0_LCPLL 1165 ++#define SRST_HDPTX0 1166 ++#define SRST_HDPTX1_ROPLL 1167 ++/********Name=SOFTRST_CON73,Offset=0xB24********/ ++#define SRST_HDPTX1_LCPLL 1168 ++#define SRST_HDPTX1 1169 ++#define SRST_HDPTX0_HDMIRXPHY_SET 1170 ++#define SRST_USBDP_COMBO_PHY0 1171 ++#define SRST_USBDP_COMBO_PHY0_LCPLL 1172 ++#define SRST_USBDP_COMBO_PHY0_ROPLL 1173 ++#define SRST_USBDP_COMBO_PHY0_PCS_HS 1174 ++#define SRST_USBDP_COMBO_PHY1 1175 ++#define SRST_USBDP_COMBO_PHY1_LCPLL 1176 ++#define SRST_USBDP_COMBO_PHY1_ROPLL 1177 ++#define SRST_USBDP_COMBO_PHY1_PCS_HS 1178 ++#define SRST_HDMIHDP0 1180 ++#define SRST_HDMIHDP1 1181 ++/********Name=SOFTRST_CON74,Offset=0xB28********/ ++#define SRST_A_VO1USB_TOP_BIU 1185 ++#define SRST_H_VO1USB_TOP_BIU 1187 ++/********Name=SOFTRST_CON75,Offset=0xB2C********/ ++#define SRST_H_SDIO_BIU 1201 ++#define SRST_H_SDIO 1202 ++#define SRST_SDIO 1203 ++/********Name=SOFTRST_CON76,Offset=0xB30********/ ++#define SRST_H_RGA3_BIU 1218 ++#define SRST_A_RGA3_BIU 1219 ++#define SRST_H_RGA3_1 1220 ++#define SRST_A_RGA3_1 1221 ++#define SRST_RGA3_1_CORE 1222 ++/********Name=SOFTRST_CON77,Offset=0xB34********/ ++#define SRST_REF_PIPE_PHY0 1238 ++#define SRST_REF_PIPE_PHY1 1239 ++#define SRST_REF_PIPE_PHY2 1240 + +#define BUCK1_SLP_SET_MASK BIT(0) +#define BUCK2_SLP_SET_MASK BIT(1) -- Gitee