diff --git a/0001-riscv-kernel.patch b/0001-riscv-kernel.patch index 32d9672bdf46dfca7fc8898d3d77ee134481e2e8..6a2bb48ded06894bcdd456cbe4b19e0e2d97a62f 100644 --- a/0001-riscv-kernel.patch +++ b/0001-riscv-kernel.patch @@ -1,6 +1,6 @@ -From 843321537ee3e992a30f6a86209f4e65a3a4e87f Mon Sep 17 00:00:00 2001 +From 9bb05fda53d4f8b32c022cebf48b41a9ae6cccdc Mon Sep 17 00:00:00 2001 From: Mingzheng Xing -Date: Thu, 4 Dec 2025 18:25:24 +0800 +Date: Tue, 9 Dec 2025 19:21:23 +0800 Subject: [PATCH] riscv kernel Signed-off-by: Mingzheng Xing @@ -16,6 +16,7 @@ Signed-off-by: Mingzheng Xing Documentation/{ => arch}/riscv/uabi.rst | 0 Documentation/{ => arch}/riscv/vector.rst | 0 Documentation/{ => arch}/riscv/vm-layout.rst | 0 + .../bindings/clock/spacemit,k1-pll.yaml | 50 + .../hwlock/xuantie,th1520-hwspinlock.yaml | 34 + .../devicetree/bindings/i2c/lrw,lrw-i2c.yaml | 99 + .../bindings/iio/adc/thead,th1520-adc.yaml | 52 + @@ -38,6 +39,7 @@ Signed-off-by: Mingzheng Xing .../devicetree/bindings/rtc/xgene-rtc.txt | 16 + .../bindings/serial/lrw,lrw-uart.yaml | 49 + .../bindings/serial/snps-dw-apb-uart.yaml | 4 + + .../soc/spacemit/spacemit,k1-syscon.yaml | 95 + .../soc/xuantie/xuantie,th1520-event.yaml | 37 + .../bindings/sound/everest,es7210.txt | 12 + .../bindings/sound/everest,es8156.yaml | 42 + @@ -79,7 +81,7 @@ Signed-off-by: Mingzheng Xing arch/powerpc/kexec/elf_64.c | 8 +- arch/powerpc/kexec/file_load_64.c | 18 +- arch/riscv/Kconfig | 237 +- - arch/riscv/Kconfig.socs | 34 + + arch/riscv/Kconfig.socs | 40 + arch/riscv/Kconfig.vendor | 19 + arch/riscv/Makefile | 23 +- arch/riscv/Makefile.isa | 15 + @@ -105,10 +107,12 @@ Signed-off-by: Mingzheng Xing .../boot/dts/sophgo/mango-top-intc2.dtsi | 62 + .../boot/dts/sophgo/mango-yixin-s2110.dts | 63 + arch/riscv/boot/dts/sophgo/mango.dtsi | 938 + - arch/riscv/boot/dts/spacemit/Makefile | 2 + + arch/riscv/boot/dts/spacemit/Makefile | 3 + .../boot/dts/spacemit/k1-bananapi-f3.dts | 448 + - arch/riscv/boot/dts/spacemit/k1.dtsi | 1221 ++ + arch/riscv/boot/dts/spacemit/k1.dtsi | 1245 ++ arch/riscv/boot/dts/spacemit/k1_pinctrl.dtsi | 1192 ++ + arch/riscv/boot/dts/spacemit/k3-pico.dts | 22 + + arch/riscv/boot/dts/spacemit/k3.dtsi | 601 + arch/riscv/boot/dts/thead/Makefile | 3 +- .../boot/dts/thead/th1520-beaglev-ahead.dts | 222 +- .../dts/thead/th1520-lichee-module-4a.dtsi | 440 +- @@ -125,10 +129,11 @@ Signed-off-by: Mingzheng Xing .../dts/ultrarisc/dp1000-titan-pinctrl.dtsi | 173 + .../boot/dts/ultrarisc/dp1000-titan-v1.dts | 139 + arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 515 + - arch/riscv/configs/defconfig | 38 +- + arch/riscv/configs/defconfig | 41 +- arch/riscv/configs/dp1000_defconfig | 5530 ++++++ arch/riscv/configs/k1_defconfig | 27 + - arch/riscv/configs/openeuler_defconfig | 2022 +- + arch/riscv/configs/k3_defconfig | 10 + + arch/riscv/configs/openeuler_defconfig | 2027 +- arch/riscv/configs/sg2042_defconfig | 9 + arch/riscv/configs/th1520_defconfig | 470 + arch/riscv/errata/andes/errata.c | 13 +- @@ -312,20 +317,17 @@ Signed-off-by: Mingzheng Xing drivers/clk/sophgo/clk-mango.c | 977 + drivers/clk/sophgo/clk.c | 881 + drivers/clk/sophgo/clk.h | 152 + - drivers/clk/spacemit/Kconfig | 9 + - drivers/clk/spacemit/Makefile | 11 + - drivers/clk/spacemit/ccu-spacemit-k1.c | 2123 ++ - drivers/clk/spacemit/ccu-spacemit-k1.h | 81 + - drivers/clk/spacemit/ccu_ddn.c | 161 + - drivers/clk/spacemit/ccu_ddn.h | 86 + - drivers/clk/spacemit/ccu_ddr.c | 272 + - drivers/clk/spacemit/ccu_ddr.h | 44 + - drivers/clk/spacemit/ccu_dpll.c | 124 + - drivers/clk/spacemit/ccu_dpll.h | 76 + - drivers/clk/spacemit/ccu_mix.c | 502 + - drivers/clk/spacemit/ccu_mix.h | 380 + - drivers/clk/spacemit/ccu_pll.c | 286 + - drivers/clk/spacemit/ccu_pll.h | 79 + + drivers/clk/spacemit/Kconfig | 25 + + drivers/clk/spacemit/Makefile | 9 + + drivers/clk/spacemit/ccu-k1.c | 1195 ++ + drivers/clk/spacemit/ccu-k3.c | 2106 ++ + drivers/clk/spacemit/ccu_common.h | 52 + + drivers/clk/spacemit/ccu_ddn.c | 83 + + drivers/clk/spacemit/ccu_ddn.h | 50 + + drivers/clk/spacemit/ccu_mix.c | 278 + + drivers/clk/spacemit/ccu_mix.h | 246 + + drivers/clk/spacemit/ccu_pll.c | 278 + + drivers/clk/spacemit/ccu_pll.h | 126 + drivers/clk/xuantie/Kconfig | 12 + drivers/clk/xuantie/Makefile | 7 + drivers/clk/xuantie/clk-th1520-fm.c | 646 + @@ -1329,11 +1331,18 @@ Signed-off-by: Mingzheng Xing drivers/regulator/spacemit-p1-regulator.c | 268 + drivers/regulator/th1520-aon-regulator.c | 770 + drivers/remoteproc/remoteproc_core.c | 6 +- - drivers/reset/Kconfig | 16 + + drivers/reset/Kconfig | 11 + drivers/reset/Makefile | 3 + drivers/reset/reset-sophgo.c | 163 + - drivers/reset/reset-spacemit-k1.c | 669 + drivers/reset/reset-th1520.c | 170 + + drivers/reset/spacemit/Kconfig | 23 + + drivers/reset/spacemit/Makefile | 4 + + drivers/reset/spacemit/reset-k1.c | 192 + + drivers/reset/spacemit/reset-k1.h | 24 + + drivers/reset/spacemit/reset-k3.c | 335 + + drivers/reset/spacemit/reset-k3.h | 30 + + drivers/reset/spacemit/reset-spacemit.c | 117 + + drivers/reset/spacemit/reset-spacemit.h | 37 + drivers/rpmsg/Kconfig | 4 + drivers/rpmsg/Makefile | 1 + drivers/rpmsg/th1520_rpmsg.c | 958 + @@ -1602,7 +1611,8 @@ Signed-off-by: Mingzheng Xing include/drm/bridge/dw_hdmi.h | 5 + .../dt-bindings/clock/sophgo-mango-clock.h | 165 + include/dt-bindings/clock/sophgo.h | 15 + - include/dt-bindings/clock/spacemit-k1-clock.h | 223 + + .../dt-bindings/clock/spacemit,k1-syscon.h | 394 + + .../dt-bindings/clock/spacemit,k3-syscon.h | 746 + include/dt-bindings/clock/th1520-audiosys.h | 35 + include/dt-bindings/clock/th1520-dspsys.h | 33 + .../dt-bindings/clock/th1520-fm-ap-clock.h | 513 + @@ -1616,7 +1626,6 @@ Signed-off-by: Mingzheng Xing include/dt-bindings/pinctrl/k1-pinctrl.h | 198 + .../dt-bindings/pinctrl/ur-dp1000-pinctrl.h | 64 + .../dt-bindings/reset/sophgo-mango-resets.h | 96 + - include/dt-bindings/reset/spacemit-k1-reset.h | 126 + .../dt-bindings/reset/xuantie,th1520-reset.h | 28 + .../dt-bindings/soc/th1520_system_status.h | 38 + .../dt-bindings/soc/xuantie,th1520-iopmp.h | 41 + @@ -1651,6 +1660,9 @@ Signed-off-by: Mingzheng Xing include/linux/sync_core.h | 16 +- include/linux/th1520_proc_debug.h | 13 + include/linux/th1520_rpmsg.h | 99 + + include/soc/spacemit/k1-syscon.h | 149 + + include/soc/spacemit/k3-syscon.h | 271 + + include/soc/spacemit/spacemit-syscon.h | 20 + include/soc/xuantie/th1520_system_monitor.h | 71 + include/soc/xuantie/th1520_system_status.h | 36 + include/uapi/drm/drm_fourcc.h | 90 + @@ -1720,11 +1732,14 @@ Signed-off-by: Mingzheng Xing .../arch/riscv/lrw/lrw-core/l3cache.json | 32 + .../arch/riscv/lrw/lrw-core/ldst.json | 67 + .../arch/riscv/lrw/lrw-core/mem.json | 182 + + .../arch/riscv/lrw/lrw-core/metrics.json | 234 + .../arch/riscv/lrw/lrw-core/pipeline.json | 132 + .../arch/riscv/lrw/lrw-core/spe.json | 7 + .../arch/riscv/lrw/lrw-core/tlb.json | 82 + .../arch/riscv/lrw/lrw-core/vec.json | 82 + tools/perf/pmu-events/arch/riscv/mapfile.csv | 3 + + .../arch/riscv/riscv-sbi-firmware.json | 2 +- + .../arch/riscv/sifive/u74/firmware.json | 2 +- .../arch/riscv/thead/c900-legacy/cache.json | 67 + .../riscv/thead/c900-legacy/firmware.json | 68 + .../riscv/thead/c900-legacy/instruction.json | 72 + @@ -1748,7 +1763,7 @@ Signed-off-by: Mingzheng Xing .../selftests/riscv/sse/run_sse_test.sh | 44 + .../selftests/riscv/vector/vstate_prctl.c | 10 +- virt/kvm/eventfd.c | 12 +- - 1743 files changed, 620657 insertions(+), 4201 deletions(-) + 1758 files changed, 623243 insertions(+), 4203 deletions(-) rename Documentation/{ => arch}/riscv/acpi.rst (100%) rename Documentation/{ => arch}/riscv/boot-image-header.rst (100%) rename Documentation/{ => arch}/riscv/boot.rst (100%) @@ -1759,6 +1774,7 @@ Signed-off-by: Mingzheng Xing rename Documentation/{ => arch}/riscv/uabi.rst (100%) rename Documentation/{ => arch}/riscv/vector.rst (100%) rename Documentation/{ => arch}/riscv/vm-layout.rst (100%) + create mode 100644 Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml create mode 100644 Documentation/devicetree/bindings/hwlock/xuantie,th1520-hwspinlock.yaml create mode 100644 Documentation/devicetree/bindings/i2c/lrw,lrw-i2c.yaml create mode 100644 Documentation/devicetree/bindings/iio/adc/thead,th1520-adc.yaml @@ -1775,6 +1791,7 @@ Signed-off-by: Mingzheng Xing create mode 100644 Documentation/devicetree/bindings/pwm/xuantie,th1520-pwm.yaml create mode 100644 Documentation/devicetree/bindings/reset/xuantie,th1520-reset.yaml create mode 100644 Documentation/devicetree/bindings/serial/lrw,lrw-uart.yaml + create mode 100644 Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml create mode 100644 Documentation/devicetree/bindings/soc/xuantie/xuantie,th1520-event.yaml create mode 100644 Documentation/devicetree/bindings/sound/everest,es7210.txt create mode 100644 Documentation/devicetree/bindings/sound/everest,es8156.yaml @@ -1818,6 +1835,8 @@ Signed-off-by: Mingzheng Xing create mode 100644 arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts create mode 100644 arch/riscv/boot/dts/spacemit/k1.dtsi create mode 100644 arch/riscv/boot/dts/spacemit/k1_pinctrl.dtsi + create mode 100644 arch/riscv/boot/dts/spacemit/k3-pico.dts + create mode 100644 arch/riscv/boot/dts/spacemit/k3.dtsi create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts create mode 100644 arch/riscv/boot/dts/thead/th1520-lpi4a-dsi0.dts create mode 100644 arch/riscv/boot/dts/thead/th1520-lpi4a-hx8279.dts @@ -1831,6 +1850,7 @@ Signed-off-by: Mingzheng Xing create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000.dtsi create mode 100644 arch/riscv/configs/dp1000_defconfig create mode 100644 arch/riscv/configs/k1_defconfig + create mode 100644 arch/riscv/configs/k3_defconfig create mode 100644 arch/riscv/configs/sg2042_defconfig create mode 100644 arch/riscv/configs/th1520_defconfig create mode 100644 arch/riscv/include/asm/arch_hweight.h @@ -1881,14 +1901,11 @@ Signed-off-by: Mingzheng Xing create mode 100644 drivers/clk/sophgo/clk.h create mode 100644 drivers/clk/spacemit/Kconfig create mode 100644 drivers/clk/spacemit/Makefile - create mode 100644 drivers/clk/spacemit/ccu-spacemit-k1.c - create mode 100644 drivers/clk/spacemit/ccu-spacemit-k1.h + create mode 100644 drivers/clk/spacemit/ccu-k1.c + create mode 100644 drivers/clk/spacemit/ccu-k3.c + create mode 100644 drivers/clk/spacemit/ccu_common.h create mode 100644 drivers/clk/spacemit/ccu_ddn.c create mode 100644 drivers/clk/spacemit/ccu_ddn.h - create mode 100644 drivers/clk/spacemit/ccu_ddr.c - create mode 100644 drivers/clk/spacemit/ccu_ddr.h - create mode 100644 drivers/clk/spacemit/ccu_dpll.c - create mode 100644 drivers/clk/spacemit/ccu_dpll.h create mode 100644 drivers/clk/spacemit/ccu_mix.c create mode 100644 drivers/clk/spacemit/ccu_mix.h create mode 100644 drivers/clk/spacemit/ccu_pll.c @@ -2733,8 +2750,15 @@ Signed-off-by: Mingzheng Xing create mode 100644 drivers/regulator/spacemit-p1-regulator.c create mode 100644 drivers/regulator/th1520-aon-regulator.c create mode 100644 drivers/reset/reset-sophgo.c - create mode 100644 drivers/reset/reset-spacemit-k1.c create mode 100644 drivers/reset/reset-th1520.c + create mode 100644 drivers/reset/spacemit/Kconfig + create mode 100644 drivers/reset/spacemit/Makefile + create mode 100644 drivers/reset/spacemit/reset-k1.c + create mode 100644 drivers/reset/spacemit/reset-k1.h + create mode 100644 drivers/reset/spacemit/reset-k3.c + create mode 100644 drivers/reset/spacemit/reset-k3.h + create mode 100644 drivers/reset/spacemit/reset-spacemit.c + create mode 100644 drivers/reset/spacemit/reset-spacemit.h create mode 100644 drivers/rpmsg/th1520_rpmsg.c create mode 100644 drivers/rtc/rtc-astbmc.c create mode 100644 drivers/rtc/rtc-spacemit-p1.c @@ -2955,7 +2979,8 @@ Signed-off-by: Mingzheng Xing create mode 100644 include/asm-generic/ticket_spinlock.h create mode 100644 include/dt-bindings/clock/sophgo-mango-clock.h create mode 100644 include/dt-bindings/clock/sophgo.h - create mode 100644 include/dt-bindings/clock/spacemit-k1-clock.h + create mode 100644 include/dt-bindings/clock/spacemit,k1-syscon.h + create mode 100644 include/dt-bindings/clock/spacemit,k3-syscon.h create mode 100644 include/dt-bindings/clock/th1520-audiosys.h create mode 100644 include/dt-bindings/clock/th1520-dspsys.h create mode 100644 include/dt-bindings/clock/th1520-fm-ap-clock.h @@ -2969,7 +2994,6 @@ Signed-off-by: Mingzheng Xing create mode 100644 include/dt-bindings/pinctrl/k1-pinctrl.h create mode 100644 include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h create mode 100644 include/dt-bindings/reset/sophgo-mango-resets.h - create mode 100644 include/dt-bindings/reset/spacemit-k1-reset.h create mode 100644 include/dt-bindings/reset/xuantie,th1520-reset.h create mode 100644 include/dt-bindings/soc/th1520_system_status.h create mode 100644 include/dt-bindings/soc/xuantie,th1520-iopmp.h @@ -2983,6 +3007,9 @@ Signed-off-by: Mingzheng Xing create mode 100644 include/linux/riscv_sse.h create mode 100644 include/linux/th1520_proc_debug.h create mode 100644 include/linux/th1520_rpmsg.h + create mode 100644 include/soc/spacemit/k1-syscon.h + create mode 100644 include/soc/spacemit/k3-syscon.h + create mode 100644 include/soc/spacemit/spacemit-syscon.h create mode 100644 include/soc/xuantie/th1520_system_monitor.h create mode 100644 include/soc/xuantie/th1520_system_status.h create mode 100644 include/uapi/drm/vs_drm.h @@ -3021,6 +3048,7 @@ Signed-off-by: Mingzheng Xing create mode 100644 tools/perf/pmu-events/arch/riscv/lrw/lrw-core/l3cache.json create mode 100644 tools/perf/pmu-events/arch/riscv/lrw/lrw-core/ldst.json create mode 100644 tools/perf/pmu-events/arch/riscv/lrw/lrw-core/mem.json + create mode 100644 tools/perf/pmu-events/arch/riscv/lrw/lrw-core/metrics.json create mode 100644 tools/perf/pmu-events/arch/riscv/lrw/lrw-core/pipeline.json create mode 100644 tools/perf/pmu-events/arch/riscv/lrw/lrw-core/spe.json create mode 100644 tools/perf/pmu-events/arch/riscv/lrw/lrw-core/tlb.json @@ -3396,6 +3424,62 @@ diff --git a/Documentation/riscv/vm-layout.rst b/Documentation/arch/riscv/vm-lay similarity index 100% rename from Documentation/riscv/vm-layout.rst rename to Documentation/arch/riscv/vm-layout.rst +diff --git a/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml b/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml +new file mode 100644 +index 000000000000..06bafd68c00a +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml +@@ -0,0 +1,50 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/spacemit,k1-pll.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: SpacemiT K1 PLL ++ ++maintainers: ++ - Haylen Chu ++ ++properties: ++ compatible: ++ const: spacemit,k1-pll ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ description: External 24MHz oscillator ++ ++ spacemit,mpmu: ++ $ref: /schemas/types.yaml#/definitions/phandle ++ description: ++ Phandle to the "Main PMU (MPMU)" syscon. It is used to check PLL ++ lock status. ++ ++ "#clock-cells": ++ const: 1 ++ description: ++ See for valid indices. ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - spacemit,mpmu ++ - "#clock-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ clock-controller@d4090000 { ++ compatible = "spacemit,k1-pll"; ++ reg = <0xd4090000 0x1000>; ++ clocks = <&vctcxo_24m>; ++ spacemit,mpmu = <&sysctl_mpmu>; ++ #clock-cells = <1>; ++ }; diff --git a/Documentation/devicetree/bindings/hwlock/xuantie,th1520-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/xuantie,th1520-hwspinlock.yaml new file mode 100644 index 000000000000..8d36beae9676 @@ -5154,6 +5238,107 @@ index 17c553123f96..ba5c8cd476c7 100644 - const: snps,dw-apb-uart reg: +diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml +new file mode 100644 +index 000000000000..133a391ee68c +--- /dev/null ++++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml +@@ -0,0 +1,95 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-syscon.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: SpacemiT K1 SoC System Controller ++ ++maintainers: ++ - Haylen Chu ++ ++description: ++ System controllers found on SpacemiT K1 SoC, which are capable of ++ clock, reset and power-management functions. ++ ++properties: ++ compatible: ++ enum: ++ - spacemit,k1-syscon-apbc ++ - spacemit,k1-syscon-apmu ++ - spacemit,k1-syscon-mpmu ++ - spacemit,k1-syscon-rcpu ++ - spacemit,k1-syscon-rcpu2 ++ - spacemit,k1-syscon-apbc2 ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 4 ++ ++ clock-names: ++ items: ++ - const: osc ++ - const: vctcxo_1m ++ - const: vctcxo_3m ++ - const: vctcxo_24m ++ ++ "#clock-cells": ++ const: 1 ++ description: ++ See for valid indices. ++ ++ "#power-domain-cells": ++ const: 1 ++ ++ "#reset-cells": ++ const: 1 ++ ++required: ++ - compatible ++ - reg ++ - "#reset-cells" ++ ++allOf: ++ - if: ++ properties: ++ compatible: ++ contains: ++ enum: ++ - spacemit,k1-syscon-apmu ++ - spacemit,k1-syscon-mpmu ++ then: ++ required: ++ - "#power-domain-cells" ++ else: ++ properties: ++ "#power-domain-cells": false ++ - if: ++ properties: ++ compatible: ++ contains: ++ enum: ++ - spacemit,k1-syscon-apbc ++ - spacemit,k1-syscon-apmu ++ - spacemit,k1-syscon-mpmu ++ then: ++ required: ++ - clocks ++ - clock-names ++ - "#clock-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ system-controller@d4050000 { ++ compatible = "spacemit,k1-syscon-mpmu"; ++ reg = <0xd4050000 0x209c>; ++ clocks = <&osc>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; ++ clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; ++ #clock-cells = <1>; ++ #power-domain-cells = <1>; ++ #reset-cells = <1>; ++ }; diff --git a/Documentation/devicetree/bindings/soc/xuantie/xuantie,th1520-event.yaml b/Documentation/devicetree/bindings/soc/xuantie/xuantie,th1520-event.yaml new file mode 100644 index 000000000000..0448f9897cd4 @@ -7224,7 +7409,7 @@ index 3be10e723b2c..2402e7a0a677 100644 def_bool $(cc-option,-mstack-protector-guard=tls -mstack-protector-guard-reg=tp -mstack-protector-guard-offset=0) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs -index 30fd6a512828..a5fb3bc6f716 100644 +index 30fd6a512828..e743f7e84e9d 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -22,6 +22,11 @@ config SOC_SIFIVE @@ -7263,7 +7448,7 @@ index 30fd6a512828..a5fb3bc6f716 100644 config ARCH_VIRT def_bool SOC_VIRT -@@ -111,4 +133,16 @@ config SOC_CANAAN_K210_DTB_SOURCE +@@ -111,4 +133,22 @@ config SOC_CANAAN_K210_DTB_SOURCE endif # ARCH_CANAAN @@ -7278,6 +7463,12 @@ index 30fd6a512828..a5fb3bc6f716 100644 + depends on SOC_SPACEMIT + help + select Spacemit k1 Platform SoCs. ++ ++config SOC_SPACEMIT_K3 ++ bool "Spacemit k3 Platform SoCs." ++ depends on SOC_SPACEMIT ++ help ++ select Spacemit k3 Platform SoCs. + endmenu # "SoC selection" diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor @@ -15472,11 +15663,12 @@ index 000000000000..57f304fc778f +}; diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile new file mode 100644 -index 000000000000..492746086409 +index 000000000000..6fc1d80c21f0 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/Makefile -@@ -0,0 +1,2 @@ +@@ -0,0 +1,3 @@ +dtb-$(CONFIG_SOC_SPACEMIT_K1) += k1-bananapi-f3.dtb ++dtb-$(CONFIG_SOC_SPACEMIT_K3) += k3-pico.dtb +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts new file mode 100644 @@ -15934,17 +16126,16 @@ index 000000000000..64f848173446 +}; diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi new file mode 100644 -index 000000000000..1c89ea8f0f80 +index 000000000000..0354ca75f658 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -0,0 +1,1221 @@ +@@ -0,0 +1,1245 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Spacemit, Inc */ + +/dts-v1/; + -+#include -+#include ++#include +#include +#include + @@ -16292,57 +16483,32 @@ index 000000000000..1c89ea8f0f80 + }; + + clocks { -+ #address-cells = <0x2>; -+ #size-cells = <0x2>; -+ ranges; -+ -+ vctcxo_24: clock-vctcxo_24 { -+ #clock-cells = <0>; ++ vctcxo_1m: clock-1m { + compatible = "fixed-clock"; -+ clock-frequency = <24000000>; -+ clock-output-names = "vctcxo_24"; -+ }; -+ -+ vctcxo_3: clock-vctcxo_3 { ++ clock-frequency = <1000000>; ++ clock-output-names = "vctcxo_1m"; + #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <3000000>; -+ clock-output-names = "vctcxo_3"; + }; + -+ vctcxo_1: clock-vctcxo_1 { -+ #clock-cells = <0>; ++ vctcxo_24m: clock-24m { + compatible = "fixed-clock"; -+ clock-frequency = <1000000>; -+ clock-output-names = "vctcxo_1"; -+ }; -+ -+ pll1_2457p6_vco: clock-pll1_2457p6_vco { ++ clock-frequency = <24000000>; ++ clock-output-names = "vctcxo_24m"; + #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <2457600000>; -+ clock-output-names = "pll1_2457p6_vco"; + }; + -+ clk_32k: clock-clk32k { -+ #clock-cells = <0>; ++ vctcxo_3m: clock-3m { + compatible = "fixed-clock"; -+ clock-frequency = <32000>; -+ clock-output-names = "clk_32k"; -+ }; -+ -+ pll_clk_cluster0: clock-pll_clk_cluster0 { ++ clock-frequency = <3000000>; ++ clock-output-names = "vctcxo_3m"; + #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <10000000>; -+ clock-output-names = "pll_clk_cluster0"; + }; + -+ pll_clk_cluster1: clock-pll_clk_cluster1 { -+ #clock-cells = <0>; ++ osc_32k: clock-32k { + compatible = "fixed-clock"; -+ clock-frequency = <10000000>; -+ clock-output-names = "pll_clk_cluster1"; ++ clock-frequency = <32000>; ++ clock-output-names = "osc_32k"; ++ #clock-cells = <0>; + }; + }; + @@ -16415,47 +16581,6 @@ index 000000000000..1c89ea8f0f80 + reg = <0x0 0xE4000000 0x0 0x00010000>; + }; + -+ ccu: clock-controller@d4050000 { -+ compatible = "spacemit,k1-clock"; -+ reg = <0x0 0xd4050000 0x0 0x209c>, -+ <0x0 0xd4282800 0x0 0x400>, -+ <0x0 0xd4015000 0x0 0x1000>, -+ <0x0 0xd4090000 0x0 0x1000>, -+ <0x0 0xd4282c00 0x0 0x400>, -+ <0x0 0xd8440000 0x0 0x98>, -+ <0x0 0xc0000000 0x0 0x4280>, -+ <0x0 0xf0610000 0x0 0x20>, -+ <0x0 0xc0880000 0x0 0x2050>, -+ <0x0 0xc0888000 0x0 0x30>; -+ reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", -+ "dciu", "ddrc", "apbc2", "rcpu", "rcpu2"; -+ clocks = <&vctcxo_24>, <&vctcxo_3>, <&vctcxo_1>, -+ <&pll1_2457p6_vco>, <&clk_32k>; -+ clock-names = "vctcxo_24", "vctcxo_3", "vctcxo_1", -+ "pll1_2457p6_vco", -+ "clk_32k"; -+ #clock-cells = <1>; -+ status = "okay"; -+ }; -+ -+ reset: reset-controller@d4050000 { -+ compatible = "spacemit,k1-reset"; -+ reg = <0x0 0xd4050000 0x0 0x209c>, -+ <0x0 0xd4282800 0x0 0x400>, -+ <0x0 0xd4015000 0x0 0x1000>, -+ <0x0 0xd4090000 0x0 0x1000>, -+ <0x0 0xd4282c00 0x0 0x400>, -+ <0x0 0xd8440000 0x0 0x98>, -+ <0x0 0xc0000000 0x0 0x4280>, -+ <0x0 0xf0610000 0x0 0x20>, -+ <0x0 0xc0880000 0x0 0x2050>, -+ <0x0 0xc0888000 0x0 0x30>; -+ reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", -+ "dciu", "ddrc", "apbc2", "rcpu", "rcpu2"; -+ #reset-cells = <1>; -+ status = "okay"; -+ }; -+ + intc: interrupt-controller@e0000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; @@ -16476,6 +16601,67 @@ index 000000000000..1c89ea8f0f80 + riscv,ndev = <159>; + }; + ++ syscon_mpmu: system-controller@d4050000 { ++ compatible = "spacemit,k1-syscon-mpmu"; ++ reg = <0x0 0xd4050000 0x0 0x209c>; ++ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, ++ <&vctcxo_24m>; ++ clock-names = "osc", "vctcxo_1m", "vctcxo_3m", ++ "vctcxo_24m"; ++ #clock-cells = <1>; ++ #power-domain-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ pll: clock-controller@d4090000 { ++ compatible = "spacemit,k1-pll"; ++ reg = <0x0 0xd4090000 0x0 0x1000>; ++ clocks = <&vctcxo_24m>; ++ spacemit,mpmu = <&syscon_mpmu>; ++ #clock-cells = <1>; ++ }; ++ ++ syscon_apmu: system-controller@d4282800 { ++ compatible = "spacemit,k1-syscon-apmu"; ++ reg = <0x0 0xd4282800 0x0 0x400>; ++ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, ++ <&vctcxo_24m>; ++ clock-names = "osc", "vctcxo_1m", "vctcxo_3m", ++ "vctcxo_24m"; ++ #clock-cells = <1>; ++ #power-domain-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ syscon_apbc: system-controller@d4015000 { ++ compatible = "spacemit,k1-syscon-apbc"; ++ reg = <0x0 0xd4015000 0x0 0x1000>; ++ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, ++ <&vctcxo_24m>; ++ clock-names = "osc", "vctcxo_1m", "vctcxo_3m", ++ "vctcxo_24m"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ syscon_apbc2: system-controller@f0610000 { ++ compatible = "spacemit,k1-syscon-apbc2"; ++ reg = <0x0 0xf0610000 0x0 0x20>; ++ #reset-cells = <1>; ++ }; ++ ++ syscon_rcpu: system-controller@c0880000 { ++ compatible = "spacemit,k1-syscon-rcpu"; ++ reg = <0x0 0xc0880000 0x0 0x2048>; ++ #reset-cells = <1>; ++ }; ++ ++ syscon_rcpu2: system-controller@c0888000 { ++ compatible = "spacemit,k1-syscon-rcpu2"; ++ reg = <0x0 0xc0888000 0x0 0x28>; ++ #reset-cells = <1>; ++ }; ++ + pinctrl: pinctrl@d401e000 { + compatible = "pinctrl-spacemit-k1"; + reg = <0x0 0xd401e000 0x0 0x250>, @@ -16489,9 +16675,10 @@ index 000000000000..1c89ea8f0f80 + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xff77>; + -+ clocks = <&ccu CLK_AIB>; -+ clock-names = "clk_aib"; -+ resets = <&reset RESET_AIB>; ++ clocks = <&syscon_apbc CLK_AIB>, ++ <&syscon_apbc CLK_AIB_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_AIB>; + reset-names = "aib_rst"; + + interrupt-parent = <&intc>; @@ -16509,8 +16696,8 @@ index 000000000000..1c89ea8f0f80 + reg = <0x0 0xd4000000 0x0 0x4000>; + interrupts = <72>; + interrupt-parent = <&intc>; -+ clocks = <&ccu CLK_DMA>; -+ resets = <&reset RESET_DMA>; ++ clocks = <&syscon_apmu CLK_DMA>; ++ resets = <&syscon_apmu RESET_DMA>; + #dma-cells= <2>; + #dma-channels = <16>; + max-burst-size = <64>; @@ -16525,9 +16712,10 @@ index 000000000000..1c89ea8f0f80 + reg = <0x0 0xd4017000 0x0 0x100>; + interrupt-parent = <&intc>; + interrupts = <42>; -+ clocks = <&ccu CLK_UART1>, <&ccu CLK_SLOW_UART>; ++ clocks = <&syscon_apbc CLK_UART0>, ++ <&syscon_apbc CLK_UART0_BUS>; + clock-names = "core", "bus"; -+ resets = <&reset RESET_UART1>; ++ resets = <&syscon_apbc RESET_UART0>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; @@ -16538,9 +16726,10 @@ index 000000000000..1c89ea8f0f80 + reg = <0x0 0xd4017100 0x0 0x100>; + interrupt-parent = <&intc>; + interrupts = <44>; -+ clocks = <&ccu CLK_UART2>, <&ccu CLK_SLOW_UART>; ++ clocks = <&syscon_apbc CLK_UART2>, ++ <&syscon_apbc CLK_UART2_BUS>; + clock-names = "core", "bus"; -+ resets = <&reset RESET_UART2>; ++ resets = <&syscon_apbc RESET_UART2>; + status = "disabled"; + }; + @@ -16549,9 +16738,10 @@ index 000000000000..1c89ea8f0f80 + reg = <0x0 0xd4017200 0x0 0x100>; + interrupt-parent = <&intc>; + interrupts = <45>; -+ clocks = <&ccu CLK_UART3>, <&ccu CLK_SLOW_UART>; ++ clocks = <&syscon_apbc CLK_UART3>, ++ <&syscon_apbc CLK_UART3_BUS>; + clock-names = "core", "bus"; -+ resets = <&reset RESET_UART3>; ++ resets = <&syscon_apbc RESET_UART3>; + status = "disabled"; + }; + @@ -16560,9 +16750,10 @@ index 000000000000..1c89ea8f0f80 + interrupt-parent = <&intc>; + reg = <0x0 0xd4017300 0x0 0x100>; + interrupts = <46>; -+ clocks = <&ccu CLK_UART4>, <&ccu CLK_SLOW_UART>; ++ clocks = <&syscon_apbc CLK_UART4>, ++ <&syscon_apbc CLK_UART4_BUS>; + clock-names = "core", "bus"; -+ resets = <&reset RESET_UART4>; ++ resets = <&syscon_apbc RESET_UART4>; + status = "disabled"; + }; + @@ -16571,9 +16762,10 @@ index 000000000000..1c89ea8f0f80 + interrupt-parent = <&intc>; + reg = <0x0 0xd4017400 0x0 0x100>; + interrupts = <47>; -+ clocks = <&ccu CLK_UART5>, <&ccu CLK_SLOW_UART>; ++ clocks = <&syscon_apbc CLK_UART5>, ++ <&syscon_apbc CLK_UART5_BUS>; + clock-names = "core", "bus"; -+ resets = <&reset RESET_UART5>; ++ resets = <&syscon_apbc RESET_UART5>; + status = "disabled"; + }; + @@ -16582,9 +16774,10 @@ index 000000000000..1c89ea8f0f80 + interrupt-parent = <&intc>; + reg = <0x0 0xd4017500 0x0 0x100>; + interrupts = <48>; -+ clocks = <&ccu CLK_UART6>, <&ccu CLK_SLOW_UART>; ++ clocks = <&syscon_apbc CLK_UART6>, ++ <&syscon_apbc CLK_UART6_BUS>; + clock-names = "core", "bus"; -+ resets = <&reset RESET_UART6>; ++ resets = <&syscon_apbc RESET_UART6>; + status = "disabled"; + }; + @@ -16593,9 +16786,10 @@ index 000000000000..1c89ea8f0f80 + interrupt-parent = <&intc>; + reg = <0x0 0xd4017600 0x0 0x100>; + interrupts = <49>; -+ clocks = <&ccu CLK_UART7>, <&ccu CLK_SLOW_UART>; ++ clocks = <&syscon_apbc CLK_UART7>, ++ <&syscon_apbc CLK_UART7_BUS>; + clock-names = "core", "bus"; -+ resets = <&reset RESET_UART7>; ++ resets = <&syscon_apbc RESET_UART7>; + status = "disabled"; + }; + @@ -16604,9 +16798,10 @@ index 000000000000..1c89ea8f0f80 + interrupt-parent = <&intc>; + reg = <0x0 0xd4017700 0x0 0x100>; + interrupts = <50>; -+ clocks = <&ccu CLK_UART8>, <&ccu CLK_SLOW_UART>; ++ clocks = <&syscon_apbc CLK_UART8>, ++ <&syscon_apbc CLK_UART8_BUS>; + clock-names = "core", "bus"; -+ resets = <&reset RESET_UART8>; ++ resets = <&syscon_apbc RESET_UART8>; + status = "disabled"; + }; + @@ -16615,9 +16810,10 @@ index 000000000000..1c89ea8f0f80 + interrupt-parent = <&intc>; + reg = <0x0 0xd4017800 0x0 0x100>; + interrupts = <51>; -+ clocks = <&ccu CLK_UART9>, <&ccu CLK_SLOW_UART>; ++ clocks = <&syscon_apbc CLK_UART9>, ++ <&syscon_apbc CLK_UART9_BUS>; + clock-names = "core", "bus"; -+ resets = <&reset RESET_UART9>; ++ resets = <&syscon_apbc RESET_UART9>; + status = "disabled"; + }; + @@ -16629,8 +16825,10 @@ index 000000000000..1c89ea8f0f80 + #size-cells = <0>; + interrupt-parent = <&intc>; + interrupts = <36>; -+ clocks = <&ccu CLK_TWSI0>; -+ resets = <&reset RESET_TWSI0>; ++ clocks = <&syscon_apbc CLK_TWSI0>, ++ <&syscon_apbc CLK_TWSI0_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_TWSI0>; + spacemit,i2c-master-code = /bits/ 8 <0x0e>; + spacemit,i2c-clk-rate = <32000000>; + spacemit,i2c-lcr = <0x82c469f>; @@ -16648,8 +16846,10 @@ index 000000000000..1c89ea8f0f80 + #size-cells = <0>; + interrupt-parent = <&intc>; + interrupts = <37>; -+ clocks = <&ccu CLK_TWSI1>; -+ resets = <&reset RESET_TWSI1>; ++ clocks = <&syscon_apbc CLK_TWSI1>, ++ <&syscon_apbc CLK_TWSI1_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_TWSI1>; + spacemit,i2c-master-code = /bits/ 8 <0x0e>; + spacemit,i2c-clk-rate = <32000000>; + spacemit,i2c-lcr = <0x82c469f>; @@ -16667,8 +16867,10 @@ index 000000000000..1c89ea8f0f80 + #size-cells = <0>; + interrupt-parent = <&intc>; + interrupts = <38>; -+ clocks = <&ccu CLK_TWSI2>; -+ resets = <&reset RESET_TWSI2>; ++ clocks = <&syscon_apbc CLK_TWSI2>, ++ <&syscon_apbc CLK_TWSI2_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_TWSI2>; + spacemit,i2c-master-code = /bits/ 8 <0x0e>; + spacemit,i2c-clk-rate = <32000000>; + spacemit,i2c-lcr = <0x82c469f>; @@ -16686,8 +16888,10 @@ index 000000000000..1c89ea8f0f80 + #size-cells = <0>; + interrupt-parent = <&intc>; + interrupts = <40>; -+ clocks = <&ccu CLK_TWSI4>; -+ resets = <&reset RESET_TWSI4>; ++ clocks = <&syscon_apbc CLK_TWSI4>, ++ <&syscon_apbc CLK_TWSI4_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_TWSI4>; + spacemit,i2c-master-code = /bits/ 8 <0x0e>; + spacemit,i2c-clk-rate = <32000000>; + spacemit,i2c-lcr = <0x82c469f>; @@ -16705,8 +16909,10 @@ index 000000000000..1c89ea8f0f80 + #size-cells = <0>; + interrupt-parent = <&intc>; + interrupts = <41>; -+ clocks = <&ccu CLK_TWSI5>; -+ resets = <&reset RESET_TWSI5>; ++ clocks = <&syscon_apbc CLK_TWSI5>, ++ <&syscon_apbc CLK_TWSI5_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_TWSI5>; + spacemit,i2c-master-code = /bits/ 8 <0x0e>; + spacemit,i2c-clk-rate = <32000000>; + spacemit,i2c-lcr = <0x82c469f>; @@ -16724,8 +16930,10 @@ index 000000000000..1c89ea8f0f80 + #size-cells = <0>; + interrupt-parent = <&intc>; + interrupts = <70>; -+ clocks = <&ccu CLK_TWSI6>; -+ resets = <&reset RESET_TWSI6>; ++ clocks = <&syscon_apbc CLK_TWSI6>, ++ <&syscon_apbc CLK_TWSI6_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_TWSI6>; + spacemit,i2c-master-code = /bits/ 8 <0x0e>; + spacemit,i2c-clk-rate = <32000000>; + spacemit,i2c-lcr = <0x82c469f>; @@ -16743,8 +16951,10 @@ index 000000000000..1c89ea8f0f80 + #size-cells = <0>; + interrupt-parent = <&intc>; + interrupts = <18>; -+ clocks = <&ccu CLK_TWSI7>; -+ resets = <&reset RESET_TWSI7>; ++ clocks = <&syscon_apbc CLK_TWSI7>, ++ <&syscon_apbc CLK_TWSI7_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_TWSI7>; + spacemit,i2c-master-code = /bits/ 8 <0x0e>; + spacemit,i2c-clk-rate = <32000000>; + spacemit,i2c-lcr = <0x82c469f>; @@ -16762,8 +16972,10 @@ index 000000000000..1c89ea8f0f80 + #size-cells = <0>; + interrupt-parent = <&intc>; + interrupts = <19>; -+ clocks = <&ccu CLK_TWSI8>; -+ resets = <&reset RESET_TWSI8>; ++ clocks = <&syscon_apbc CLK_TWSI8>, ++ <&syscon_apbc CLK_TWSI8_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_TWSI8>; + spacemit,i2c-master-code = /bits/ 8 <0x0e>; + spacemit,i2c-clk-rate = <32000000>; + spacemit,i2c-lcr = <0x82c469f>; @@ -16783,8 +16995,8 @@ index 000000000000..1c89ea8f0f80 + dma-names = "rx", "tx"; + interrupt-parent = <&intc>; + interrupts = <56>; -+ clocks = <&ccu CLK_SSPA0>; -+ resets = <&reset RESET_SSPA0>; ++ clocks = <&syscon_apbc CLK_SSPA0>; ++ resets = <&syscon_apbc RESET_SSPA0>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&dram_range0>; @@ -16802,8 +17014,8 @@ index 000000000000..1c89ea8f0f80 + dma-names = "rx", "tx"; + interrupt-parent = <&intc>; + interrupts = <57>; -+ clocks = <&ccu CLK_SSPA1>; -+ resets = <&reset RESET_SSPA1>; ++ clocks = <&syscon_apbc CLK_SSPA1>; ++ resets = <&syscon_apbc RESET_SSPA1>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&dram_range0>; @@ -16821,8 +17033,8 @@ index 000000000000..1c89ea8f0f80 + dma-names = "rx", "tx"; + interrupt-parent = <&intc>; + interrupts = <55>; -+ clocks = <&ccu CLK_SSP3>; -+ resets = <&reset RESET_SSP3>; ++ clocks = <&syscon_apbc CLK_SSP3>; ++ resets = <&syscon_apbc RESET_SSP3>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&dram_range0>; @@ -16841,11 +17053,11 @@ index 000000000000..1c89ea8f0f80 + k1,qspi-sfa2ad = <0x100000>; + k1,qspi-sfb1ad = <0x100000>; + k1,qspi-sfb2ad = <0x100000>; -+ clocks = <&ccu CLK_QSPI>, -+ <&ccu CLK_QSPI_BUS>; -+ clock-names = "qspi_clk", "qspi_bus_clk"; -+ resets = <&reset RESET_QSPI>, -+ <&reset RESET_QSPI_BUS>; ++ clocks = <&syscon_apmu CLK_QSPI_BUS>, ++ <&syscon_apmu CLK_QSPI>; ++ clock-names = "qspi_bus_clk", "qspi_clk"; ++ resets = <&syscon_apmu RESET_QSPI>, ++ <&syscon_apmu RESET_QSPI_BUS>; + reset-names = "qspi_reset", "qspi_bus_reset"; + k1,qspi-pmuap-reg = <0xd4282860>; + k1,qspi-mpmu-acgr-reg = <0xd4051024>; @@ -16866,8 +17078,8 @@ index 000000000000..1c89ea8f0f80 + compatible = "spacemit,k1-pwm"; + reg = <0x0 0xd401a000 0x0 0x10>; + #pwm-cells = <1>; -+ clocks = <&ccu CLK_PWM0>; -+ resets = <&reset RESET_PWM0>; ++ clocks = <&syscon_apbc CLK_PWM0>; ++ resets = <&syscon_apbc RESET_PWM0>; + status = "disabled"; + }; + @@ -16875,8 +17087,8 @@ index 000000000000..1c89ea8f0f80 + compatible = "spacemit,k1-pwm"; + reg = <0x0 0xd401a400 0x0 0x10>; + #pwm-cells = <1>; -+ clocks = <&ccu CLK_PWM1>; -+ resets = <&reset RESET_PWM1>; ++ clocks = <&syscon_apbc CLK_PWM1>; ++ resets = <&syscon_apbc RESET_PWM1>; + status = "disabled"; + }; + @@ -16884,8 +17096,8 @@ index 000000000000..1c89ea8f0f80 + compatible = "spacemit,k1-pwm"; + reg = <0x0 0xd401a800 0x0 0x10>; + #pwm-cells = <1>; -+ clocks = <&ccu CLK_PWM2>; -+ resets = <&reset RESET_PWM2>; ++ clocks = <&syscon_apbc CLK_PWM2>; ++ resets = <&syscon_apbc RESET_PWM2>; + status = "disabled"; + }; + @@ -16893,8 +17105,8 @@ index 000000000000..1c89ea8f0f80 + compatible = "spacemit,k1-pwm"; + reg = <0x0 0xd401ac00 0x0 0x10>; + #pwm-cells = <1>; -+ clocks = <&ccu CLK_PWM3>; -+ resets = <&reset RESET_PWM3>; ++ clocks = <&syscon_apbc CLK_PWM3>; ++ resets = <&syscon_apbc RESET_PWM3>; + status = "disabled"; + }; + @@ -16902,8 +17114,8 @@ index 000000000000..1c89ea8f0f80 + compatible = "spacemit,k1-pwm"; + reg = <0x0 0xd401b000 0x0 0x10>; + #pwm-cells = <1>; -+ clocks = <&ccu CLK_PWM4>; -+ resets = <&reset RESET_PWM4>; ++ clocks = <&syscon_apbc CLK_PWM4>; ++ resets = <&syscon_apbc RESET_PWM4>; + status = "disabled"; + }; + @@ -16911,8 +17123,8 @@ index 000000000000..1c89ea8f0f80 + compatible = "spacemit,k1-pwm"; + reg = <0x0 0xd401b400 0x0 0x10>; + #pwm-cells = <1>; -+ clocks = <&ccu CLK_PWM5>; -+ resets = <&reset RESET_PWM5>; ++ clocks = <&syscon_apbc CLK_PWM5>; ++ resets = <&syscon_apbc RESET_PWM5>; + status = "disabled"; + }; + @@ -16920,8 +17132,8 @@ index 000000000000..1c89ea8f0f80 + compatible = "spacemit,k1-pwm"; + reg = <0x0 0xd401b800 0x0 0x10>; + #pwm-cells = <1>; -+ clocks = <&ccu CLK_PWM6>; -+ resets = <&reset RESET_PWM6>; ++ clocks = <&syscon_apbc CLK_PWM6>; ++ resets = <&syscon_apbc RESET_PWM6>; + status = "disabled"; + }; + @@ -16929,8 +17141,8 @@ index 000000000000..1c89ea8f0f80 + compatible = "spacemit,k1-pwm"; + reg = <0x0 0xd401bc00 0x0 0x10>; + #pwm-cells = <1>; -+ clocks = <&ccu CLK_PWM7>; -+ resets = <&reset RESET_PWM7>; ++ clocks = <&syscon_apbc CLK_PWM7>; ++ resets = <&syscon_apbc RESET_PWM7>; + status = "disabled"; + }; + @@ -16938,8 +17150,8 @@ index 000000000000..1c89ea8f0f80 + compatible = "spacemit,k1-pwm"; + reg = <0x0 0xd4020000 0x0 0x10>; + #pwm-cells = <1>; -+ clocks = <&ccu CLK_PWM8>; -+ resets = <&reset RESET_PWM8>; ++ clocks = <&syscon_apbc CLK_PWM8>; ++ resets = <&syscon_apbc RESET_PWM8>; + status = "disabled"; + }; + @@ -16947,8 +17159,8 @@ index 000000000000..1c89ea8f0f80 + compatible = "spacemit,k1-pwm"; + reg = <0x0 0xd4020400 0x0 0x10>; + #pwm-cells = <1>; -+ clocks = <&ccu CLK_PWM9>; -+ resets = <&reset RESET_PWM9>; ++ clocks = <&syscon_apbc CLK_PWM9>; ++ resets = <&syscon_apbc RESET_PWM9>; + status = "disabled"; + }; + @@ -16956,8 +17168,8 @@ index 000000000000..1c89ea8f0f80 + compatible = "spacemit,k1-pwm"; + reg = <0x0 0xd4020800 0x0 0x10>; + #pwm-cells = <1>; -+ clocks = <&ccu CLK_PWM10>; -+ resets = <&reset RESET_PWM10>; ++ clocks = <&syscon_apbc CLK_PWM10>; ++ resets = <&syscon_apbc RESET_PWM10>; + status = "disabled"; + }; + @@ -16965,8 +17177,8 @@ index 000000000000..1c89ea8f0f80 + compatible = "spacemit,k1-pwm"; + reg = <0x0 0xd4020c00 0x0 0x10>; + #pwm-cells = <1>; -+ clocks = <&ccu CLK_PWM11>; -+ resets = <&reset RESET_PWM11>; ++ clocks = <&syscon_apbc CLK_PWM11>; ++ resets = <&syscon_apbc RESET_PWM11>; + status = "disabled"; + }; + @@ -16974,8 +17186,8 @@ index 000000000000..1c89ea8f0f80 + compatible = "spacemit,k1-pwm"; + reg = <0x0 0xd4021000 0x0 0x10>; + #pwm-cells = <1>; -+ clocks = <&ccu CLK_PWM12>; -+ resets = <&reset RESET_PWM12>; ++ clocks = <&syscon_apbc CLK_PWM12>; ++ resets = <&syscon_apbc RESET_PWM12>; + status = "disabled"; + }; + @@ -16983,8 +17195,8 @@ index 000000000000..1c89ea8f0f80 + compatible = "spacemit,k1-pwm"; + reg = <0x0 0xd4021400 0x0 0x10>; + #pwm-cells = <1>; -+ clocks = <&ccu CLK_PWM13>; -+ resets = <&reset RESET_PWM13>; ++ clocks = <&syscon_apbc CLK_PWM13>; ++ resets = <&syscon_apbc RESET_PWM13>; + status = "disabled"; + }; + @@ -16992,8 +17204,8 @@ index 000000000000..1c89ea8f0f80 + compatible = "spacemit,k1-pwm"; + reg = <0x0 0xd4021800 0x0 0x10>; + #pwm-cells = <1>; -+ clocks = <&ccu CLK_PWM14>; -+ resets = <&reset RESET_PWM14>; ++ clocks = <&syscon_apbc CLK_PWM14>; ++ resets = <&syscon_apbc RESET_PWM14>; + status = "disabled"; + }; + @@ -17001,8 +17213,8 @@ index 000000000000..1c89ea8f0f80 + compatible = "spacemit,k1-pwm"; + reg = <0x0 0xd4021c00 0x0 0x10>; + #pwm-cells = <1>; -+ clocks = <&ccu CLK_PWM15>; -+ resets = <&reset RESET_PWM15>; ++ clocks = <&syscon_apbc CLK_PWM15>; ++ resets = <&syscon_apbc RESET_PWM15>; + status = "disabled"; + }; + @@ -17010,8 +17222,8 @@ index 000000000000..1c89ea8f0f80 + compatible = "spacemit,k1-pwm"; + reg = <0x0 0xd4022000 0x0 0x10>; + #pwm-cells = <1>; -+ clocks = <&ccu CLK_PWM16>; -+ resets = <&reset RESET_PWM16>; ++ clocks = <&syscon_apbc CLK_PWM16>; ++ resets = <&syscon_apbc RESET_PWM16>; + status = "disabled"; + }; + @@ -17019,8 +17231,8 @@ index 000000000000..1c89ea8f0f80 + compatible = "spacemit,k1-pwm"; + reg = <0x0 0xd4022400 0x0 0x10>; + #pwm-cells = <1>; -+ clocks = <&ccu CLK_PWM17>; -+ resets = <&reset RESET_PWM17>; ++ clocks = <&syscon_apbc CLK_PWM17>; ++ resets = <&syscon_apbc RESET_PWM17>; + status = "disabled"; + }; + @@ -17028,8 +17240,8 @@ index 000000000000..1c89ea8f0f80 + compatible = "spacemit,k1-pwm"; + reg = <0x0 0xd4022800 0x0 0x10>; + #pwm-cells = <1>; -+ clocks = <&ccu CLK_PWM18>; -+ resets = <&reset RESET_PWM18>; ++ clocks = <&syscon_apbc CLK_PWM18>; ++ resets = <&syscon_apbc RESET_PWM18>; + status = "disabled"; + }; + @@ -17037,8 +17249,8 @@ index 000000000000..1c89ea8f0f80 + compatible = "spacemit,k1-pwm"; + reg = <0x0 0xd4022c00 0x0 0x10>; + #pwm-cells = <1>; -+ clocks = <&ccu CLK_PWM19>; -+ resets = <&reset RESET_PWM19>; ++ clocks = <&syscon_apbc CLK_PWM19>; ++ resets = <&syscon_apbc RESET_PWM19>; + status = "disabled"; + }; + @@ -17048,7 +17260,9 @@ index 000000000000..1c89ea8f0f80 + gpio-controller; + #gpio-cells = <2>; + interrupts = <58>; -+ clocks = <&ccu CLK_GPIO>; ++ clocks = <&syscon_apbc CLK_GPIO>, ++ <&syscon_apbc CLK_GPIO_BUS>; ++ clock-names = "core", "bus"; + interrupt-names = "gpio_mux"; + interrupt-parent = <&intc>; + interrupt-controller; @@ -17076,13 +17290,13 @@ index 000000000000..1c89ea8f0f80 + reg = <0x0 0xd4280000 0x0 0x200>; + interrupts = <99>; + interrupt-parent = <&intc>; -+ resets = <&reset RESET_SDH_AXI>, -+ <&reset RESET_SDH0>; -+ reset-names = "sdh_axi", "sdh0"; -+ clocks = <&ccu CLK_SDH0>, -+ <&ccu CLK_SDH_AXI>, -+ <&ccu CLK_AIB>; -+ clock-names = "sdh-io", "sdh-core","aib-clk"; ++ clocks = <&syscon_apmu CLK_SDH_AXI>, ++ <&syscon_apmu CLK_SDH0>, ++ <&syscon_apmu CLK_AIB>; ++ clock-names = "core", "io", "aib"; ++ resets = <&syscon_apmu RESET_SDH_AXI>, ++ <&syscon_apmu RESET_SDH0>; ++ reset-names = "core", "io"; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; @@ -17093,12 +17307,12 @@ index 000000000000..1c89ea8f0f80 + reg = <0x0 0xd4280800 0x0 0x200>; + interrupts = <100>; + interrupt-parent = <&intc>; -+ resets = <&reset RESET_SDH_AXI>, -+ <&reset RESET_SDH1>; -+ reset-names = "sdh_axi", "sdh1"; -+ clocks = <&ccu CLK_SDH1>, -+ <&ccu CLK_SDH_AXI>; -+ clock-names = "sdh-io", "sdh-core"; ++ clocks = <&syscon_apmu CLK_SDH_AXI>, ++ <&syscon_apmu CLK_SDH1>; ++ clock-names = "core", "io"; ++ resets = <&syscon_apmu RESET_SDH_AXI>, ++ <&syscon_apmu RESET_SDH1>; ++ reset-names = "core", "io"; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; @@ -17109,12 +17323,12 @@ index 000000000000..1c89ea8f0f80 + reg = <0x0 0xd4281000 0x0 0x200>; + interrupts = <101>; + interrupt-parent = <&intc>; -+ resets = <&reset RESET_SDH_AXI>, -+ <&reset RESET_SDH2>; -+ reset-names = "sdh_axi", "sdh2"; -+ clocks = <&ccu CLK_SDH2>, -+ <&ccu CLK_SDH_AXI>; -+ clock-names = "sdh-io", "sdh-core"; ++ clocks = <&syscon_apmu CLK_SDH_AXI>, ++ <&syscon_apmu CLK_SDH2>; ++ clock-names = "core", "io"; ++ resets = <&syscon_apmu RESET_SDH_AXI>, ++ <&syscon_apmu RESET_SDH2>; ++ reset-names = "core", "io"; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; @@ -17126,9 +17340,10 @@ index 000000000000..1c89ea8f0f80 + k1,apmu-base-reg = <0xD4282800>; + ctrl-reg = <0x3e4>; + dline-reg = <0x3e8>; -+ clocks = <&ccu CLK_EMAC0_BUS>, <&ccu CLK_EMAC0_PTP>; ++ clocks = <&syscon_apmu CLK_EMAC0_BUS>, ++ <&syscon_apmu CLK_EMAC0_PTP>; + clock-names = "emac-clk", "ptp-clk"; -+ resets = <&reset RESET_EMAC0>; ++ resets = <&syscon_apmu RESET_EMAC0>; + reset-names = "emac-reset"; + interrupts-extended = <&intc 131>; + mac-address = [ 00 00 00 00 00 00 ]; @@ -17145,9 +17360,10 @@ index 000000000000..1c89ea8f0f80 + k1,apmu-base-reg = <0xD4282800>; + ctrl-reg = <0x3ec>; + dline-reg = <0x3f0>; -+ clocks = <&ccu CLK_EMAC1_BUS>, <&ccu CLK_EMAC1_PTP>; ++ clocks = <&syscon_apmu CLK_EMAC1_BUS>, ++ <&syscon_apmu CLK_EMAC1_PTP>; + clock-names = "emac-clk", "ptp-clk"; -+ resets = <&reset RESET_EMAC1>; ++ resets = <&syscon_apmu RESET_EMAC1>; + reset-names = "emac-reset"; + interrupts-extended = <&intc 133>; + mac-address = [ 00 00 00 00 00 00 ]; @@ -18357,6 +18573,641 @@ index 000000000000..42a6e499deee + }; +}; + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico.dts b/arch/riscv/boot/dts/spacemit/k3-pico.dts +new file mode 100644 +index 000000000000..50394133d013 +--- /dev/null ++++ b/arch/riscv/boot/dts/spacemit/k3-pico.dts +@@ -0,0 +1,22 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* Copyright (c) 2025 Spacemit, Inc */ ++ ++#include "k3.dtsi" ++ ++/ { ++ model = "Spacemit K3 Pico"; ++ ++ memory@102000000 { ++ device_type = "memory"; ++ reg = <0x1 0x02000000 0x0 0x7e000000>; ++ }; ++ ++ chosen { ++ bootargs = "earlycon=sbi console=ttyS0,115200n8 loglevel=8 rdinit=/init"; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +new file mode 100644 +index 000000000000..b4e38b7f89b3 +--- /dev/null ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -0,0 +1,601 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* Copyright (c) 2025 Spacemit, Inc */ ++ ++/dts-v1/; ++ ++#include ++#include ++ ++/ { ++ compatible = "spacemit,k3"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ cpus: cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ timebase-frequency = <24000000>; ++ ++ cpu_0: cpu@0 { ++ device_type = "cpu"; ++ reg = <0>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcvh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", ++ "smaia","smstateen","ssaia","sscofpmf", ++ "sstc","svinval","svnapot","svpbmt", ++ "svvptc","zawrs","zba","zbb","zbc","zbs", ++ "zcmop","zfa","zfh","zfhmin","zkt","zicbom", ++ "zicbop","zicboz","zicntr","zicond","zicsr", ++ "zifencei","zihintpause","zihintntl","zihpm", ++ "zimop","zvbb","zvbc","zvfh","zvfhmin","zvkb", ++ "zvkg","zvkn","zvknc","zvkned","zvkng","zvknha", ++ "zvknhb","zvks","zvksc","zvksed","zvksh","zvksg", ++ "zvkt","zcb"; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&clst0_l2_cache>; ++ mmu-type = "riscv,sv39"; ++ cpu0_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu_1: cpu@1 { ++ device_type = "cpu"; ++ reg = <1>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcvh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", ++ "smaia","smstateen","ssaia","sscofpmf", ++ "sstc","svinval","svnapot","svpbmt", ++ "svvptc","zawrs","zba","zbb","zbc","zbs", ++ "zcmop","zfa","zfh","zfhmin","zkt","zicbom", ++ "zicbop","zicboz","zicntr","zicond","zicsr", ++ "zifencei","zihintpause","zihintntl","zihpm", ++ "zimop","zvbb","zvbc","zvfh","zvfhmin","zvkb", ++ "zvkg","zvkn","zvknc","zvkned","zvkng","zvknha", ++ "zvknhb","zvks","zvksc","zvksed","zvksh","zvksg", ++ "zvkt","zcb"; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&clst0_l2_cache>; ++ mmu-type = "riscv,sv39"; ++ cpu1_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu_2: cpu@2 { ++ device_type = "cpu"; ++ reg = <2>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcvh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", ++ "smaia","smstateen","ssaia","sscofpmf", ++ "sstc","svinval","svnapot","svpbmt", ++ "svvptc","zawrs","zba","zbb","zbc","zbs", ++ "zcmop","zfa","zfh","zfhmin","zkt","zicbom", ++ "zicbop","zicboz","zicntr","zicond","zicsr", ++ "zifencei","zihintpause","zihintntl","zihpm", ++ "zimop","zvbb","zvbc","zvfh","zvfhmin","zvkb", ++ "zvkg","zvkn","zvknc","zvkned","zvkng","zvknha", ++ "zvknhb","zvks","zvksc","zvksed","zvksh","zvksg", ++ "zvkt","zcb"; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&clst0_l2_cache>; ++ mmu-type = "riscv,sv39"; ++ cpu2_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu_3: cpu@3 { ++ device_type = "cpu"; ++ reg = <3>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcvh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", ++ "smaia","smstateen","ssaia","sscofpmf", ++ "sstc","svinval","svnapot","svpbmt", ++ "svvptc","zawrs","zba","zbb","zbc","zbs", ++ "zcmop","zfa","zfh","zfhmin","zkt","zicbom", ++ "zicbop","zicboz","zicntr","zicond","zicsr", ++ "zifencei","zihintpause","zihintntl","zihpm", ++ "zimop","zvbb","zvbc","zvfh","zvfhmin","zvkb", ++ "zvkg","zvkn","zvknc","zvkned","zvkng","zvknha", ++ "zvknhb","zvks","zvksc","zvksed","zvksh","zvksg", ++ "zvkt","zcb"; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&clst0_l2_cache>; ++ mmu-type = "riscv,sv39"; ++ cpu3_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu_4: cpu@4 { ++ device_type = "cpu"; ++ reg = <4>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcvh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", ++ "smaia","smstateen","ssaia","sscofpmf", ++ "sstc","svinval","svnapot","svpbmt", ++ "svvptc","zawrs","zba","zbb","zbc","zbs", ++ "zcmop","zfa","zfh","zfhmin","zkt","zicbom", ++ "zicbop","zicboz","zicntr","zicond","zicsr", ++ "zifencei","zihintpause","zihintntl","zihpm", ++ "zimop","zvbb","zvbc","zvfh","zvfhmin","zvkb", ++ "zvkg","zvkn","zvknc","zvkned","zvkng","zvknha", ++ "zvknhb","zvks","zvksc","zvksed","zvksh","zvksg", ++ "zvkt","zcb"; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&clst1_l2_cache>; ++ mmu-type = "riscv,sv39"; ++ cpu4_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu_5: cpu@5 { ++ device_type = "cpu"; ++ reg = <5>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcvh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", ++ "smaia","smstateen","ssaia","sscofpmf", ++ "sstc","svinval","svnapot","svpbmt", ++ "svvptc","zawrs","zba","zbb","zbc","zbs", ++ "zcmop","zfa","zfh","zfhmin","zkt","zicbom", ++ "zicbop","zicboz","zicntr","zicond","zicsr", ++ "zifencei","zihintpause","zihintntl","zihpm", ++ "zimop","zvbb","zvbc","zvfh","zvfhmin","zvkb", ++ "zvkg","zvkn","zvknc","zvkned","zvkng","zvknha", ++ "zvknhb","zvks","zvksc","zvksed","zvksh","zvksg", ++ "zvkt","zcb"; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&clst1_l2_cache>; ++ mmu-type = "riscv,sv39"; ++ cpu5_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu_6: cpu@6 { ++ device_type = "cpu"; ++ reg = <6>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcvh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", ++ "smaia","smstateen","ssaia","sscofpmf", ++ "sstc","svinval","svnapot","svpbmt", ++ "svvptc","zawrs","zba","zbb","zbc","zbs", ++ "zcmop","zfa","zfh","zfhmin","zkt","zicbom", ++ "zicbop","zicboz","zicntr","zicond","zicsr", ++ "zifencei","zihintpause","zihintntl","zihpm", ++ "zimop","zvbb","zvbc","zvfh","zvfhmin","zvkb", ++ "zvkg","zvkn","zvknc","zvkned","zvkng","zvknha", ++ "zvknhb","zvks","zvksc","zvksed","zvksh","zvksg", ++ "zvkt","zcb"; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&clst1_l2_cache>; ++ mmu-type = "riscv,sv39"; ++ cpu6_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu_7: cpu@7 { ++ device_type = "cpu"; ++ reg = <7>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcvh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", ++ "smaia","smstateen","ssaia","sscofpmf", ++ "sstc","svinval","svnapot","svpbmt", ++ "svvptc","zawrs","zba","zbb","zbc","zbs", ++ "zcmop","zfa","zfh","zfhmin","zkt","zicbom", ++ "zicbop","zicboz","zicntr","zicond","zicsr", ++ "zifencei","zihintpause","zihintntl","zihpm", ++ "zimop","zvbb","zvbc","zvfh","zvfhmin","zvkb", ++ "zvkg","zvkn","zvknc","zvkned","zvkng","zvknha", ++ "zvknhb","zvks","zvksc","zvksed","zvksh","zvksg", ++ "zvkt","zcb"; ++ riscv,cbom-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&clst1_l2_cache>; ++ mmu-type = "riscv,sv39"; ++ cpu7_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu-map { ++ cluster0 { ++ core0 { ++ cpu = <&cpu_0>; ++ }; ++ ++ core1 { ++ cpu = <&cpu_1>; ++ }; ++ ++ core2 { ++ cpu = <&cpu_2>; ++ }; ++ ++ core3 { ++ cpu = <&cpu_3>; ++ }; ++ }; ++ cluster1 { ++ core0 { ++ cpu = <&cpu_4>; ++ }; ++ ++ core1 { ++ cpu = <&cpu_5>; ++ }; ++ ++ core2 { ++ cpu = <&cpu_6>; ++ }; ++ ++ core3 { ++ cpu = <&cpu_7>; ++ }; ++ }; ++ }; ++ ++ clst0_l2_cache: l2-cache0 { ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <4194304>; ++ cache-sets = <4096>; ++ cache-unified; ++ }; ++ ++ clst1_l2_cache: l2-cache1 { ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <4194304>; ++ cache-sets = <4096>; ++ cache-unified; ++ }; ++ }; ++ ++ clocks { ++ vctcxo_1m: clock-1m { ++ compatible = "fixed-clock"; ++ clock-frequency = <1000000>; ++ clock-output-names = "vctcxo_1m"; ++ #clock-cells = <0>; ++ }; ++ ++ vctcxo_24m: clock-24m { ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++ clock-output-names = "vctcxo_24m"; ++ #clock-cells = <0>; ++ }; ++ ++ vctcxo_3m: clock-3m { ++ compatible = "fixed-clock"; ++ clock-frequency = <3000000>; ++ clock-output-names = "vctcxo_3m"; ++ #clock-cells = <0>; ++ }; ++ ++ osc_32k: clock-32k { ++ compatible = "fixed-clock"; ++ clock-frequency = <32000>; ++ clock-output-names = "osc_32k"; ++ #clock-cells = <0>; ++ }; ++ ++ reserved_clk: clock-reserved { ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ clock-output-names = "reserved_clk"; ++ #clock-cells = <0>; ++ }; ++ ++ external_clk: clock-external { ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ clock-output-names = "external_clk"; ++ #clock-cells = <0>; ++ }; ++ }; ++ ++ soc: soc { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ compatible = "simple-bus"; ++ dma-noncoherent; ++ ranges; ++ ++ clint0: clint@e081c000 { ++ compatible = "riscv,clint0"; ++ interrupts-extended = < ++ &cpu0_intc 3 &cpu0_intc 7 ++ &cpu1_intc 3 &cpu1_intc 7 ++ &cpu2_intc 3 &cpu2_intc 7 ++ &cpu3_intc 3 &cpu3_intc 7 ++ &cpu4_intc 3 &cpu4_intc 7 ++ &cpu5_intc 3 &cpu5_intc 7 ++ &cpu6_intc 3 &cpu6_intc 7 ++ &cpu7_intc 3 &cpu7_intc 7>; ++ reg = <0x0 0xe081c000 0x0 0x0004000>; ++ }; ++ ++ simsic: interrupt-controller@e0400000 { ++ compatible = "riscv,imsics"; ++ interrupts-extended = < ++ &cpu0_intc 9 &cpu1_intc 9 ++ &cpu2_intc 9 &cpu3_intc 9 ++ &cpu4_intc 9 &cpu5_intc 9 ++ &cpu6_intc 9 &cpu7_intc 9>; ++ ++ reg = <0x0 0xe0400000 0x0 0x40000 ++ 0x0 0xe0440000 0x0 0x40000 ++ 0x0 0xe0480000 0x0 0x40000 ++ 0x0 0xe04c0000 0x0 0x40000 ++ 0x0 0xe0500000 0x0 0x40000 ++ 0x0 0xe0540000 0x0 0x40000 ++ 0x0 0xe0580000 0x0 0x40000 ++ 0x0 0xe05c0000 0x0 0x40000>; ++ interrupt-controller; ++ #interrupt-cells = <0>; ++ #msi-cells = <0>; ++ msi-controller; ++ /* Number of interrupt identities: 511 */ ++ riscv,num-ids = <511>; ++ /* Number of guest interrupt identities: 511 */ ++ riscv,num-guest-ids = <511>; ++ /* Number of HART index bits: 4 (2^4 = 16 harts) */ ++ riscv,hart-index-bits = <4>; ++ riscv,guest-index-bits = <6>; ++ status = "okay"; ++ }; ++ ++ saplic: interrupt-controller@e0804000 { ++ compatible = "riscv,aplic"; ++ /* aplic config */ ++ reg = <0x0 0xe0804000 0x0 0x4000>; ++ msi-parent = <&simsic>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ /* the number of wired interrupt sources:512 */ ++ riscv,num-sources = <512>; ++ status = "okay"; ++ }; ++ ++ syscon_mpmu: system-controller@d4050000 { ++ compatible = "spacemit,k3-syscon-mpmu", "syscon"; ++ reg = <0x0 0xd4050000 0x0 0x10000>; ++ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, ++ <&vctcxo_24m>, <&reserved_clk>, <&external_clk>; ++ clock-names = "osc_32k", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m", ++ "reserved_clk", "external_clk"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ pll: clock-controller@d4090000 { ++ compatible = "spacemit,k3-pll"; ++ reg = <0x0 0xd4090000 0x0 0x10000>; ++ clocks = <&vctcxo_24m>; ++ spacemit,mpmu = <&syscon_mpmu>; ++ #clock-cells = <1>; ++ }; ++ ++ syscon_apmu: system-controller@d4282800 { ++ compatible = "spacemit,k3-syscon-apmu", "syscon"; ++ reg = <0x0 0xd4282800 0x0 0x400>; ++ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>, ++ <&reserved_clk>, <&external_clk>; ++ clock-names = "osc_32k", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m", ++ "reserved_clk", "external_clk"; ++ #clock-cells = <1>; ++ #power-domain-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ syscon_apbc: system-controller@d4015000 { ++ compatible = "spacemit,k3-syscon-apbc"; ++ reg = <0x0 0xd4015000 0x0 0x1000>; ++ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>, ++ <&reserved_clk>, <&external_clk>; ++ clock-names = "osc_32k", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m", ++ "reserved_clk", "external_clk"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ syscon_apbc2: system-controller@f0610000 { ++ compatible = "spacemit,k3-syscon-apbc2"; ++ reg = <0x0 0xf0610000 0x0 0x2000>; ++ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>, ++ <&reserved_clk>, <&external_clk>; ++ clock-names = "osc_32k", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m", ++ "reserved_clk", "external_clk"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ syscon_dciu: system-controller@d8440000 { ++ compatible = "spacemit,k3-syscon-dciu"; ++ reg = <0x0 0xd8440000 0x0 0xc000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ syscon_rcpu_sysctrl: system-controller@c0880000 { ++ compatible = "spacemit,k3-syscon-rcpu-sysctrl", "syscon"; ++ reg = <0x0 0xc0880000 0x0 0x1000>; ++ clocks = <&vctcxo_24m>, <&external_clk>; ++ clock-names = "vctcxo_24m", "external_clk"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ syscon_rcpu_uartctrl: system-controller@c0881f00 { ++ compatible = "spacemit,k3-syscon-rcpu-uartctrl"; ++ reg = <0x0 0xc0881f00 0x0 0x100>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ syscon_rcpu_i2sctrl: system-controller@c0882000 { ++ compatible = "spacemit,k3-syscon-rcpu-i2sctrl"; ++ reg = <0x0 0xc0882000 0x0 0x1000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ syscon_rcpu_spictrl: system-controller@c0885f00 { ++ compatible = "spacemit,k3-syscon-rcpu-spictrl"; ++ reg = <0x0 0xc0885f00 0x0 0x100>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ syscon_rcpu_i2cctrl: system-controller@c0886f00 { ++ compatible = "spacemit,k3-syscon-rcpu-i2cctrl"; ++ reg = <0x0 0xc0886f00 0x0 0x100>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ syscon_rpmu: system-controller@c088c000 { ++ compatible = "spacemit,k3-syscon-rpmu", "syscon"; ++ reg = <0x0 0xc088c000 0x0 0x800>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ syscon_rcpu_pwmctrl: system-controller@c088d000 { ++ compatible = "spacemit,k3-syscon-rcpu-pwmctrl"; ++ reg = <0x0 0xc088d000 0x0 0x100>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ uart0: serial@d4017000 { ++ compatible = "spacemit,k1-uart", ++ "intel,xscale-uart"; ++ reg = <0x0 0xd4017000 0x0 0x100>; ++ clocks = <&syscon_apbc CLK_APBC_UART0>, ++ <&syscon_apbc CLK_APBC_UART0_BUS>, ++ <&syscon_mpmu CLK_MPMU_SLOW_UART>; ++ clock-names = "core", "bus", "gate"; ++ resets = <&syscon_apbc RESET_APBC_UART0>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ interrupt-parent = <&saplic>; ++ interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; ++ status = "okay"; ++ }; ++ }; ++}; diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile index b55a17127c2b..3e6311bc9976 100644 --- a/arch/riscv/boot/dts/thead/Makefile @@ -24195,10 +25046,10 @@ index 000000000000..93b99d622a78 + }; +}; diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig -index ab86ec3b9eab..2bf8ed8dae61 100644 +index ab86ec3b9eab..ed510e0ff874 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig -@@ -28,17 +28,24 @@ CONFIG_PROFILING=y +@@ -28,21 +28,30 @@ CONFIG_PROFILING=y CONFIG_SOC_MICROCHIP_POLARFIRE=y CONFIG_ARCH_RENESAS=y CONFIG_ARCH_THEAD=y @@ -24209,6 +25060,7 @@ index ab86ec3b9eab..2bf8ed8dae61 100644 CONFIG_SOC_VIRT=y +CONFIG_SOC_SPACEMIT=y +CONFIG_SOC_SPACEMIT_K1=y ++CONFIG_SOC_SPACEMIT_K3=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y CONFIG_PM=y @@ -24223,7 +25075,12 @@ index ab86ec3b9eab..2bf8ed8dae61 100644 CONFIG_JUMP_LABEL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -@@ -123,6 +130,7 @@ CONFIG_VIRTIO_NET=y + CONFIG_SPARSEMEM_MANUAL=y ++CONFIG_MODVERSIONS=y + CONFIG_BLK_DEV_THROTTLING=y + CONFIG_NET=y + CONFIG_PACKET=y +@@ -123,6 +132,7 @@ CONFIG_VIRTIO_NET=y CONFIG_MACB=y CONFIG_E1000E=y CONFIG_R8169=y @@ -24231,7 +25088,7 @@ index ab86ec3b9eab..2bf8ed8dae61 100644 CONFIG_STMMAC_ETH=m CONFIG_MICROSEMI_PHY=y CONFIG_INPUT_MOUSEDEV=y -@@ -133,15 +141,27 @@ CONFIG_SERIAL_8250_DW=y +@@ -133,15 +143,27 @@ CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_SH_SCI=y CONFIG_VIRTIO_CONSOLE=y @@ -24259,7 +25116,7 @@ index ab86ec3b9eab..2bf8ed8dae61 100644 CONFIG_SUNXI_WATCHDOG=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y -@@ -168,22 +188,30 @@ CONFIG_MMC=y +@@ -168,21 +190,30 @@ CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_CADENCE=y @@ -24278,7 +25135,9 @@ index ab86ec3b9eab..2bf8ed8dae61 100644 CONFIG_VIRTIO_INPUT=y CONFIG_VIRTIO_MMIO=y CONFIG_SUN8I_DE2_CCU=m ++CONFIG_SPACEMIT_CCU=y +CONFIG_SPACEMIT_K1_CCU=y ++CONFIG_SPACEMIT_K3_CCU=y CONFIG_SUN50I_IOMMU=y +CONFIG_MAILBOX=y CONFIG_RPMSG_CHAR=y @@ -24286,11 +25145,9 @@ index ab86ec3b9eab..2bf8ed8dae61 100644 CONFIG_RPMSG_VIRTIO=y +CONFIG_RPMSG_TH1520=y CONFIG_ARCH_R9A07G043=y -+CONFIG_RESET_K1_SPACEMIT=y CONFIG_PHY_SUN4I_USB=m CONFIG_LIBNVDIMM=y - CONFIG_NVMEM_SUNXI_SID=y -@@ -238,5 +266,13 @@ CONFIG_DEBUG_SG=y +@@ -238,5 +269,13 @@ CONFIG_DEBUG_SG=y # CONFIG_RCU_TRACE is not set CONFIG_RCU_EQS_DEBUG=y # CONFIG_FTRACE is not set @@ -29874,8 +30731,24 @@ index 000000000000..a027c9272a4b +CONFIG_NET_VENDOR_SPACEMIT=y +CONFIG_K1_EMAC=m + +diff --git a/arch/riscv/configs/k3_defconfig b/arch/riscv/configs/k3_defconfig +new file mode 100644 +index 000000000000..fe5517ca6acb +--- /dev/null ++++ b/arch/riscv/configs/k3_defconfig +@@ -0,0 +1,10 @@ ++# ++# Spacemit k3 SoC support ++# ++CONFIG_SOC_SPACEMIT=y ++CONFIG_SOC_SPACEMIT_K3=y ++CONFIG_RISCV_ISA_ZICBOM=y ++CONFIG_SPACEMIT_CCU=y ++CONFIG_SPACEMIT_K3_CCU=y ++CONFIG_RESET_SPACEMIT=y ++CONFIG_RESET_SPACEMIT_K3=y diff --git a/arch/riscv/configs/openeuler_defconfig b/arch/riscv/configs/openeuler_defconfig -index 61f2b2f12589..0f2b22d817e1 100644 +index 61f2b2f12589..1a9a39da77d2 100644 --- a/arch/riscv/configs/openeuler_defconfig +++ b/arch/riscv/configs/openeuler_defconfig @@ -44,6 +44,8 @@ CONFIG_IRQ_DOMAIN_HIERARCHY=y @@ -29973,7 +30846,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_PGTABLE_LEVELS=5 CONFIG_LOCKDEP_SUPPORT=y CONFIG_RISCV_DMA_NONCOHERENT=y -@@ -306,15 +314,20 @@ CONFIG_RISCV_DMA_NONCOHERENT=y +@@ -306,15 +314,21 @@ CONFIG_RISCV_DMA_NONCOHERENT=y # SoC selection # # CONFIG_SOC_MICROCHIP_POLARFIRE is not set @@ -29993,10 +30866,11 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_SOC_VIRT=y +CONFIG_SOC_SPACEMIT=y +CONFIG_SOC_SPACEMIT_K1=y ++CONFIG_SOC_SPACEMIT_K3=y # end of SoC selection # -@@ -330,6 +343,18 @@ CONFIG_ERRATA_THEAD_CMO=y +@@ -330,6 +344,18 @@ CONFIG_ERRATA_THEAD_CMO=y CONFIG_ERRATA_THEAD_PMU=y # end of CPU errata selection @@ -30015,7 +30889,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # # Platform type # -@@ -339,12 +364,14 @@ CONFIG_ARCH_RV64I=y +@@ -339,12 +365,14 @@ CONFIG_ARCH_RV64I=y CONFIG_CMODEL_MEDANY=y CONFIG_MODULE_SECTIONS=y CONFIG_SMP=y @@ -30031,7 +30905,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_RISCV_ALTERNATIVE=y CONFIG_RISCV_ALTERNATIVE_EARLY=y CONFIG_RISCV_ISA_C=y -@@ -353,9 +380,16 @@ CONFIG_RISCV_ISA_SVPBMT=y +@@ -353,9 +381,16 @@ CONFIG_RISCV_ISA_SVPBMT=y CONFIG_TOOLCHAIN_HAS_V=y CONFIG_RISCV_ISA_V=y CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y @@ -30049,7 +30923,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y CONFIG_FPU=y CONFIG_IRQ_STACKS=y -@@ -380,6 +414,8 @@ CONFIG_ARCH_SELECTS_KEXEC_FILE=y +@@ -380,6 +415,8 @@ CONFIG_ARCH_SELECTS_KEXEC_FILE=y CONFIG_ARCH_SUPPORTS_KEXEC_PURGATORY=y CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y CONFIG_COMPAT=y @@ -30058,7 +30932,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_RELOCATABLE is not set # CONFIG_RANDOMIZE_BASE is not set # end of Kernel features -@@ -390,6 +426,7 @@ CONFIG_COMPAT=y +@@ -390,6 +427,7 @@ CONFIG_COMPAT=y CONFIG_CMDLINE="" CONFIG_EFI_STUB=y CONFIG_EFI=y @@ -30066,7 +30940,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y CONFIG_STACKPROTECTOR_PER_TASK=y CONFIG_RISCV_ISA_FALLBACK=y -@@ -420,7 +457,7 @@ CONFIG_PM_GENERIC_DOMAINS=y +@@ -420,7 +458,7 @@ CONFIG_PM_GENERIC_DOMAINS=y CONFIG_PM_GENERIC_DOMAINS_SLEEP=y CONFIG_PM_GENERIC_DOMAINS_OF=y CONFIG_CPU_PM=y @@ -30075,7 +30949,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_ARCH_SUSPEND_POSSIBLE=y # end of Power management options -@@ -436,6 +473,7 @@ CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +@@ -436,6 +474,7 @@ CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y # CONFIG_CPU_IDLE_GOV_LADDER is not set CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_IDLE_GOV_TEO=y @@ -30083,7 +30957,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_DT_IDLE_STATES=y CONFIG_DT_IDLE_GENPD=y -@@ -471,6 +509,9 @@ CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +@@ -471,6 +510,9 @@ CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y # CONFIG_CPUFREQ_DT=y CONFIG_CPUFREQ_DT_PLATDEV=y @@ -30093,7 +30967,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # end of CPU Frequency scaling # end of CPU Power Management -@@ -480,14 +521,65 @@ CONFIG_HAVE_KVM_IRQ_ROUTING=y +@@ -480,14 +522,65 @@ CONFIG_HAVE_KVM_IRQ_ROUTING=y CONFIG_HAVE_KVM_EVENTFD=y CONFIG_KVM_MMIO=y CONFIG_HAVE_KVM_MSI=y @@ -30160,7 +31034,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # # General architecture-dependent options -@@ -524,7 +616,12 @@ CONFIG_HAVE_PERF_REGS=y +@@ -524,7 +617,12 @@ CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y @@ -30173,7 +31047,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_SECCOMP=y -@@ -565,7 +662,7 @@ CONFIG_VMAP_STACK=y +@@ -565,7 +663,7 @@ CONFIG_VMAP_STACK=y CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y @@ -30182,7 +31056,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y CONFIG_ARCH_USE_MEMREMAP_PROT=y -@@ -585,7 +682,14 @@ CONFIG_DYNAMIC_SIGFRAME=y +@@ -585,7 +683,14 @@ CONFIG_DYNAMIC_SIGFRAME=y CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y # end of GCOV-based kernel profiling @@ -30197,7 +31071,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_FUNCTION_ALIGNMENT=0 # end of General architecture-dependent options -@@ -638,6 +742,7 @@ CONFIG_BLK_WBT_MQ=y +@@ -638,6 +743,7 @@ CONFIG_BLK_WBT_MQ=y # CONFIG_BLK_CGROUP_IOLATENCY is not set # CONFIG_BLK_CGROUP_FC_APPID is not set # CONFIG_BLK_CGROUP_IOCOST is not set @@ -30205,7 +31079,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_BLK_CGROUP_IOPRIO is not set CONFIG_BLK_DEBUG_FS=y CONFIG_BLK_DEBUG_FS_ZONED=y -@@ -646,6 +751,7 @@ CONFIG_BLK_INLINE_ENCRYPTION=y +@@ -646,6 +752,7 @@ CONFIG_BLK_INLINE_ENCRYPTION=y CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y # CONFIG_BLK_DEV_DETECT_WRITING_PART0 is not set # CONFIG_BLK_DEV_WRITE_MOUNTED_DUMP is not set @@ -30213,7 +31087,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_BLK_IO_HIERARCHY_STATS is not set # -@@ -701,11 +807,15 @@ CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +@@ -701,11 +808,15 @@ CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_RWSEM_SPIN_ON_OWNER=y CONFIG_LOCK_SPIN_ON_OWNER=y @@ -30229,7 +31103,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y # CONFIG_PID_MAX_PER_NAMESPACE is not set CONFIG_FREEZER=y -@@ -771,6 +881,8 @@ CONFIG_SPARSEMEM_EXTREME=y +@@ -771,6 +882,8 @@ CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSEMEM_VMEMMAP=y CONFIG_ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP=y @@ -30238,7 +31112,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_MEMORY_ISOLATION=y CONFIG_EXCLUSIVE_SYSTEM_RAM=y CONFIG_SPLIT_PTLOCK_CPUS=4 -@@ -795,13 +907,14 @@ CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y +@@ -795,13 +908,14 @@ CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set CONFIG_THP_SWAP=y # CONFIG_READ_ONLY_THP_FOR_FS is not set @@ -30256,7 +31130,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set CONFIG_PAGE_IDLE_FLAG=y -@@ -833,6 +946,8 @@ CONFIG_LOCK_MM_AND_FIND_VMA=y +@@ -833,6 +947,8 @@ CONFIG_LOCK_MM_AND_FIND_VMA=y # # CONFIG_DAMON is not set # end of Data Access Monitoring @@ -30265,7 +31139,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # end of Memory Management options CONFIG_NET=y -@@ -870,6 +985,8 @@ CONFIG_NET_KEY=m +@@ -870,6 +986,8 @@ CONFIG_NET_KEY=m CONFIG_NET_KEY_MIGRATE=y # CONFIG_SMC is not set # CONFIG_XDP_SOCKETS is not set @@ -30274,7 +31148,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_NET_HANDSHAKE=y CONFIG_INET=y CONFIG_IP_MULTICAST=y -@@ -1346,10 +1463,10 @@ CONFIG_L2TP_DEBUGFS=m +@@ -1346,10 +1464,10 @@ CONFIG_L2TP_DEBUGFS=m CONFIG_L2TP_V3=y CONFIG_L2TP_IP=m CONFIG_L2TP_ETH=m @@ -30287,7 +31161,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_BRIDGE_IGMP_SNOOPING=y CONFIG_BRIDGE_VLAN_FILTERING=y # CONFIG_BRIDGE_MRP is not set -@@ -1358,7 +1475,7 @@ CONFIG_BRIDGE_VLAN_FILTERING=y +@@ -1358,7 +1476,7 @@ CONFIG_BRIDGE_VLAN_FILTERING=y CONFIG_VLAN_8021Q=m CONFIG_VLAN_8021Q_GVRP=y CONFIG_VLAN_8021Q_MVRP=y @@ -30296,7 +31170,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_LLC2 is not set # CONFIG_ATALK is not set # CONFIG_X25 is not set -@@ -1496,6 +1613,7 @@ CONFIG_CGROUP_NET_CLASSID=y +@@ -1496,6 +1614,7 @@ CONFIG_CGROUP_NET_CLASSID=y CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y # CONFIG_BPF_STREAM_PARSER is not set @@ -30304,7 +31178,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_NET_FLOW_LIMIT=y # -@@ -1513,7 +1631,54 @@ CONFIG_CAN_BCM=m +@@ -1513,7 +1632,54 @@ CONFIG_CAN_BCM=m CONFIG_CAN_GW=m # CONFIG_CAN_J1939 is not set # CONFIG_CAN_ISOTP is not set @@ -30360,7 +31234,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_AF_RXRPC is not set # CONFIG_AF_KCM is not set CONFIG_STREAM_PARSER=y -@@ -1522,7 +1687,7 @@ CONFIG_FIB_RULES=y +@@ -1522,7 +1688,7 @@ CONFIG_FIB_RULES=y CONFIG_WIRELESS=y CONFIG_WEXT_CORE=y CONFIG_WEXT_PROC=y @@ -30369,7 +31243,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_NL80211_TESTMODE is not set # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set # CONFIG_CFG80211_CERTIFICATION_ONUS is not set -@@ -1532,7 +1697,7 @@ CONFIG_CFG80211_DEFAULT_PS=y +@@ -1532,7 +1698,7 @@ CONFIG_CFG80211_DEFAULT_PS=y # CONFIG_CFG80211_DEBUGFS is not set CONFIG_CFG80211_CRDA_SUPPORT=y CONFIG_CFG80211_WEXT=y @@ -30378,7 +31252,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_MAC80211_HAS_RC=y CONFIG_MAC80211_RC_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y -@@ -1543,7 +1708,7 @@ CONFIG_MAC80211_DEBUGFS=y +@@ -1543,7 +1709,7 @@ CONFIG_MAC80211_DEBUGFS=y # CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 @@ -30387,7 +31261,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y CONFIG_RFKILL_GPIO=m -@@ -1573,6 +1738,7 @@ CONFIG_FAILOVER=y +@@ -1573,6 +1739,7 @@ CONFIG_FAILOVER=y CONFIG_ETHTOOL_NETLINK=y CONFIG_NETACC_BPF=y CONFIG_NETACC_TERRACE=y @@ -30395,7 +31269,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # # Device Drivers -@@ -1595,6 +1761,7 @@ CONFIG_PCIEASPM_DEFAULT=y +@@ -1595,6 +1762,7 @@ CONFIG_PCIEASPM_DEFAULT=y CONFIG_PCIE_PME=y CONFIG_PCIE_DPC=y # CONFIG_PCIE_PTM is not set @@ -30403,7 +31277,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_PCI_MSI=y CONFIG_PCI_QUIRKS=y # CONFIG_PCI_DEBUG is not set -@@ -1606,6 +1773,7 @@ CONFIG_PCI_ECAM=y +@@ -1606,6 +1774,7 @@ CONFIG_PCI_ECAM=y CONFIG_PCI_IOV=y CONFIG_PCI_PRI=y CONFIG_PCI_PASID=y @@ -30411,7 +31285,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_PCI_DYNAMIC_OF_NODES is not set # CONFIG_PCIE_BUS_TUNE_OFF is not set CONFIG_PCIE_BUS_DEFAULT=y -@@ -1615,6 +1783,7 @@ CONFIG_PCIE_BUS_DEFAULT=y +@@ -1615,6 +1784,7 @@ CONFIG_PCIE_BUS_DEFAULT=y CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=64 CONFIG_HOTPLUG_PCI=y @@ -30419,7 +31293,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_HOTPLUG_PCI_CPCI is not set CONFIG_HOTPLUG_PCI_SHPC=y -@@ -1625,6 +1794,8 @@ CONFIG_HOTPLUG_PCI_SHPC=y +@@ -1625,6 +1795,8 @@ CONFIG_HOTPLUG_PCI_SHPC=y CONFIG_PCI_HOST_COMMON=y CONFIG_PCI_HOST_GENERIC=y CONFIG_PCIE_MICROCHIP_HOST=y @@ -30428,7 +31302,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_PCIE_XILINX=y # -@@ -1636,6 +1807,7 @@ CONFIG_PCIE_CADENCE_EP=y +@@ -1636,6 +1808,7 @@ CONFIG_PCIE_CADENCE_EP=y CONFIG_PCIE_CADENCE_PLAT=y CONFIG_PCIE_CADENCE_PLAT_HOST=y CONFIG_PCIE_CADENCE_PLAT_EP=y @@ -30436,7 +31310,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_PCI_J721E=y CONFIG_PCI_J721E_HOST=y # CONFIG_PCI_J721E_EP is not set -@@ -1647,11 +1819,13 @@ CONFIG_PCI_J721E_HOST=y +@@ -1647,11 +1820,13 @@ CONFIG_PCI_J721E_HOST=y CONFIG_PCIE_DW=y CONFIG_PCIE_DW_HOST=y CONFIG_PCIE_DW_EP=y @@ -30450,7 +31324,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # end of DesignWare-based PCIe controllers # -@@ -1697,7 +1871,9 @@ CONFIG_FW_LOADER=y +@@ -1697,7 +1872,9 @@ CONFIG_FW_LOADER=y CONFIG_FW_LOADER_DEBUG=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_FW_LOADER_USER_HELPER is not set @@ -30461,7 +31335,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_FW_CACHE=y # CONFIG_FW_UPLOAD is not set # end of Firmware loader -@@ -1709,10 +1885,12 @@ CONFIG_WANT_DEV_COREDUMP=y +@@ -1709,10 +1886,12 @@ CONFIG_WANT_DEV_COREDUMP=y # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set CONFIG_GENERIC_CPU_DEVICES=y @@ -30476,7 +31350,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_DMA_SHARED_BUFFER=y # CONFIG_DMA_FENCE_TRACE is not set CONFIG_GENERIC_ARCH_TOPOLOGY=y -@@ -1724,6 +1902,8 @@ CONFIG_GENERIC_ARCH_NUMA=y +@@ -1724,6 +1903,8 @@ CONFIG_GENERIC_ARCH_NUMA=y # Bus devices # # CONFIG_MOXTET is not set @@ -30485,7 +31359,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_MHI_BUS is not set # CONFIG_MHI_BUS_EP is not set # end of Bus devices -@@ -1747,6 +1927,10 @@ CONFIG_PROC_EVENTS=y +@@ -1747,6 +1928,10 @@ CONFIG_PROC_EVENTS=y # end of ARM System Control and Management Interface Protocol # CONFIG_FIRMWARE_MEMMAP is not set @@ -30496,7 +31370,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_SYSFB=y CONFIG_SYSFB_SIMPLEFB=y # CONFIG_GOOGLE_FIRMWARE is not set -@@ -1767,19 +1951,30 @@ CONFIG_EFI_GENERIC_STUB=y +@@ -1767,19 +1952,30 @@ CONFIG_EFI_GENERIC_STUB=y # CONFIG_RESET_ATTACK_MITIGATION is not set # CONFIG_EFI_DISABLE_PCI_DMA is not set CONFIG_EFI_EARLYCON=y @@ -30529,7 +31403,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # # Partition parsers -@@ -1793,9 +1988,8 @@ CONFIG_MTD_OF_PARTS=m +@@ -1793,9 +1989,8 @@ CONFIG_MTD_OF_PARTS=m # # User Modules And Translation Layers # @@ -30541,7 +31415,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # # Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. -@@ -1862,8 +2056,8 @@ CONFIG_MTD_PHYSMAP_OF=y +@@ -1862,8 +2057,8 @@ CONFIG_MTD_PHYSMAP_OF=y # CONFIG_MTD_MCHP23K256 is not set # CONFIG_MTD_MCHP48L640 is not set # CONFIG_MTD_SST25L is not set @@ -30552,7 +31426,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_MTD_MTDRAM is not set CONFIG_MTD_BLOCK2MTD=m -@@ -1876,13 +2070,15 @@ CONFIG_MTD_BLOCK2MTD=m +@@ -1876,13 +2071,15 @@ CONFIG_MTD_BLOCK2MTD=m # # NAND # @@ -30569,7 +31443,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_MTD_NAND_ECC_SW_HAMMING is not set # CONFIG_MTD_NAND_ECC_SW_BCH is not set # CONFIG_MTD_NAND_ECC_MXIC is not set -@@ -1895,12 +2091,13 @@ CONFIG_MTD_BLOCK2MTD=m +@@ -1895,12 +2092,13 @@ CONFIG_MTD_BLOCK2MTD=m # CONFIG_MTD_LPDDR is not set # end of LPDDR & LPDDR2 PCM memory drivers @@ -30585,7 +31459,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MTD_UBI_BEB_LIMIT=20 # CONFIG_MTD_UBI_FASTMAP is not set -@@ -1921,6 +2118,13 @@ CONFIG_OF_RESOLVE=y +@@ -1921,6 +2119,13 @@ CONFIG_OF_RESOLVE=y CONFIG_OF_OVERLAY=y CONFIG_OF_NUMA=y # CONFIG_PARPORT is not set @@ -30599,7 +31473,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_BLK_DEV=y CONFIG_BLK_DEV_NULL_BLK=m CONFIG_CDROM=y -@@ -1939,7 +2143,7 @@ CONFIG_BLK_DEV_LOOP=y +@@ -1939,7 +2144,7 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 CONFIG_BLK_DEV_DRBD=m # CONFIG_DRBD_FAULT_INJECTION is not set @@ -30608,7 +31482,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=16384 -@@ -2008,7 +2212,7 @@ CONFIG_MISC_RTSX=m +@@ -2008,7 +2213,7 @@ CONFIG_MISC_RTSX=m # # EEPROM support # @@ -30617,7 +31491,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_EEPROM_AT25 is not set CONFIG_EEPROM_LEGACY=m CONFIG_EEPROM_MAX6875=m -@@ -2028,7 +2232,6 @@ CONFIG_CB710_DEBUG_ASSUMPTIONS=y +@@ -2028,7 +2233,6 @@ CONFIG_CB710_DEBUG_ASSUMPTIONS=y # CONFIG_TI_ST is not set # end of Texas Instruments shared transport line discipline @@ -30625,7 +31499,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_SENSORS_LIS3_I2C=m CONFIG_ALTERA_STAPL=m # CONFIG_GENWQE is not set -@@ -2109,7 +2312,9 @@ CONFIG_SCSI_MPT3SAS=m +@@ -2109,7 +2313,9 @@ CONFIG_SCSI_MPT3SAS=m CONFIG_SCSI_MPT2SAS_MAX_SGE=128 CONFIG_SCSI_MPT3SAS_MAX_SGE=128 CONFIG_SCSI_MPT2SAS=m @@ -30635,7 +31509,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_SCSI_SMARTPQI=m # CONFIG_SCSI_HPTIOP is not set # CONFIG_SCSI_BUSLOGIC is not set -@@ -2156,8 +2361,11 @@ CONFIG_SCSI_DH_ALUA=y +@@ -2156,8 +2362,11 @@ CONFIG_SCSI_DH_ALUA=y CONFIG_ATA=y CONFIG_SATA_HOST=y @@ -30647,7 +31521,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_SATA_PMP=y # -@@ -2168,6 +2376,7 @@ CONFIG_SATA_MOBILE_LPM_POLICY=0 +@@ -2168,6 +2377,7 @@ CONFIG_SATA_MOBILE_LPM_POLICY=0 CONFIG_SATA_AHCI_PLATFORM=y # CONFIG_AHCI_DWC is not set # CONFIG_AHCI_CEVA is not set @@ -30655,7 +31529,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_SATA_INIC162X is not set # CONFIG_SATA_ACARD_AHCI is not set # CONFIG_SATA_SIL24 is not set -@@ -2189,6 +2398,7 @@ CONFIG_ATA_PIIX=m +@@ -2189,6 +2399,7 @@ CONFIG_ATA_PIIX=m # CONFIG_SATA_MV is not set # CONFIG_SATA_NV is not set # CONFIG_SATA_PROMISE is not set @@ -30663,7 +31537,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_SATA_SIL is not set # CONFIG_SATA_SIS is not set # CONFIG_SATA_SVW is not set -@@ -2247,6 +2457,7 @@ CONFIG_ATA_PIIX=m +@@ -2247,6 +2458,7 @@ CONFIG_ATA_PIIX=m # # Generic fallback / legacy drivers # @@ -30671,7 +31545,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_ATA_GENERIC=m # CONFIG_PATA_LEGACY is not set CONFIG_MD=y -@@ -2265,14 +2476,14 @@ CONFIG_BCACHE=m +@@ -2265,14 +2477,14 @@ CONFIG_BCACHE=m # CONFIG_BCACHE_CLOSURES_DEBUG is not set # CONFIG_BCACHE_ASYNC_REGISTRATION is not set CONFIG_BLK_DEV_DM_BUILTIN=y @@ -30688,7 +31562,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_DM_SNAPSHOT=m CONFIG_DM_THIN_PROVISIONING=m CONFIG_DM_CACHE=m -@@ -2292,6 +2503,7 @@ CONFIG_DM_MULTIPATH_ST=m +@@ -2292,6 +2504,7 @@ CONFIG_DM_MULTIPATH_ST=m # CONFIG_DM_MULTIPATH_IOA is not set CONFIG_DM_DELAY=m # CONFIG_DM_DUST is not set @@ -30696,7 +31570,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_DM_UEVENT=y CONFIG_DM_FLAKEY=m CONFIG_DM_VERITY=m -@@ -2322,7 +2534,7 @@ CONFIG_ISCSI_TARGET_CXGB4=m +@@ -2322,7 +2535,7 @@ CONFIG_ISCSI_TARGET_CXGB4=m # end of IEEE 1394 (FireWire) support CONFIG_NETDEVICES=y @@ -30705,7 +31579,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_NET_CORE=y CONFIG_BONDING=m CONFIG_DUMMY=m -@@ -2366,10 +2578,13 @@ CONFIG_VSOCKMON=m +@@ -2366,10 +2579,13 @@ CONFIG_VSOCKMON=m CONFIG_ETHERNET=y CONFIG_MDIO=m # CONFIG_NET_VENDOR_3COM is not set @@ -30719,7 +31593,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_NET_VENDOR_ALTEON is not set # CONFIG_ALTERA_TSE is not set CONFIG_NET_VENDOR_AMAZON=y -@@ -2406,14 +2621,13 @@ CONFIG_BNXT_DCB=y +@@ -2406,14 +2622,13 @@ CONFIG_BNXT_DCB=y # CONFIG_BNXT_HWMON is not set CONFIG_NET_VENDOR_CADENCE=y CONFIG_MACB=y @@ -30735,7 +31609,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_LIQUIDIO_CORE=m CONFIG_LIQUIDIO=m CONFIG_LIQUIDIO_VF=m -@@ -2441,7 +2655,10 @@ CONFIG_NET_VENDOR_ENGLEDER=y +@@ -2441,7 +2656,10 @@ CONFIG_NET_VENDOR_ENGLEDER=y CONFIG_NET_VENDOR_FUNGIBLE=y # CONFIG_FUN_ETH is not set CONFIG_NET_VENDOR_GOOGLE=y @@ -30746,7 +31620,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_NET_VENDOR_I825XX is not set CONFIG_NET_VENDOR_INTEL=y # CONFIG_E100 is not set -@@ -2464,8 +2681,13 @@ CONFIG_ICE=m +@@ -2464,8 +2682,13 @@ CONFIG_ICE=m CONFIG_ICE_SWITCHDEV=y CONFIG_FM10K=m # CONFIG_IGC is not set @@ -30760,7 +31634,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_JME is not set CONFIG_NET_VENDOR_ADI=y # CONFIG_ADIN1110 is not set -@@ -2506,6 +2728,8 @@ CONFIG_MLXFW=m +@@ -2506,6 +2729,8 @@ CONFIG_MLXFW=m CONFIG_NET_VENDOR_MICROSEMI=y # CONFIG_MSCC_OCELOT_SWITCH is not set CONFIG_NET_VENDOR_MICROSOFT=y @@ -30769,7 +31643,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_NET_VENDOR_MYRI=y # CONFIG_MYRI10GE is not set # CONFIG_FEALNX is not set -@@ -2539,6 +2763,7 @@ CONFIG_QED_OOO=y +@@ -2539,6 +2764,7 @@ CONFIG_QED_OOO=y # CONFIG_NET_VENDOR_BROCADE is not set CONFIG_NET_VENDOR_QUALCOMM=y # CONFIG_QCA7000_SPI is not set @@ -30777,7 +31651,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_QCOM_EMAC=m # CONFIG_RMNET is not set # CONFIG_NET_VENDOR_RDC is not set -@@ -2564,13 +2789,25 @@ CONFIG_SFC_MCDI_MON=y +@@ -2564,13 +2790,25 @@ CONFIG_SFC_MCDI_MON=y CONFIG_SFC_SRIOV=y CONFIG_SFC_MCDI_LOGGING=y # CONFIG_SFC_FALCON is not set @@ -30805,7 +31679,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_NET_VENDOR_SUN is not set # CONFIG_NET_VENDOR_SYNOPSYS is not set # CONFIG_NET_VENDOR_TEHUTI is not set -@@ -2579,13 +2816,18 @@ CONFIG_NET_VENDOR_VERTEXCOM=y +@@ -2579,13 +2817,18 @@ CONFIG_NET_VENDOR_VERTEXCOM=y # CONFIG_MSE102X is not set # CONFIG_NET_VENDOR_VIA is not set CONFIG_NET_VENDOR_WANGXUN=y @@ -30825,7 +31699,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_PHYLINK=y CONFIG_PHYLIB=y CONFIG_SWPHY=y -@@ -2661,6 +2903,7 @@ CONFIG_CAN_CALC_BITTIMING=y +@@ -2661,6 +2904,7 @@ CONFIG_CAN_CALC_BITTIMING=y # CONFIG_CAN_GRCAN is not set # CONFIG_CAN_KVASER_PCIEFD is not set CONFIG_CAN_SLCAN=m @@ -30833,7 +31707,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_CAN_C_CAN=m CONFIG_CAN_C_CAN_PLATFORM=m CONFIG_CAN_C_CAN_PCI=m -@@ -2672,6 +2915,8 @@ CONFIG_CAN_CC770_PLATFORM=m +@@ -2672,6 +2916,8 @@ CONFIG_CAN_CC770_PLATFORM=m # CONFIG_CAN_IFI_CANFD is not set # CONFIG_CAN_M_CAN is not set # CONFIG_CAN_PEAK_PCIEFD is not set @@ -30842,7 +31716,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_CAN_SJA1000=m CONFIG_CAN_EMS_PCI=m # CONFIG_CAN_F81601 is not set -@@ -2711,7 +2956,9 @@ CONFIG_MDIO_DEVICE=y +@@ -2711,7 +2957,9 @@ CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y CONFIG_FWNODE_MDIO=y CONFIG_OF_MDIO=y @@ -30852,7 +31726,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_MDIO_BITBANG=m CONFIG_MDIO_BCM_UNIMAC=m CONFIG_MDIO_CAVIUM=m -@@ -2728,6 +2975,7 @@ CONFIG_MDIO_THUNDER=m +@@ -2728,6 +2976,7 @@ CONFIG_MDIO_THUNDER=m # # MDIO Multiplexers # @@ -30860,7 +31734,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_MDIO_BUS_MUX_GPIO is not set # CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set # CONFIG_MDIO_BUS_MUX_MMIOREG is not set -@@ -2735,7 +2983,7 @@ CONFIG_MDIO_THUNDER=m +@@ -2735,7 +2984,7 @@ CONFIG_MDIO_THUNDER=m # # PCS device drivers # @@ -30869,7 +31743,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # end of PCS device drivers CONFIG_PPP=m -@@ -2768,8 +3016,8 @@ CONFIG_USB_RTL8150=m +@@ -2768,8 +3017,8 @@ CONFIG_USB_RTL8150=m CONFIG_USB_RTL8152=m CONFIG_USB_LAN78XX=m CONFIG_USB_USBNET=m @@ -30880,7 +31754,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_USB_NET_CDCETHER=m CONFIG_USB_NET_CDC_EEM=m CONFIG_USB_NET_CDC_NCM=m -@@ -2781,7 +3029,7 @@ CONFIG_USB_NET_SR9700=m +@@ -2781,7 +3030,7 @@ CONFIG_USB_NET_SR9700=m CONFIG_USB_NET_SMSC75XX=m CONFIG_USB_NET_SMSC95XX=m CONFIG_USB_NET_GL620A=m @@ -30889,7 +31763,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_USB_NET_PLUSB=m CONFIG_USB_NET_MCS7830=m CONFIG_USB_NET_RNDIS_HOST=m -@@ -2865,7 +3113,39 @@ CONFIG_RT2X00_LIB_CRYPTO=y +@@ -2865,7 +3114,39 @@ CONFIG_RT2X00_LIB_CRYPTO=y CONFIG_RT2X00_LIB_LEDS=y # CONFIG_RT2X00_LIB_DEBUGFS is not set # CONFIG_RT2X00_DEBUG is not set @@ -30930,7 +31804,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_WLAN_VENDOR_RSI is not set CONFIG_WLAN_VENDOR_SILABS=y # CONFIG_WFX is not set -@@ -2876,6 +3156,10 @@ CONFIG_WLAN_VENDOR_SILABS=y +@@ -2876,6 +3157,10 @@ CONFIG_WLAN_VENDOR_SILABS=y # CONFIG_USB_NET_RNDIS_WLAN is not set # CONFIG_MAC80211_HWSIM is not set # CONFIG_VIRT_WIFI is not set @@ -30941,7 +31815,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_WAN=y CONFIG_HDLC=m CONFIG_HDLC_RAW=m -@@ -2900,6 +3184,7 @@ CONFIG_HDLC_PPP=m +@@ -2900,6 +3185,7 @@ CONFIG_HDLC_PPP=m # end of Wireless WAN # CONFIG_VMXNET3 is not set @@ -30949,7 +31823,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_USB4_NET=m # CONFIG_NETDEVSIM is not set CONFIG_NET_FAILOVER=y -@@ -2930,6 +3215,7 @@ CONFIG_INPUT_EVDEV=y +@@ -2930,6 +3216,7 @@ CONFIG_INPUT_EVDEV=y # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y @@ -30957,7 +31831,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_KEYBOARD_ADP5588 is not set # CONFIG_KEYBOARD_ADP5589 is not set CONFIG_KEYBOARD_ATKBD=y -@@ -2955,6 +3241,7 @@ CONFIG_KEYBOARD_GPIO=y +@@ -2955,6 +3242,7 @@ CONFIG_KEYBOARD_GPIO=y # CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set # CONFIG_KEYBOARD_STOWAWAY is not set # CONFIG_KEYBOARD_SUNKBD is not set @@ -30965,7 +31839,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_KEYBOARD_OMAP4 is not set # CONFIG_KEYBOARD_TM2_TOUCHKEY is not set # CONFIG_KEYBOARD_XTKBD is not set -@@ -2987,7 +3274,83 @@ CONFIG_MOUSE_SYNAPTICS_I2C=m +@@ -2987,7 +3275,83 @@ CONFIG_MOUSE_SYNAPTICS_I2C=m CONFIG_MOUSE_SYNAPTICS_USB=m # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set @@ -31050,7 +31924,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_INPUT_MISC=y # CONFIG_INPUT_AD714X is not set # CONFIG_INPUT_ATMEL_CAPTOUCH is not set -@@ -3004,7 +3367,7 @@ CONFIG_INPUT_MISC=y +@@ -3004,7 +3368,7 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_YEALINK is not set # CONFIG_INPUT_CM109 is not set # CONFIG_INPUT_REGULATOR_HAPTIC is not set @@ -31059,7 +31933,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_INPUT_PCF8574 is not set # CONFIG_INPUT_PWM_BEEPER is not set # CONFIG_INPUT_PWM_VIBRA is not set -@@ -3017,9 +3380,11 @@ CONFIG_INPUT_UINPUT=m +@@ -3017,9 +3381,11 @@ CONFIG_INPUT_UINPUT=m # CONFIG_INPUT_IQS626A is not set # CONFIG_INPUT_IQS7222 is not set # CONFIG_INPUT_CMA3000 is not set @@ -31071,7 +31945,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_RMI4_CORE=m CONFIG_RMI4_I2C=m CONFIG_RMI4_SPI=m -@@ -3048,6 +3413,7 @@ CONFIG_SERIO_ALTERA_PS2=m +@@ -3048,6 +3414,7 @@ CONFIG_SERIO_ALTERA_PS2=m # CONFIG_SERIO_PS2MULT is not set CONFIG_SERIO_ARC_PS2=m # CONFIG_SERIO_APBPS2 is not set @@ -31079,7 +31953,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_SERIO_GPIO_PS2 is not set # CONFIG_USERIO is not set # CONFIG_GAMEPORT is not set -@@ -3075,6 +3441,7 @@ CONFIG_LDISC_AUTOLOAD=y +@@ -3075,6 +3442,7 @@ CONFIG_LDISC_AUTOLOAD=y CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_8250=y # CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set @@ -31087,7 +31961,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_SERIAL_8250_16550A_VARIANTS=y # CONFIG_SERIAL_8250_FINTEK is not set CONFIG_SERIAL_8250_CONSOLE=y -@@ -3082,8 +3449,8 @@ CONFIG_SERIAL_8250_DMA=y +@@ -3082,8 +3450,8 @@ CONFIG_SERIAL_8250_DMA=y CONFIG_SERIAL_8250_PCILIB=y CONFIG_SERIAL_8250_PCI=y CONFIG_SERIAL_8250_EXAR=y @@ -31098,7 +31972,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y # CONFIG_SERIAL_8250_PCI1XXXX is not set -@@ -3092,6 +3459,7 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y +@@ -3092,6 +3460,7 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_RSA=y CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_8250_DW=y @@ -31106,7 +31980,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_SERIAL_8250_RT288X=y CONFIG_SERIAL_8250_PERICOM=y CONFIG_SERIAL_OF_PLATFORM=y -@@ -3102,10 +3470,16 @@ CONFIG_SERIAL_OF_PLATFORM=y +@@ -3102,10 +3471,16 @@ CONFIG_SERIAL_OF_PLATFORM=y # CONFIG_SERIAL_AMBA_PL010 is not set # CONFIG_SERIAL_AMBA_PL011 is not set # CONFIG_SERIAL_EARLYCON_SEMIHOST is not set @@ -31123,7 +31997,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_CONSOLE_POLL=y -@@ -3123,6 +3497,8 @@ CONFIG_SERIAL_SIFIVE_CONSOLE=y +@@ -3123,6 +3498,8 @@ CONFIG_SERIAL_SIFIVE_CONSOLE=y # CONFIG_SERIAL_FSL_LINFLEXUART is not set # CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set # CONFIG_SERIAL_SPRD is not set @@ -31132,7 +32006,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # end of Serial drivers CONFIG_SERIAL_MCTRL_GPIO=y -@@ -3135,11 +3511,14 @@ CONFIG_N_GSM=m +@@ -3135,11 +3512,14 @@ CONFIG_N_GSM=m # CONFIG_NOZOMI is not set # CONFIG_NULL_TTY is not set CONFIG_HVC_DRIVER=y @@ -31148,7 +32022,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_IPMI_PLAT_DATA=y # CONFIG_IPMI_PANIC_EVENT is not set CONFIG_IPMI_DEVICE_INTERFACE=m -@@ -3154,6 +3533,7 @@ CONFIG_HW_RANDOM=y +@@ -3154,6 +3534,7 @@ CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_TIMERIOMEM=m # CONFIG_HW_RANDOM_BA431 is not set CONFIG_HW_RANDOM_VIRTIO=y @@ -31156,7 +32030,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set # CONFIG_HW_RANDOM_JH7110 is not set -@@ -3172,7 +3552,10 @@ CONFIG_TCG_TIS_I2C_ATMEL=m +@@ -3172,7 +3553,10 @@ CONFIG_TCG_TIS_I2C_ATMEL=m CONFIG_TCG_TIS_I2C_INFINEON=m CONFIG_TCG_TIS_I2C_NUVOTON=m CONFIG_TCG_ATMEL=m @@ -31167,7 +32041,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_TCG_TIS_ST33ZP24=m CONFIG_TCG_TIS_ST33ZP24_I2C=m CONFIG_TCG_TIS_ST33ZP24_SPI=m -@@ -3184,6 +3567,7 @@ CONFIG_TCG_TIS_ST33ZP24_SPI=m +@@ -3184,6 +3568,7 @@ CONFIG_TCG_TIS_ST33ZP24_SPI=m # I2C support # CONFIG_I2C=y @@ -31175,7 +32049,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_I2C_BOARDINFO=y CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=y -@@ -3221,6 +3605,7 @@ CONFIG_I2C_CCGX_UCSI=m +@@ -3221,6 +3606,7 @@ CONFIG_I2C_CCGX_UCSI=m # CONFIG_I2C_ALI15X3 is not set # CONFIG_I2C_AMD756 is not set # CONFIG_I2C_AMD8111 is not set @@ -31183,7 +32057,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_I2C_I801 is not set # CONFIG_I2C_ISCH is not set # CONFIG_I2C_PIIX4 is not set -@@ -3229,9 +3614,15 @@ CONFIG_I2C_NFORCE2=m +@@ -3229,9 +3615,15 @@ CONFIG_I2C_NFORCE2=m # CONFIG_I2C_SIS5595 is not set # CONFIG_I2C_SIS630 is not set # CONFIG_I2C_SIS96X is not set @@ -31199,7 +32073,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # # I2C system bus drivers (mostly embedded / system-on-chip) # -@@ -3240,15 +3631,22 @@ CONFIG_I2C_DESIGNWARE_CORE=y +@@ -3240,15 +3632,22 @@ CONFIG_I2C_DESIGNWARE_CORE=y CONFIG_I2C_DESIGNWARE_SLAVE=y CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_I2C_DESIGNWARE_PCI=m @@ -31222,7 +32096,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # # External I2C/SMBus adapter drivers -@@ -3290,6 +3688,7 @@ CONFIG_SPI_MEM=y +@@ -3290,6 +3689,7 @@ CONFIG_SPI_MEM=y CONFIG_SPI_CADENCE=m # CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_CADENCE_XSPI is not set @@ -31230,7 +32104,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_SPI_DESIGNWARE=y # CONFIG_SPI_DW_DMA is not set CONFIG_SPI_DW_PCI=m -@@ -3302,9 +3701,17 @@ CONFIG_SPI_DW_MMIO=y +@@ -3302,9 +3702,17 @@ CONFIG_SPI_DW_MMIO=y # CONFIG_SPI_PCI1XXXX is not set # CONFIG_SPI_PL022 is not set # CONFIG_SPI_PXA2XX is not set @@ -31248,7 +32122,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_SPI_MXIC is not set # CONFIG_SPI_XCOMM is not set # CONFIG_SPI_XILINX is not set -@@ -3319,7 +3726,7 @@ CONFIG_SPI_SIFIVE=y +@@ -3319,7 +3727,7 @@ CONFIG_SPI_SIFIVE=y # # SPI Protocol Masters # @@ -31257,7 +32131,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_SPI_LOOPBACK_TEST is not set # CONFIG_SPI_TLE62X0 is not set # CONFIG_SPI_SLAVE is not set -@@ -3343,14 +3750,8 @@ CONFIG_PPS_CLIENT_GPIO=m +@@ -3343,14 +3751,8 @@ CONFIG_PPS_CLIENT_GPIO=m # # PTP clock support # @@ -31273,7 +32147,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # end of PTP clock support CONFIG_PINCTRL=y -@@ -3360,26 +3761,59 @@ CONFIG_GENERIC_PINMUX_FUNCTIONS=y +@@ -3360,26 +3762,59 @@ CONFIG_GENERIC_PINMUX_FUNCTIONS=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set @@ -31333,7 +32207,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_GPIOLIB_IRQCHIP=y # CONFIG_DEBUG_GPIO is not set CONFIG_GPIO_SYSFS=y -@@ -3392,6 +3826,7 @@ CONFIG_GPIO_GENERIC=y +@@ -3392,6 +3827,7 @@ CONFIG_GPIO_GENERIC=y # # CONFIG_GPIO_74XX_MMIO is not set # CONFIG_GPIO_ALTERA is not set @@ -31341,7 +32215,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_GPIO_CADENCE=m CONFIG_GPIO_DWAPB=y # CONFIG_GPIO_EXAR is not set -@@ -3402,6 +3837,7 @@ CONFIG_GPIO_GENERIC_PLATFORM=m +@@ -3402,6 +3838,7 @@ CONFIG_GPIO_GENERIC_PLATFORM=m # CONFIG_GPIO_LOGICVC is not set # CONFIG_GPIO_MB86S7X is not set # CONFIG_GPIO_PL061 is not set @@ -31349,7 +32223,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_GPIO_SIFIVE=y # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_XILINX is not set -@@ -3417,7 +3853,8 @@ CONFIG_GPIO_SIFIVE=y +@@ -3417,7 +3854,8 @@ CONFIG_GPIO_SIFIVE=y # CONFIG_GPIO_GW_PLD is not set # CONFIG_GPIO_MAX7300 is not set # CONFIG_GPIO_MAX732X is not set @@ -31359,7 +32233,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_GPIO_PCA9570 is not set # CONFIG_GPIO_PCF857X is not set # CONFIG_GPIO_TPIC2810 is not set -@@ -3461,6 +3898,7 @@ CONFIG_GPIO_SIFIVE=y +@@ -3461,6 +3899,7 @@ CONFIG_GPIO_SIFIVE=y # CONFIG_GPIO_MOCKUP is not set # CONFIG_GPIO_VIRTIO is not set # CONFIG_GPIO_SIM is not set @@ -31367,7 +32241,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # end of Virtual GPIO drivers # CONFIG_W1 is not set -@@ -3477,6 +3915,7 @@ CONFIG_POWER_RESET_SYSCON_POWEROFF=y +@@ -3477,6 +3916,7 @@ CONFIG_POWER_RESET_SYSCON_POWEROFF=y CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y @@ -31375,7 +32249,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_IP5XXX_POWER is not set # CONFIG_TEST_POWER is not set # CONFIG_CHARGER_ADP5061 is not set -@@ -3565,6 +4004,7 @@ CONFIG_SENSORS_G762=m +@@ -3565,6 +4005,7 @@ CONFIG_SENSORS_G762=m # CONFIG_SENSORS_HS3001 is not set CONFIG_SENSORS_IBMAEM=m CONFIG_SENSORS_IBMPEX=m @@ -31383,7 +32257,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_SENSORS_IT87=m CONFIG_SENSORS_JC42=m CONFIG_SENSORS_POWR1220=m -@@ -3600,7 +4040,7 @@ CONFIG_SENSORS_MAX31790=m +@@ -3600,7 +4041,7 @@ CONFIG_SENSORS_MAX31790=m CONFIG_SENSORS_MCP3021=m # CONFIG_SENSORS_TC654 is not set # CONFIG_SENSORS_TPS23861 is not set @@ -31392,7 +32266,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_SENSORS_ADCXX=m CONFIG_SENSORS_LM63=m CONFIG_SENSORS_LM70=m -@@ -3620,6 +4060,7 @@ CONFIG_SENSORS_LM95241=m +@@ -3620,6 +4061,7 @@ CONFIG_SENSORS_LM95241=m CONFIG_SENSORS_LM95245=m CONFIG_SENSORS_PC87360=m CONFIG_SENSORS_PC87427=m @@ -31400,7 +32274,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_SENSORS_NCT6683=m # CONFIG_SENSORS_NCT6775 is not set # CONFIG_SENSORS_NCT6775_I2C is not set -@@ -3680,7 +4121,7 @@ CONFIG_SENSORS_UCD9200=m +@@ -3680,7 +4122,7 @@ CONFIG_SENSORS_UCD9200=m # CONFIG_SENSORS_XDPE152 is not set # CONFIG_SENSORS_XDPE122 is not set CONFIG_SENSORS_ZL6100=m @@ -31409,7 +32283,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SBRMI is not set CONFIG_SENSORS_SHT15=m -@@ -3733,9 +4174,15 @@ CONFIG_SENSORS_W83L785TS=m +@@ -3733,9 +4175,15 @@ CONFIG_SENSORS_W83L785TS=m CONFIG_SENSORS_W83L786NG=m CONFIG_SENSORS_W83627HF=m CONFIG_SENSORS_W83627EHF=m @@ -31426,7 +32300,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y CONFIG_THERMAL_OF=y -@@ -3743,41 +4190,62 @@ CONFIG_THERMAL_OF=y +@@ -3743,41 +4191,62 @@ CONFIG_THERMAL_OF=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set @@ -31492,7 +32366,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # # PCI-based Watchdog Cards -@@ -3804,8 +4272,9 @@ CONFIG_BCMA_DRIVER_GPIO=y +@@ -3804,8 +4273,9 @@ CONFIG_BCMA_DRIVER_GPIO=y # # Multifunction device drivers # @@ -31503,7 +32377,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_MFD_AS3711 is not set # CONFIG_MFD_SMPRO is not set # CONFIG_MFD_AS3722 is not set -@@ -3877,8 +4346,8 @@ CONFIG_MFD_CORE=m +@@ -3877,8 +4347,8 @@ CONFIG_MFD_CORE=m # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set # CONFIG_MFD_STMPE is not set @@ -31513,7 +32387,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_MFD_LP3943 is not set # CONFIG_MFD_LP8788 is not set # CONFIG_MFD_TI_LMU is not set -@@ -3921,6 +4390,8 @@ CONFIG_MFD_SYSCON=y +@@ -3921,6 +4391,8 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_STMFX is not set # CONFIG_MFD_ATC260X_I2C is not set # CONFIG_MFD_QCOM_PM8008 is not set @@ -31522,7 +32396,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_MFD_INTEL_M10_BMC_SPI is not set # CONFIG_MFD_RSMU_I2C is not set # CONFIG_MFD_RSMU_SPI is not set -@@ -3987,6 +4458,7 @@ CONFIG_REGULATOR_PWM=y +@@ -3987,6 +4459,7 @@ CONFIG_REGULATOR_PWM=y # CONFIG_REGULATOR_RTQ6752 is not set # CONFIG_REGULATOR_RTQ2208 is not set # CONFIG_REGULATOR_SLG51000 is not set @@ -31530,7 +32404,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_REGULATOR_SY8106A is not set # CONFIG_REGULATOR_SY8824X is not set # CONFIG_REGULATOR_SY8827N is not set -@@ -3999,6 +4471,7 @@ CONFIG_REGULATOR_PWM=y +@@ -3999,6 +4472,7 @@ CONFIG_REGULATOR_PWM=y # CONFIG_REGULATOR_TPS65132 is not set # CONFIG_REGULATOR_TPS6524X is not set # CONFIG_REGULATOR_VCTRL is not set @@ -31538,7 +32412,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_RC_CORE is not set # -@@ -4007,7 +4480,7 @@ CONFIG_REGULATOR_PWM=y +@@ -4007,7 +4481,7 @@ CONFIG_REGULATOR_PWM=y # CONFIG_MEDIA_CEC_SUPPORT is not set # end of CEC support @@ -31547,7 +32421,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_MEDIA_SUPPORT_FILTER is not set # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set -@@ -4131,10 +4604,12 @@ CONFIG_RADIO_ADAPTERS=m +@@ -4131,10 +4605,12 @@ CONFIG_RADIO_ADAPTERS=m # CONFIG_USB_RAREMONO is not set # CONFIG_RADIO_SI470X is not set CONFIG_MEDIA_PLATFORM_DRIVERS=y @@ -31562,7 +32436,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # # Allegro DVT media platform drivers -@@ -4173,6 +4648,7 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y +@@ -4173,6 +4649,7 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y # # Marvell media platform drivers # @@ -31570,7 +32444,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # # Mediatek media platform drivers -@@ -4197,6 +4673,15 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y +@@ -4197,6 +4674,15 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y # # Renesas media platform drivers # @@ -31586,7 +32460,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # # Rockchip media platform drivers -@@ -4213,6 +4698,11 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y +@@ -4213,6 +4699,11 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y # # Sunxi media platform drivers # @@ -31598,7 +32472,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # # Texas Instruments drivers -@@ -4221,6 +4711,7 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y +@@ -4221,6 +4712,7 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y # # Verisilicon media platform drivers # @@ -31606,7 +32480,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # # VIA media platform drivers -@@ -4229,6 +4720,7 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y +@@ -4229,6 +4721,7 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y # # Xilinx media platform drivers # @@ -31614,7 +32488,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # # MMC/SDIO DVB adapters -@@ -4283,6 +4775,7 @@ CONFIG_VIDEO_CAMERA_SENSOR=y +@@ -4283,6 +4776,7 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_OV2659 is not set # CONFIG_VIDEO_OV2680 is not set # CONFIG_VIDEO_OV2685 is not set @@ -31622,7 +32496,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_VIDEO_OV4689 is not set # CONFIG_VIDEO_OV5640 is not set # CONFIG_VIDEO_OV5645 is not set -@@ -4304,6 +4797,7 @@ CONFIG_VIDEO_CAMERA_SENSOR=y +@@ -4304,6 +4798,7 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_OV9282 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set @@ -31630,7 +32504,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_VIDEO_RDACM20 is not set # CONFIG_VIDEO_RDACM21 is not set # CONFIG_VIDEO_RJ54N1 is not set -@@ -4341,6 +4835,7 @@ CONFIG_VIDEO_CAMERA_SENSOR=y +@@ -4341,6 +4836,7 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_CS53L32A is not set # CONFIG_VIDEO_MSP3400 is not set # CONFIG_VIDEO_SONY_BTF_MPX is not set @@ -31638,7 +32512,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_VIDEO_TDA7432 is not set # CONFIG_VIDEO_TDA9840 is not set # CONFIG_VIDEO_TEA6415C is not set -@@ -4451,7 +4946,7 @@ CONFIG_CXD2880_SPI_DRV=m +@@ -4451,7 +4947,7 @@ CONFIG_CXD2880_SPI_DRV=m # CONFIG_VIDEO_GS1662 is not set # end of Media SPI Adapters @@ -31647,7 +32521,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # # Customize TV tuners -@@ -4668,6 +5163,7 @@ CONFIG_DVB_SP2=m +@@ -4668,6 +5164,7 @@ CONFIG_DVB_SP2=m # Graphics support # CONFIG_APERTURE_HELPERS=y @@ -31655,7 +32529,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_VIDEO_CMDLINE=y CONFIG_VIDEO_NOMODESET=y CONFIG_AUXDISPLAY=y -@@ -4679,6 +5175,7 @@ CONFIG_AUXDISPLAY=y +@@ -4679,6 +5176,7 @@ CONFIG_AUXDISPLAY=y # CONFIG_CHARLCD_BL_ON is not set CONFIG_CHARLCD_BL_FLASH=y CONFIG_DRM=y @@ -31663,7 +32537,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_DRM_DEBUG_MM is not set CONFIG_DRM_KMS_HELPER=y # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set -@@ -4687,7 +5184,7 @@ CONFIG_DRM_FBDEV_EMULATION=y +@@ -4687,7 +5185,7 @@ CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 # CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set CONFIG_DRM_LOAD_EDID_FIRMWARE=y @@ -31672,7 +32546,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_DRM_DISPLAY_DP_HELPER=y CONFIG_DRM_DISPLAY_HDCP_HELPER=y CONFIG_DRM_DISPLAY_HDMI_HELPER=y -@@ -4720,7 +5217,7 @@ CONFIG_DRM_I2C_NXP_TDA998X=m +@@ -4720,7 +5218,7 @@ CONFIG_DRM_I2C_NXP_TDA998X=m CONFIG_DRM_RADEON=m CONFIG_DRM_RADEON_USERPTR=y CONFIG_DRM_AMDGPU=m @@ -31681,7 +32555,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_DRM_AMDGPU_CIK=y CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set -@@ -4735,9 +5232,13 @@ CONFIG_DRM_AMDGPU_USERPTR=y +@@ -4735,9 +5233,13 @@ CONFIG_DRM_AMDGPU_USERPTR=y # Display Engine Configuration # CONFIG_DRM_AMD_DC=y @@ -31695,7 +32569,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_DRM_NOUVEAU=m CONFIG_NOUVEAU_DEBUG=5 CONFIG_NOUVEAU_DEBUG_DEFAULT=3 -@@ -4749,6 +5250,9 @@ CONFIG_DRM_NOUVEAU_BACKLIGHT=y +@@ -4749,6 +5251,9 @@ CONFIG_DRM_NOUVEAU_BACKLIGHT=y CONFIG_DRM_UDL=m CONFIG_DRM_AST=m CONFIG_DRM_MGAG200=m @@ -31705,7 +32579,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_DRM_QXL=m CONFIG_DRM_VIRTIO_GPU=m CONFIG_DRM_VIRTIO_GPU_KMS=y -@@ -4759,36 +5263,89 @@ CONFIG_DRM_PANEL=y +@@ -4759,36 +5264,89 @@ CONFIG_DRM_PANEL=y # # CONFIG_DRM_PANEL_ABT_Y030XX067A is not set # CONFIG_DRM_PANEL_ARM_VERSATILE is not set @@ -31796,7 +32670,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # end of Display Panels CONFIG_DRM_BRIDGE=y -@@ -4834,10 +5391,16 @@ CONFIG_DRM_PANEL_BRIDGE=y +@@ -4834,10 +5392,16 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_I2C_ADV7511 is not set # CONFIG_DRM_CDNS_DSI is not set # CONFIG_DRM_CDNS_MHDP8546 is not set @@ -31814,7 +32688,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_DRM_LOGICVC is not set # CONFIG_DRM_ARCPGU is not set CONFIG_DRM_BOCHS=m -@@ -4856,6 +5419,14 @@ CONFIG_DRM_CIRRUS_QEMU=m +@@ -4856,6 +5420,14 @@ CONFIG_DRM_CIRRUS_QEMU=m # CONFIG_TINYDRM_ST7735R is not set # CONFIG_DRM_GUD is not set # CONFIG_DRM_SSD130X is not set @@ -31829,7 +32703,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -@@ -4894,6 +5465,7 @@ CONFIG_FB_RADEON_BACKLIGHT=y +@@ -4894,6 +5466,7 @@ CONFIG_FB_RADEON_BACKLIGHT=y # CONFIG_FB_ARK is not set # CONFIG_FB_PM3 is not set # CONFIG_FB_CARMINE is not set @@ -31837,7 +32711,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_FB_SMSCUFX is not set # CONFIG_FB_UDL is not set # CONFIG_FB_IBM_GXT4500 is not set -@@ -4919,6 +5491,7 @@ CONFIG_FB_SYS_IMAGEBLIT=y +@@ -4919,6 +5492,7 @@ CONFIG_FB_SYS_IMAGEBLIT=y # CONFIG_FB_FOREIGN_ENDIAN is not set CONFIG_FB_SYS_FOPS=y CONFIG_FB_DEFERRED_IO=y @@ -31845,7 +32719,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_FB_IOMEM_HELPERS=y CONFIG_FB_SYSMEM_HELPERS=y CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y -@@ -4946,7 +5519,7 @@ CONFIG_LCD_PLATFORM=m +@@ -4946,7 +5520,7 @@ CONFIG_LCD_PLATFORM=m CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_KTD253 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set @@ -31854,7 +32728,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_BACKLIGHT_QCOM_WLED is not set # CONFIG_BACKLIGHT_ADP8860 is not set # CONFIG_BACKLIGHT_ADP8870 is not set -@@ -4960,6 +5533,7 @@ CONFIG_BACKLIGHT_GPIO=m +@@ -4960,6 +5534,7 @@ CONFIG_BACKLIGHT_GPIO=m # CONFIG_BACKLIGHT_LED is not set # end of Backlight & LCD device support @@ -31862,7 +32736,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_HDMI=y # -@@ -4983,10 +5557,13 @@ CONFIG_LOGO_LINUX_CLUT224=y +@@ -4983,10 +5558,13 @@ CONFIG_LOGO_LINUX_CLUT224=y # end of Graphics support # CONFIG_DRM_ACCEL is not set @@ -31880,7 +32754,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_SND_HWDEP=m CONFIG_SND_RAWMIDI=m CONFIG_SND_JACK=y -@@ -5010,6 +5587,7 @@ CONFIG_SND_ALOOP=m +@@ -5010,6 +5588,7 @@ CONFIG_SND_ALOOP=m # CONFIG_SND_PCMTEST is not set # CONFIG_SND_MTPAV is not set # CONFIG_SND_SERIAL_U16550 is not set @@ -31888,7 +32762,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_SND_MPU401 is not set CONFIG_SND_PCI=y # CONFIG_SND_AD1889 is not set -@@ -5074,6 +5652,11 @@ CONFIG_SND_HDA_INTEL=m +@@ -5074,6 +5653,11 @@ CONFIG_SND_HDA_INTEL=m # CONFIG_SND_HDA_RECONFIG is not set # CONFIG_SND_HDA_INPUT_BEEP is not set # CONFIG_SND_HDA_PATCH_LOADER is not set @@ -31900,7 +32774,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_SND_HDA_CODEC_REALTEK is not set # CONFIG_SND_HDA_CODEC_ANALOG is not set # CONFIG_SND_HDA_CODEC_SIGMATEL is not set -@@ -5095,7 +5678,9 @@ CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0 +@@ -5095,7 +5679,9 @@ CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0 CONFIG_SND_HDA_CORE=m CONFIG_SND_HDA_COMPONENT=y CONFIG_SND_HDA_PREALLOC_SIZE=64 @@ -31910,7 +32784,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_SND_SPI=y CONFIG_SND_USB=y CONFIG_SND_USB_AUDIO=m -@@ -5110,7 +5695,273 @@ CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y +@@ -5110,7 +5696,273 @@ CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y # CONFIG_SND_USB_PODHD is not set # CONFIG_SND_USB_TONEPORT is not set # CONFIG_SND_USB_VARIAX is not set @@ -32185,7 +33059,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_SND_VIRTIO is not set CONFIG_HID_SUPPORT=y CONFIG_HID=y -@@ -5195,6 +6046,7 @@ CONFIG_HID_MULTITOUCH=m +@@ -5195,6 +6047,7 @@ CONFIG_HID_MULTITOUCH=m # CONFIG_HID_NINTENDO is not set # CONFIG_HID_NTI is not set CONFIG_HID_NTRIG=y @@ -32193,7 +33067,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_HID_ORTEK=m CONFIG_HID_PANTHERLORD=m # CONFIG_PANTHERLORD_FF is not set -@@ -5261,6 +6113,7 @@ CONFIG_USB_HIDDEV=y +@@ -5261,6 +6114,7 @@ CONFIG_USB_HIDDEV=y # end of USB HID support CONFIG_I2C_HID=y @@ -32201,7 +33075,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_I2C_HID_OF is not set # CONFIG_I2C_HID_OF_ELAN is not set # CONFIG_I2C_HID_OF_GOODIX is not set -@@ -5297,6 +6150,7 @@ CONFIG_USB_XHCI_HCD=y +@@ -5297,6 +6151,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y # CONFIG_USB_XHCI_PCI_RENESAS is not set CONFIG_USB_XHCI_PLATFORM=y @@ -32209,7 +33083,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y -@@ -5314,6 +6168,7 @@ CONFIG_USB_UHCI_HCD=y +@@ -5314,6 +6169,7 @@ CONFIG_USB_UHCI_HCD=y # CONFIG_USB_R8A66597_HCD is not set # CONFIG_USB_HCD_BCMA is not set # CONFIG_USB_HCD_TEST_MODE is not set @@ -32217,7 +33091,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # # USB Device Class drivers -@@ -5338,8 +6193,8 @@ CONFIG_USB_STORAGE_DATAFAB=m +@@ -5338,8 +6194,8 @@ CONFIG_USB_STORAGE_DATAFAB=m CONFIG_USB_STORAGE_FREECOM=m CONFIG_USB_STORAGE_ISD200=m CONFIG_USB_STORAGE_USBAT=m @@ -32228,7 +33102,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_USB_STORAGE_JUMPSHOT=m CONFIG_USB_STORAGE_ALAUDA=m CONFIG_USB_STORAGE_ONETOUCH=m -@@ -5360,7 +6215,19 @@ CONFIG_USB_MICROTEK=m +@@ -5360,7 +6216,19 @@ CONFIG_USB_MICROTEK=m # # CONFIG_USB_CDNS_SUPPORT is not set # CONFIG_USB_MUSB_HDRC is not set @@ -32249,7 +33123,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_USB_DWC2 is not set # CONFIG_USB_CHIPIDEA is not set # CONFIG_USB_ISP1760 is not set -@@ -5452,7 +6319,7 @@ CONFIG_USB_HSIC_USB3503=m +@@ -5452,7 +6320,7 @@ CONFIG_USB_HSIC_USB3503=m # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set CONFIG_USB_CHAOSKEY=m @@ -32258,7 +33132,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_USB_ATM=m # CONFIG_USB_SPEEDTOUCH is not set CONFIG_USB_CXACRU=m -@@ -5467,7 +6334,101 @@ CONFIG_USB_XUSBATM=m +@@ -5467,7 +6335,101 @@ CONFIG_USB_XUSBATM=m # CONFIG_USB_ISP1301 is not set # end of USB Physical Layer drivers @@ -32361,7 +33235,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_TYPEC=m CONFIG_TYPEC_TCPM=m CONFIG_TYPEC_TCPCI=m -@@ -5476,6 +6437,7 @@ CONFIG_TYPEC_TCPCI=m +@@ -5476,6 +6438,7 @@ CONFIG_TYPEC_TCPCI=m # CONFIG_TYPEC_FUSB302 is not set CONFIG_TYPEC_UCSI=m # CONFIG_UCSI_CCG is not set @@ -32369,7 +33243,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_UCSI_STM32G0 is not set # CONFIG_TYPEC_TPS6598X is not set # CONFIG_TYPEC_ANX7411 is not set -@@ -5500,7 +6462,7 @@ CONFIG_TYPEC_DP_ALTMODE=m +@@ -5500,7 +6463,7 @@ CONFIG_TYPEC_DP_ALTMODE=m # CONFIG_TYPEC_NVIDIA_ALTMODE is not set # end of USB Type-C Alternate Mode drivers @@ -32378,7 +33252,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_MMC=y CONFIG_PWRSEQ_EMMC=m CONFIG_PWRSEQ_SIMPLE=m -@@ -5519,15 +6481,19 @@ CONFIG_MMC_SDHCI=y +@@ -5519,15 +6482,19 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_IO_ACCESSORS=y CONFIG_MMC_SDHCI_PCI=m CONFIG_MMC_RICOH_MMC=y @@ -32399,7 +33273,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_MMC_CB710=m CONFIG_MMC_VIA_SDMMC=m CONFIG_MMC_DW=m -@@ -5538,18 +6504,18 @@ CONFIG_MMC_DW_BLUEFIELD=m +@@ -5538,18 +6505,18 @@ CONFIG_MMC_DW_BLUEFIELD=m # CONFIG_MMC_DW_K3 is not set CONFIG_MMC_DW_PCI=m # CONFIG_MMC_DW_STARFIVE is not set @@ -32420,7 +33294,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_SCSI_UFSHCD is not set CONFIG_MEMSTICK=m # CONFIG_MEMSTICK_DEBUG is not set -@@ -5590,7 +6556,7 @@ CONFIG_LEDS_LM3530=m +@@ -5590,7 +6557,7 @@ CONFIG_LEDS_LM3530=m # CONFIG_LEDS_LM3642 is not set # CONFIG_LEDS_LM3692X is not set # CONFIG_LEDS_PCA9532 is not set @@ -32429,7 +33303,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_LEDS_LP3944=m # CONFIG_LEDS_LP3952 is not set # CONFIG_LEDS_LP50XX is not set -@@ -5672,6 +6638,7 @@ CONFIG_INFINIBAND_USER_MEM=y +@@ -5672,6 +6639,7 @@ CONFIG_INFINIBAND_USER_MEM=y CONFIG_INFINIBAND_ON_DEMAND_PAGING=y CONFIG_INFINIBAND_ADDR_TRANS=y CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y @@ -32437,7 +33311,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_INFINIBAND_VIRT_DMA=y CONFIG_INFINIBAND_BNXT_RE=m CONFIG_INFINIBAND_CXGB4=m -@@ -5753,6 +6720,7 @@ CONFIG_RTC_DRV_EM3027=m +@@ -5753,6 +6721,7 @@ CONFIG_RTC_DRV_EM3027=m # CONFIG_RTC_DRV_RV3032 is not set CONFIG_RTC_DRV_RV8803=m # CONFIG_RTC_DRV_SD3078 is not set @@ -32445,7 +33319,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # # SPI RTC drivers -@@ -5804,21 +6772,28 @@ CONFIG_RTC_DRV_M48T35=m +@@ -5804,21 +6773,28 @@ CONFIG_RTC_DRV_M48T35=m CONFIG_RTC_DRV_M48T59=m CONFIG_RTC_DRV_MSM6242=m CONFIG_RTC_DRV_RP5C01=m @@ -32474,7 +33348,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set -@@ -5826,12 +6801,16 @@ CONFIG_DMADEVICES=y +@@ -5826,12 +6802,16 @@ CONFIG_DMADEVICES=y # DMA Devices # CONFIG_DMA_ENGINE=y @@ -32492,7 +33366,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_PL330_DMA is not set # CONFIG_PLX_DMA is not set # CONFIG_XILINX_DMA is not set -@@ -5844,6 +6823,8 @@ CONFIG_DW_DMAC=m +@@ -5844,6 +6824,8 @@ CONFIG_DW_DMAC=m CONFIG_DW_DMAC_PCI=m # CONFIG_DW_EDMA is not set # CONFIG_SF_PDMA is not set @@ -32501,7 +33375,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # # DMA Clients -@@ -5855,11 +6836,11 @@ CONFIG_ASYNC_TX_DMA=y +@@ -5855,11 +6837,11 @@ CONFIG_ASYNC_TX_DMA=y # DMABUF options # CONFIG_SYNC_FILE=y @@ -32516,7 +33390,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_DMABUF_HEAPS is not set # CONFIG_DMABUF_SYSFS_STATS is not set # end of DMABUF options -@@ -5877,8 +6858,10 @@ CONFIG_UIO_PCI_GENERIC=m +@@ -5877,8 +6859,10 @@ CONFIG_UIO_PCI_GENERIC=m CONFIG_VFIO=m CONFIG_VFIO_GROUP=y CONFIG_VFIO_CONTAINER=y @@ -32527,7 +33401,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # # VFIO support for PCI devices -@@ -5948,8 +6931,11 @@ CONFIG_COMMON_CLK=y +@@ -5948,8 +6932,13 @@ CONFIG_COMMON_CLK=y # CONFIG_COMMON_CLK_VC7 is not set # CONFIG_COMMON_CLK_FIXED_MMIO is not set CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y @@ -32535,11 +33409,13 @@ index 61f2b2f12589..0f2b22d817e1 100644 +# CONFIG_CLK_RCAR_USB2_CLOCK_SEL is not set CONFIG_CLK_SIFIVE=y CONFIG_CLK_SIFIVE_PRCI=y ++CONFIG_SPACEMIT_CCU=y +CONFIG_SPACEMIT_K1_CCU=y ++CONFIG_SPACEMIT_K3_CCU=y CONFIG_CLK_STARFIVE_JH71X0=y CONFIG_CLK_STARFIVE_JH7100=y CONFIG_CLK_STARFIVE_JH7100_AUDIO=m -@@ -5959,15 +6945,27 @@ CONFIG_CLK_STARFIVE_JH7110_AON=m +@@ -5959,15 +6948,27 @@ CONFIG_CLK_STARFIVE_JH7110_AON=m CONFIG_CLK_STARFIVE_JH7110_STG=m CONFIG_CLK_STARFIVE_JH7110_ISP=m CONFIG_CLK_STARFIVE_JH7110_VOUT=m @@ -32567,7 +33443,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_RISCV_TIMER=y # end of Clock Source drivers -@@ -5976,8 +6974,12 @@ CONFIG_MAILBOX=y +@@ -5976,8 +6977,12 @@ CONFIG_MAILBOX=y # CONFIG_ARM_MHU_V2 is not set # CONFIG_PLATFORM_MHU is not set # CONFIG_PL320_MBOX is not set @@ -32580,7 +33456,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_IOMMU_API=y CONFIG_IOMMU_SUPPORT=y -@@ -5991,7 +6993,11 @@ CONFIG_IOMMU_SUPPORT=y +@@ -5991,7 +6996,11 @@ CONFIG_IOMMU_SUPPORT=y CONFIG_IOMMU_DEFAULT_DMA_LAZY=y # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set CONFIG_OF_IOMMU=y @@ -32592,7 +33468,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # # Remoteproc drivers -@@ -6007,6 +7013,7 @@ CONFIG_RPMSG_CHAR=y +@@ -6007,6 +7016,7 @@ CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_CTRL=y CONFIG_RPMSG_NS=y # CONFIG_RPMSG_QCOM_GLINK_RPM is not set @@ -32600,7 +33476,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_RPMSG_VIRTIO=y # end of Rpmsg drivers -@@ -6055,22 +7062,73 @@ CONFIG_RPMSG_VIRTIO=y +@@ -6055,22 +7065,73 @@ CONFIG_RPMSG_VIRTIO=y # CONFIG_QCOM_PMIC_GLINK is not set # end of Qualcomm SoC drivers @@ -32675,7 +33551,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_EXTCON_FSA9480 is not set CONFIG_EXTCON_GPIO=m # CONFIG_EXTCON_MAX3355 is not set -@@ -6080,7 +7138,540 @@ CONFIG_EXTCON_GPIO=m +@@ -6080,7 +7141,540 @@ CONFIG_EXTCON_GPIO=m # CONFIG_EXTCON_USB_GPIO is not set # CONFIG_EXTCON_USBC_TUSB320 is not set # CONFIG_MEMORY is not set @@ -33217,7 +34093,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_NTB is not set CONFIG_PWM=y CONFIG_PWM_SYSFS=y -@@ -6090,7 +7681,12 @@ CONFIG_PWM_SYSFS=y +@@ -6090,7 +7684,12 @@ CONFIG_PWM_SYSFS=y # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_PCA9685 is not set @@ -33230,7 +34106,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_PWM_XILINX is not set # -@@ -6099,15 +7695,24 @@ CONFIG_PWM_SIFIVE=m +@@ -6099,15 +7698,26 @@ CONFIG_PWM_SIFIVE=m CONFIG_IRQCHIP=y # CONFIG_AL_FIC is not set # CONFIG_XILINX_INTC is not set @@ -33251,11 +34127,13 @@ index 61f2b2f12589..0f2b22d817e1 100644 +CONFIG_RESET_TH1520=y # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RESET_TI_TPS380X is not set -+CONFIG_RESET_K1_SPACEMIT=y ++CONFIG_RESET_SPACEMIT=y ++CONFIG_RESET_SPACEMIT_K1=y ++CONFIG_RESET_SPACEMIT_K3=y CONFIG_RESET_STARFIVE_JH71X0=y CONFIG_RESET_STARFIVE_JH7100=y CONFIG_RESET_STARFIVE_JH7110=y -@@ -6116,7 +7721,12 @@ CONFIG_RESET_STARFIVE_JH7110=y +@@ -6116,7 +7726,12 @@ CONFIG_RESET_STARFIVE_JH7110=y # PHY Subsystem # CONFIG_GENERIC_PHY=y @@ -33268,7 +34146,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # # PHY drivers for Broadcom platforms -@@ -6132,14 +7742,21 @@ CONFIG_GENERIC_PHY=y +@@ -6132,14 +7747,21 @@ CONFIG_GENERIC_PHY=y # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set # CONFIG_PHY_LAN966X_SERDES is not set @@ -33290,7 +34168,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # end of PHY Subsystem # CONFIG_POWERCAP is not set -@@ -6151,6 +7768,9 @@ CONFIG_GENERIC_PHY=y +@@ -6151,6 +7773,9 @@ CONFIG_GENERIC_PHY=y CONFIG_RISCV_PMU=y CONFIG_RISCV_PMU_LEGACY=y CONFIG_RISCV_PMU_SBI=y @@ -33300,7 +34178,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # end of Performance monitor support CONFIG_RAS=y -@@ -6191,7 +7811,9 @@ CONFIG_NVMEM_SYSFS=y +@@ -6191,7 +7816,9 @@ CONFIG_NVMEM_SYSFS=y # end of Layout Types # CONFIG_NVMEM_RMEM is not set @@ -33310,7 +34188,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # # HW tracing support -@@ -6202,6 +7824,8 @@ CONFIG_NVMEM_SYSFS=y +@@ -6202,6 +7829,8 @@ CONFIG_NVMEM_SYSFS=y # CONFIG_FPGA is not set # CONFIG_FSI is not set @@ -33319,7 +34197,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_PM_OPP=y # CONFIG_SIOX is not set # CONFIG_SLIMBUS is not set -@@ -6223,6 +7847,7 @@ CONFIG_INTERCONNECT=y +@@ -6223,6 +7852,7 @@ CONFIG_INTERCONNECT=y # CONFIG_VALIDATE_FS_PARSER=y CONFIG_FS_IOMAP=y @@ -33327,7 +34205,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_BUFFER_HEAD=y CONFIG_LEGACY_DIRECT_IO=y # CONFIG_EXT2_FS is not set -@@ -6235,6 +7860,7 @@ CONFIG_EXT4_FS_POSIX_ACL=y +@@ -6235,6 +7865,7 @@ CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y # CONFIG_EXT4_DEBUG is not set # CONFIG_EXT4_ERROR_REPORT is not set @@ -33335,7 +34213,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_JBD2=y # CONFIG_JBD2_DEBUG is not set CONFIG_FS_MBCACHE=y -@@ -6289,10 +7915,12 @@ CONFIG_QUOTA_TREE=y +@@ -6289,10 +7920,12 @@ CONFIG_QUOTA_TREE=y CONFIG_QFMT_V2=y CONFIG_QUOTACTL=y CONFIG_AUTOFS_FS=y @@ -33350,7 +34228,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # CONFIG_OVERLAY_FS_INDEX is not set -@@ -6363,9 +7991,9 @@ CONFIG_TMPFS_XATTR=y +@@ -6363,9 +7996,9 @@ CONFIG_TMPFS_XATTR=y # CONFIG_TMPFS_QUOTA is not set CONFIG_ARCH_SUPPORTS_HUGETLBFS=y CONFIG_HUGETLBFS=y @@ -33361,7 +34239,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_HUGETLB_ALLOC_LIMIT is not set CONFIG_ARCH_HAS_GIGANTIC_PAGE=y CONFIG_CONFIGFS_FS=y -@@ -6382,8 +8010,24 @@ CONFIG_MISC_FILESYSTEMS=y +@@ -6382,8 +8015,24 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set @@ -33388,7 +34266,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_CRAMFS=m CONFIG_CRAMFS_BLOCKDEV=y # CONFIG_CRAMFS_MTD is not set -@@ -6422,6 +8066,7 @@ CONFIG_PSTORE_RAM=m +@@ -6422,6 +8071,7 @@ CONFIG_PSTORE_RAM=m # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set # CONFIG_EROFS_FS is not set @@ -33396,7 +34274,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V2=m -@@ -6432,7 +8077,7 @@ CONFIG_NFS_V4=y +@@ -6432,7 +8082,7 @@ CONFIG_NFS_V4=y CONFIG_NFS_V4_1=y CONFIG_NFS_V4_2=y CONFIG_PNFS_FILE_LAYOUT=y @@ -33405,7 +34283,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_PNFS_FLEXFILE_LAYOUT=m CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" # CONFIG_NFS_V4_1_MIGRATION is not set -@@ -6518,7 +8163,7 @@ CONFIG_NLS_ISO8859_8=m +@@ -6518,7 +8168,7 @@ CONFIG_NLS_ISO8859_8=m CONFIG_NLS_CODEPAGE_1250=m CONFIG_NLS_CODEPAGE_1251=m CONFIG_NLS_ASCII=y @@ -33414,7 +34292,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_NLS_ISO8859_2=m CONFIG_NLS_ISO8859_3=m CONFIG_NLS_ISO8859_4=m -@@ -6557,6 +8202,7 @@ CONFIG_KEYS=y +@@ -6557,6 +8207,7 @@ CONFIG_KEYS=y CONFIG_PERSISTENT_KEYRINGS=y CONFIG_TRUSTED_KEYS=y CONFIG_TRUSTED_KEYS_TPM=y @@ -33422,7 +34300,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_ENCRYPTED_KEYS=y # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_KEY_DH_OPERATIONS is not set -@@ -6635,6 +8281,7 @@ CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS=y +@@ -6635,6 +8286,7 @@ CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS=y CONFIG_IMA_QUEUE_EARLY_BOOT_KEYS=y # CONFIG_IMA_DISABLE_HTABLE is not set # CONFIG_IMA_DIGEST_LIST is not set @@ -33430,7 +34308,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_EVM=y # CONFIG_EVM_DEFAULT_HASH_SHA1 is not set CONFIG_EVM_DEFAULT_HASH_SHA256=y -@@ -6657,6 +8304,8 @@ CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,appar +@@ -6657,6 +8309,8 @@ CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,appar # Memory initialization # CONFIG_INIT_STACK_NONE=y @@ -33439,7 +34317,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set # CONFIG_ZERO_CALL_USED_REGS is not set -@@ -6670,9 +8319,9 @@ CONFIG_LIST_HARDENED=y +@@ -6670,9 +8324,9 @@ CONFIG_LIST_HARDENED=y # end of Hardening of kernel data structures CONFIG_RANDSTRUCT_NONE=y @@ -33451,7 +34329,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # end of Security options CONFIG_XOR_BLOCKS=m -@@ -6693,6 +8342,7 @@ CONFIG_CRYPTO_ALGAPI=y +@@ -6693,6 +8347,7 @@ CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y @@ -33459,7 +34337,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_CRYPTO_SIG2=y CONFIG_CRYPTO_SKCIPHER=y CONFIG_CRYPTO_SKCIPHER2=y -@@ -6704,18 +8354,18 @@ CONFIG_CRYPTO_RNG_DEFAULT=y +@@ -6704,18 +8359,18 @@ CONFIG_CRYPTO_RNG_DEFAULT=y CONFIG_CRYPTO_AKCIPHER2=y CONFIG_CRYPTO_AKCIPHER=y CONFIG_CRYPTO_KPP2=y @@ -33481,7 +34359,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_CRYPTO_TEST=m CONFIG_CRYPTO_ENGINE=y # end of Crypto core or helper -@@ -6724,14 +8374,14 @@ CONFIG_CRYPTO_ENGINE=y +@@ -6724,14 +8379,14 @@ CONFIG_CRYPTO_ENGINE=y # Public-key cryptography # CONFIG_CRYPTO_RSA=y @@ -33500,7 +34378,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # end of Public-key cryptography # -@@ -6747,7 +8397,7 @@ CONFIG_CRYPTO_CAMELLIA=m +@@ -6747,7 +8402,7 @@ CONFIG_CRYPTO_CAMELLIA=m CONFIG_CRYPTO_CAST_COMMON=m CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m @@ -33509,7 +34387,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_SEED=m -@@ -6764,7 +8414,7 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m +@@ -6764,7 +8419,7 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # # CONFIG_CRYPTO_ADIANTUM is not set CONFIG_CRYPTO_ARC4=m @@ -33518,7 +34396,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_CRYPTO_CBC=y # CONFIG_CRYPTO_CFB is not set CONFIG_CRYPTO_CTR=y -@@ -6773,35 +8423,35 @@ CONFIG_CRYPTO_ECB=y +@@ -6773,35 +8428,35 @@ CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_HCTR2 is not set # CONFIG_CRYPTO_KEYWRAP is not set CONFIG_CRYPTO_LRW=m @@ -33561,7 +34439,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_CRYPTO_RMD160=m CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y -@@ -6864,6 +8514,10 @@ CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y +@@ -6864,6 +8519,10 @@ CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_HW=y @@ -33572,7 +34450,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set # CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set -@@ -6871,6 +8525,7 @@ CONFIG_CRYPTO_HW=y +@@ -6871,6 +8530,7 @@ CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_QAT_C3XXX is not set # CONFIG_CRYPTO_DEV_QAT_C62X is not set # CONFIG_CRYPTO_DEV_QAT_4XXX is not set @@ -33580,7 +34458,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set # CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set # CONFIG_CRYPTO_DEV_QAT_C62XVF is not set -@@ -6933,16 +8588,16 @@ CONFIG_GENERIC_PCI_IOMAP=y +@@ -6933,16 +8593,16 @@ CONFIG_GENERIC_PCI_IOMAP=y # CONFIG_CRYPTO_LIB_UTILS=y CONFIG_CRYPTO_LIB_AES=y @@ -33602,7 +34480,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_CRYPTO_LIB_POLY1305 is not set # CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set CONFIG_CRYPTO_LIB_SHA1=y -@@ -7011,8 +8666,12 @@ CONFIG_HAS_IOMEM=y +@@ -7011,8 +8671,12 @@ CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y @@ -33615,7 +34493,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_DMA_DECLARE_COHERENT=y CONFIG_ARCH_HAS_SETUP_DMA_OPS=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y -@@ -7032,7 +8691,7 @@ CONFIG_DMA_CMA=y +@@ -7032,7 +8696,7 @@ CONFIG_DMA_CMA=y # # Default contiguous memory area size: # @@ -33624,7 +34502,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set # CONFIG_CMA_SIZE_SEL_MIN is not set -@@ -7043,7 +8702,6 @@ CONFIG_DMA_MAP_BENCHMARK=y +@@ -7043,7 +8707,6 @@ CONFIG_DMA_MAP_BENCHMARK=y CONFIG_SGL_ALLOC=y CONFIG_CHECK_SIGNATURE=y # CONFIG_CPUMASK_OFFSTACK is not set @@ -33632,7 +34510,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_CPU_RMAP=y CONFIG_DQL=y CONFIG_GLOB=y -@@ -7113,6 +8771,8 @@ CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +@@ -7113,6 +8776,8 @@ CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y # CONFIG_DEBUG_INFO_REDUCED is not set CONFIG_DEBUG_INFO_COMPRESSED_NONE=y # CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set @@ -33641,7 +34519,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_DEBUG_INFO_BTF=y CONFIG_PAHOLE_HAS_SPLIT_BTF=y CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y -@@ -7179,7 +8839,6 @@ CONFIG_SLUB_DEBUG=y +@@ -7179,7 +8844,6 @@ CONFIG_SLUB_DEBUG=y # CONFIG_PAGE_TABLE_CHECK is not set # CONFIG_PAGE_POISONING is not set # CONFIG_DEBUG_PAGE_REF is not set @@ -33649,7 +34527,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_ARCH_HAS_DEBUG_WX=y # CONFIG_DEBUG_WX is not set CONFIG_GENERIC_PTDUMP=y -@@ -7257,7 +8916,7 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y +@@ -7257,7 +8921,7 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y # CONFIG_DEBUG_LOCK_ALLOC is not set CONFIG_DEBUG_ATOMIC_SLEEP=y # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set @@ -33658,7 +34536,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_WW_MUTEX_SELFTEST is not set # CONFIG_SCF_TORTURE_TEST is not set # CONFIG_CSD_LOCK_WAIT_DEBUG is not set -@@ -7281,8 +8940,9 @@ CONFIG_DEBUG_LIST=y +@@ -7281,8 +8945,9 @@ CONFIG_DEBUG_LIST=y # # RCU Debugging # @@ -33669,7 +34547,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_RCU_REF_SCALE_TEST is not set CONFIG_RCU_CPU_STALL_TIMEOUT=60 CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 -@@ -7346,6 +9006,7 @@ CONFIG_FTRACE_MCOUNT_RECORD=y +@@ -7346,6 +9011,7 @@ CONFIG_FTRACE_MCOUNT_RECORD=y CONFIG_FTRACE_MCOUNT_USE_RECORDMCOUNT=y CONFIG_SYNTH_EVENTS=y # CONFIG_USER_EVENTS is not set @@ -33677,7 +34555,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 # CONFIG_TRACE_EVENT_INJECT is not set # CONFIG_TRACEPOINT_BENCHMARK is not set CONFIG_RING_BUFFER_BENCHMARK=m -@@ -7358,7 +9019,38 @@ CONFIG_RING_BUFFER_BENCHMARK=m +@@ -7358,7 +9024,38 @@ CONFIG_RING_BUFFER_BENCHMARK=m # CONFIG_SYNTH_EVENT_GEN_TEST is not set # CONFIG_KPROBE_EVENT_GEN_TEST is not set # CONFIG_RV is not set @@ -33717,7 +34595,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_STRICT_DEVMEM=y CONFIG_IO_STRICT_DEVMEM=y -@@ -7376,7 +9068,47 @@ CONFIG_FUNCTION_ERROR_INJECTION=y +@@ -7376,7 +9073,47 @@ CONFIG_FUNCTION_ERROR_INJECTION=y # CONFIG_FAULT_INJECTION is not set CONFIG_ARCH_HAS_KCOV=y # CONFIG_KCOV is not set @@ -33766,7 +34644,7 @@ index 61f2b2f12589..0f2b22d817e1 100644 CONFIG_ARCH_USE_MEMTEST=y # CONFIG_MEMTEST is not set # end of Kernel Testing and Coverage -@@ -7388,9 +9120,3 @@ CONFIG_ARCH_USE_MEMTEST=y +@@ -7388,9 +9125,3 @@ CONFIG_ARCH_USE_MEMTEST=y # end of Kernel hacking # CONFIG_KWORKER_NUMA_AFFINITY is not set @@ -53436,2500 +54314,3555 @@ index 000000000000..81e9f9eb1b20 +#endif diff --git a/drivers/clk/spacemit/Kconfig b/drivers/clk/spacemit/Kconfig new file mode 100644 -index 000000000000..47cccef86793 +index 000000000000..590556990ead --- /dev/null +++ b/drivers/clk/spacemit/Kconfig -@@ -0,0 +1,9 @@ -+# SPDX-License-Identifier: GPL-2.0 -+# common clock support for SPACEMIT SoC family. +@@ -0,0 +1,25 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++config SPACEMIT_CCU ++ tristate "Clock support for SpacemiT SoCs" ++ depends on SOC_SPACEMIT || COMPILE_TEST ++ select AUXILIARY_BUS ++ select MFD_SYSCON ++ help ++ Say Y to enable clock controller unit support for SpacemiT SoCs. ++ ++if SPACEMIT_CCU + +config SPACEMIT_K1_CCU -+ tristate "Clock support for Spacemit k1 SoC" -+ depends on SOC_SPACEMIT_K1 -+ help -+ Build the driver for Spacemit K1 Clock Driver. ++ tristate "Support for SpacemiT K1 SoC" ++ depends on SOC_SPACEMIT || COMPILE_TEST ++ help ++ Support for clock controller unit in SpacemiT K1 SoC. + ++config SPACEMIT_K3_CCU ++ tristate "Support for SpacemiT K3 SoC" ++ depends on SOC_SPACEMIT || COMPILE_TEST ++ help ++ Support for clock controller unit in SpacemiT K3 SoC. ++ ++endif diff --git a/drivers/clk/spacemit/Makefile b/drivers/clk/spacemit/Makefile new file mode 100644 -index 000000000000..889a5c51bfe6 +index 000000000000..67946f5d0208 --- /dev/null +++ b/drivers/clk/spacemit/Makefile -@@ -0,0 +1,11 @@ +@@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Spacemit Clock specific Makefile +# + -+obj-$(CONFIG_SPACEMIT_K1_CCU) += ccu-spacemit-k1.o -+obj-$(CONFIG_SPACEMIT_K1_CCU) += ccu_mix.o -+obj-$(CONFIG_SPACEMIT_K1_CCU) += ccu_pll.o -+obj-$(CONFIG_SPACEMIT_K1_CCU) += ccu_dpll.o -+obj-$(CONFIG_SPACEMIT_K1_CCU) += ccu_ddn.o -+obj-$(CONFIG_SPACEMIT_K1_CCU) += ccu_ddr.o -diff --git a/drivers/clk/spacemit/ccu-spacemit-k1.c b/drivers/clk/spacemit/ccu-spacemit-k1.c ++obj-$(CONFIG_SPACEMIT_CCU) += ccu_pll.o ccu_mix.o ccu_ddn.o ++obj-$(CONFIG_SPACEMIT_K1_CCU) += ccu-k1.o ++obj-$(CONFIG_SPACEMIT_K3_CCU) += ccu-k3.o ++ +diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c new file mode 100644 -index 000000000000..117ebb97ac27 +index 000000000000..038139a1f8f5 --- /dev/null -+++ b/drivers/clk/spacemit/ccu-spacemit-k1.c -@@ -0,0 +1,2123 @@ ++++ b/drivers/clk/spacemit/ccu-k1.c +@@ -0,0 +1,1195 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* -+ * Spacemit k1 clock controller driver -+ * -+ * Copyright (c) 2023, spacemit Corporation. -+ * ++ * Copyright (c) 2024 SpacemiT Technology Co. Ltd ++ * Copyright (c) 2024-2025 Haylen Chu + */ + ++#include +#include -+#include -+#include ++#include ++#include ++#include +#include -+#include +#include -+#include -+#include "ccu-spacemit-k1.h" -+#include "ccu_mix.h" -+#include "ccu_pll.h" -+#include "ccu_ddn.h" -+#include "ccu_dpll.h" -+#include "ccu_ddr.h" -+ -+DEFINE_SPINLOCK(g_cru_lock); -+ -+/* APBS register offset */ -+/* pll1 */ -+#define APB_SPARE1_REG 0x100 -+#define APB_SPARE2_REG 0x104 -+#define APB_SPARE3_REG 0x108 -+/* pll2 */ -+#define APB_SPARE7_REG 0x118 -+#define APB_SPARE8_REG 0x11c -+#define APB_SPARE9_REG 0x120 -+/* pll3 */ -+#define APB_SPARE10_REG 0x124 -+#define APB_SPARE11_REG 0x128 -+#define APB_SPARE12_REG 0x12c -+/* end of APBS register offset */ -+ -+/* APBC register offset */ -+#define APBC_UART1_CLK_RST 0x0 -+#define APBC_UART2_CLK_RST 0x4 -+#define APBC_GPIO_CLK_RST 0x8 -+#define APBC_PWM0_CLK_RST 0xc -+#define APBC_PWM1_CLK_RST 0x10 -+#define APBC_PWM2_CLK_RST 0x14 -+#define APBC_PWM3_CLK_RST 0x18 -+#define APBC_TWSI8_CLK_RST 0x20 -+#define APBC_UART3_CLK_RST 0x24 -+#define APBC_RTC_CLK_RST 0x28 -+#define APBC_TWSI0_CLK_RST 0x2c -+#define APBC_TWSI1_CLK_RST 0x30 -+#define APBC_TIMERS1_CLK_RST 0x34 -+#define APBC_TWSI2_CLK_RST 0x38 -+#define APBC_AIB_CLK_RST 0x3c -+#define APBC_TWSI4_CLK_RST 0x40 -+#define APBC_TIMERS2_CLK_RST 0x44 -+#define APBC_ONEWIRE_CLK_RST 0x48 -+#define APBC_TWSI5_CLK_RST 0x4c -+#define APBC_DRO_CLK_RST 0x58 -+#define APBC_IR_CLK_RST 0x5c -+#define APBC_TWSI6_CLK_RST 0x60 -+#define APBC_COUNTER_CLK_SEL 0x64 -+ -+#define APBC_TWSI7_CLK_RST 0x68 -+#define APBC_TSEN_CLK_RST 0x6c -+ -+#define APBC_UART4_CLK_RST 0x70 -+#define APBC_UART5_CLK_RST 0x74 -+#define APBC_UART6_CLK_RST 0x78 -+#define APBC_SSP3_CLK_RST 0x7c -+ -+#define APBC_SSPA0_CLK_RST 0x80 -+#define APBC_SSPA1_CLK_RST 0x84 -+ -+#define APBC_IPC_AP2AUD_CLK_RST 0x90 -+#define APBC_UART7_CLK_RST 0x94 -+#define APBC_UART8_CLK_RST 0x98 -+#define APBC_UART9_CLK_RST 0x9c -+ -+#define APBC_CAN0_CLK_RST 0xa0 -+#define APBC_PWM4_CLK_RST 0xa8 -+#define APBC_PWM5_CLK_RST 0xac -+#define APBC_PWM6_CLK_RST 0xb0 -+#define APBC_PWM7_CLK_RST 0xb4 -+#define APBC_PWM8_CLK_RST 0xb8 -+#define APBC_PWM9_CLK_RST 0xbc -+#define APBC_PWM10_CLK_RST 0xc0 -+#define APBC_PWM11_CLK_RST 0xc4 -+#define APBC_PWM12_CLK_RST 0xc8 -+#define APBC_PWM13_CLK_RST 0xcc -+#define APBC_PWM14_CLK_RST 0xd0 -+#define APBC_PWM15_CLK_RST 0xd4 -+#define APBC_PWM16_CLK_RST 0xd8 -+#define APBC_PWM17_CLK_RST 0xdc -+#define APBC_PWM18_CLK_RST 0xe0 -+#define APBC_PWM19_CLK_RST 0xe4 -+/* end of APBC register offset */ -+ -+/* MPMU register offset */ -+#define MPMU_POSR 0x10 -+#define POSR_PLL1_LOCK BIT(27) -+#define POSR_PLL2_LOCK BIT(28) -+#define POSR_PLL3_LOCK BIT(29) -+ -+#define MPMU_VRCR 0x18 -+#define MPMU_VRCR_REQ_EN0 BIT(0) -+#define MPMU_VRCR_REQ_EN2 BIT(2) -+#define MPMU_VRCR_REQ_POL2 BIT(6) -+#define MPMU_VRCR_VCXO_OUT_REQ_EN2 BIT(14) -+ -+#define MPMU_WDTPCR 0x200 -+#define MPMU_RIPCCR 0x210 -+#define MPMU_ACGR 0x1024 -+#define MPMU_SUCCR 0x14 -+#define MPMU_ISCCR 0x44 -+#define MPMU_SUCCR_1 0x10b0 -+#define MPMU_APBCSCR 0x1050 -+ -+/* end of MPMU register offset */ -+ -+/* APMU register offset */ -+#define APMU_JPG_CLK_RES_CTRL 0x20 -+#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x24 -+#define APMU_ISP_CLK_RES_CTRL 0x38 -+#define APMU_LCD_CLK_RES_CTRL1 0x44 -+#define APMU_LCD_SPI_CLK_RES_CTRL 0x48 -+#define APMU_LCD_CLK_RES_CTRL2 0x4c -+#define APMU_CCIC_CLK_RES_CTRL 0x50 -+#define APMU_SDH0_CLK_RES_CTRL 0x54 -+#define APMU_SDH1_CLK_RES_CTRL 0x58 -+#define APMU_USB_CLK_RES_CTRL 0x5c -+#define APMU_QSPI_CLK_RES_CTRL 0x60 -+#define APMU_USB_CLK_RES_CTRL 0x5c -+#define APMU_DMA_CLK_RES_CTRL 0x64 -+#define APMU_AES_CLK_RES_CTRL 0x68 -+#define APMU_VPU_CLK_RES_CTRL 0xa4 -+#define APMU_GPU_CLK_RES_CTRL 0xcc -+#define APMU_SDH2_CLK_RES_CTRL 0xe0 -+#define APMU_PMUA_MC_CTRL 0xe8 -+#define APMU_PMU_CC2_AP 0x100 -+#define APMU_PMUA_EM_CLK_RES_CTRL 0x104 -+ -+#define APMU_AUDIO_CLK_RES_CTRL 0x14c -+#define APMU_HDMI_CLK_RES_CTRL 0x1B8 -+#define APMU_CCI550_CLK_CTRL 0x300 -+#define APMU_ACLK_CLK_CTRL 0x388 -+#define APMU_CPU_C0_CLK_CTRL 0x38C -+#define APMU_CPU_C1_CLK_CTRL 0x390 -+ -+#define APMU_PCIE_CLK_RES_CTRL_0 0x3cc -+#define APMU_PCIE_CLK_RES_CTRL_1 0x3d4 -+#define APMU_PCIE_CLK_RES_CTRL_2 0x3dc -+ -+#define APMU_EMAC0_CLK_RES_CTRL 0x3e4 -+#define APMU_EMAC1_CLK_RES_CTRL 0x3ec -+ -+#define APMU_DFC_AP 0x180 -+#define APMU_DFC_STATUS 0x188 -+ -+#define APMU_DFC_LEVEL0 0x190 -+#define APMU_DFC_LEVEL1 0x194 -+#define APMU_DFC_LEVEL2 0x198 -+#define APMU_DFC_LEVEL3 0x19c -+#define APMU_DFC_LEVEL4 0x1a0 -+#define APMU_DFC_LEVEL5 0x1a4 -+#define APMU_DFC_LEVEL6 0x1a8 -+#define APMU_DFC_LEVEL7 0x1ac -+ -+#define APMU_DPLL1_CLK_CTRL1 0x39c -+#define APMU_DPLL1_CLK_CTRL2 0x3a0 -+#define APMU_DPLL2_CLK_CTRL1 0x3a8 -+#define APMU_DPLL2_CLK_CTRL2 0x3ac -+/* end of APMU register offset */ -+ -+/* APBC2 register offset */ -+#define APBC2_UART1_CLK_RST 0x00 -+#define APBC2_SSP2_CLK_RST 0x04 -+#define APBC2_TWSI3_CLK_RST 0x08 -+#define APBC2_RTC_CLK_RST 0x0c -+#define APBC2_TIMERS0_CLK_RST 0x10 -+#define APBC2_KPC_CLK_RST 0x14 -+#define APBC2_GPIO_CLK_RST 0x1c -+/* end of APBC2 register offset */ -+ -+/* RCPU register offset */ -+#define RCPU_HDMI_CLK_RST 0x2044 -+#define RCPU_CAN_CLK_RST 0x4c -+#define RCPU_I2C0_CLK_RST 0x30 -+ -+#define RCPU_SSP0_CLK_RST 0x28 -+#define RCPU_IR_CLK_RST 0x48 -+#define RCPU_UART0_CLK_RST 0xd8 -+#define RCPU_UART1_CLK_RST 0x3c -+/* end of RCPU register offset */ -+ -+/* RCPU2 register offset */ -+#define RCPU2_PWM0_CLK_RST 0x00 -+#define RCPU2_PWM1_CLK_RST 0x04 -+#define RCPU2_PWM2_CLK_RST 0x08 -+#define RCPU2_PWM3_CLK_RST 0x0c -+#define RCPU2_PWM4_CLK_RST 0x10 -+#define RCPU2_PWM5_CLK_RST 0x14 -+#define RCPU2_PWM6_CLK_RST 0x18 -+#define RCPU2_PWM7_CLK_RST 0x1c -+#define RCPU2_PWM8_CLK_RST 0x20 -+#define RCPU2_PWM9_CLK_RST 0x24 -+/* end of RCPU2 register offset */ -+ -+struct spacemit_k1_clk k1_clock_controller; -+ -+static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = { -+ PLL_RATE(3000000000UL, 0x66, 0xdd, 0x50, 0x00, 0x3f, 0xe00000), -+ PLL_RATE(3200000000UL, 0x67, 0xdd, 0x50, 0x00, 0x43, 0xeaaaab), -+ PLL_RATE(2457600000UL, 0x64, 0xdd, 0x50, 0x00, 0x33, 0x0ccccd), -+ PLL_RATE(2800000000UL, 0x66, 0xdd, 0x50, 0x00, 0x3a, 0x155555), -+}; -+ -+static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = { -+ PLL_RATE(1600000000UL, 0x61, 0xcd, 0x50, 0x00, 0x43, 0xeaaaab), -+ PLL_RATE(1800000000UL, 0x61, 0xcd, 0x50, 0x00, 0x4b, 0x000000), -+ PLL_RATE(2000000000UL, 0x62, 0xdd, 0x50, 0x00, 0x2a, 0xeaaaab), -+ PLL_RATE(3000000000UL, 0x66, 0xdd, 0x50, 0x00, 0x3f, 0xe00000), -+ PLL_RATE(3200000000UL, 0x67, 0xdd, 0x50, 0x00, 0x43, 0xeaaaab), -+ PLL_RATE(2457600000UL, 0x64, 0xdd, 0x50, 0x00, 0x33, 0x0ccccd), -+}; -+ -+static SPACEMIT_CCU_PLL(pll2, "pll2", &pll2_rate_tbl, -+ ARRAY_SIZE(pll2_rate_tbl), -+ BASE_TYPE_APBS, APB_SPARE7_REG, APB_SPARE8_REG, APB_SPARE9_REG, -+ MPMU_POSR, POSR_PLL2_LOCK, 1, -+ CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_PLL(pll3, "pll3", &pll3_rate_tbl, -+ ARRAY_SIZE(pll3_rate_tbl), -+ BASE_TYPE_APBS, APB_SPARE10_REG, APB_SPARE11_REG, APB_SPARE12_REG, -+ MPMU_POSR, POSR_PLL3_LOCK, 1, -+ CLK_IGNORE_UNUSED); -+ -+/* pll1 */ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_d2, "pll1_d2", "pll1_2457p6_vco", -+ BASE_TYPE_APBS, APB_SPARE2_REG, -+ BIT(1), BIT(1), 0x0, -+ 2, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_d3, "pll1_d3", "pll1_2457p6_vco", -+ BASE_TYPE_APBS, APB_SPARE2_REG, -+ BIT(2), BIT(2), 0x0, -+ 3, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_d4, "pll1_d4", "pll1_2457p6_vco", -+ BASE_TYPE_APBS, APB_SPARE2_REG, -+ BIT(3), BIT(3), 0x0, -+ 4, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_d5, "pll1_d5", "pll1_2457p6_vco", -+ BASE_TYPE_APBS, APB_SPARE2_REG, -+ BIT(4), BIT(4), 0x0, -+ 5, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_d6, "pll1_d6", "pll1_2457p6_vco", -+ BASE_TYPE_APBS, APB_SPARE2_REG, -+ BIT(5), BIT(5), 0x0, -+ 6, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_d7, "pll1_d7", "pll1_2457p6_vco", -+ BASE_TYPE_APBS, APB_SPARE2_REG, -+ BIT(6), BIT(6), 0x0, -+ 7, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_d8, "pll1_d8", "pll1_2457p6_vco", -+ BASE_TYPE_APBS, APB_SPARE2_REG, -+ BIT(7), BIT(7), 0x0, -+ 8, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_d11_223p4, "pll1_d11_223p4", -+ "pll1_2457p6_vco", -+ BASE_TYPE_APBS, APB_SPARE2_REG, -+ BIT(15), BIT(15), 0x0, -+ 11, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_d13_189, "pll1_d13_189", -+ "pll1_2457p6_vco", -+ BASE_TYPE_APBS, APB_SPARE2_REG, -+ BIT(16), BIT(16), 0x0, -+ 13, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_d23_106p8, "pll1_d23_106p8", -+ "pll1_2457p6_vco", -+ BASE_TYPE_APBS, APB_SPARE2_REG, -+ BIT(20), BIT(20), 0x0, -+ 23, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_d64_38p4, "pll1_d64_38p4", -+ "pll1_2457p6_vco", -+ BASE_TYPE_APBS, APB_SPARE2_REG, -+ BIT(0), BIT(0), 0x0, -+ 64, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_aud_245p7, "pll1_aud_245p7", -+ "pll1_2457p6_vco", -+ BASE_TYPE_APBS, APB_SPARE2_REG, -+ BIT(10), BIT(10), 0x0, -+ 10, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_aud_24p5, "pll1_aud_24p5", -+ "pll1_2457p6_vco", -+ BASE_TYPE_APBS, APB_SPARE2_REG, -+ BIT(11), BIT(11), 0x0, -+ 100, 1, CLK_IGNORE_UNUSED); -+ -+/* pll2 */ -+static SPACEMIT_CCU_GATE_FACTOR(pll2_d1, "pll2_d1", "pll2", -+ BASE_TYPE_APBS, APB_SPARE8_REG, -+ BIT(0), BIT(0), 0x0, -+ 1, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll2_d2, "pll2_d2", "pll2", -+ BASE_TYPE_APBS, APB_SPARE8_REG, -+ BIT(1), BIT(1), 0x0, -+ 2, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll2_d3, "pll2_d3", "pll2", -+ BASE_TYPE_APBS, APB_SPARE8_REG, -+ BIT(2), BIT(2), 0x0, -+ 3, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll2_d4, "pll2_d4", "pll2", -+ BASE_TYPE_APBS, APB_SPARE8_REG, -+ BIT(3), BIT(3), 0x0, -+ 4, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll2_d5, "pll2_d5", "pll2", -+ BASE_TYPE_APBS, APB_SPARE8_REG, -+ BIT(4), BIT(4), 0x0, -+ 5, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll2_d6, "pll2_d6", "pll2", -+ BASE_TYPE_APBS, APB_SPARE8_REG, -+ BIT(5), BIT(5), 0x0, -+ 6, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll2_d7, "pll2_d7", "pll2", -+ BASE_TYPE_APBS, APB_SPARE8_REG, -+ BIT(6), BIT(6), 0x0, -+ 7, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll2_d8, "pll2_d8", "pll2", -+ BASE_TYPE_APBS, APB_SPARE8_REG, -+ BIT(7), BIT(7), 0x0, -+ 8, 1, CLK_IGNORE_UNUSED); -+ -+/* pll3 */ -+static SPACEMIT_CCU_GATE_FACTOR(pll3_d1, "pll3_d1", "pll3", -+ BASE_TYPE_APBS, APB_SPARE11_REG, -+ BIT(0), BIT(0), 0x0, -+ 1, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll3_d2, "pll3_d2", "pll3", -+ BASE_TYPE_APBS, APB_SPARE11_REG, -+ BIT(1), BIT(1), 0x0, -+ 2, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll3_d3, "pll3_d3", "pll3", -+ BASE_TYPE_APBS, APB_SPARE11_REG, -+ BIT(2), BIT(2), 0x0, -+ 3, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll3_d4, "pll3_d4", "pll3", -+ BASE_TYPE_APBS, APB_SPARE11_REG, -+ BIT(3), BIT(3), 0x0, -+ 4, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll3_d5, "pll3_d5", "pll3", -+ BASE_TYPE_APBS, APB_SPARE11_REG, -+ BIT(4), BIT(4), 0x0, -+ 5, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll3_d6, "pll3_d6", "pll3", -+ BASE_TYPE_APBS, APB_SPARE11_REG, -+ BIT(5), BIT(5), 0x0, -+ 6, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll3_d7, "pll3_d7", "pll3", -+ BASE_TYPE_APBS, APB_SPARE11_REG, -+ BIT(6), BIT(6), 0x0, -+ 7, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll3_d8, "pll3_d8", "pll3", -+ BASE_TYPE_APBS, APB_SPARE11_REG, -+ BIT(7), BIT(7), 0x0, -+ 8, 1, CLK_IGNORE_UNUSED); -+ -+/* pll3_div */ -+static SPACEMIT_CCU_FACTOR(pll3_80, "pll3_80", "pll3_d8", -+ 5, 1); -+ -+static SPACEMIT_CCU_FACTOR(pll3_40, "pll3_40", "pll3_d8", -+ 10, 1); -+ -+static SPACEMIT_CCU_FACTOR(pll3_20, "pll3_20", "pll3_d8", -+ 20, 1); -+ -+/* pll1_d8 */ -+static SPACEMIT_CCU_GATE(pll1_d8_307p2, "pll1_d8_307p2", "pll1_d8", -+ BASE_TYPE_MPMU, MPMU_ACGR, -+ BIT(13), BIT(13), 0x0, -+ CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_FACTOR(pll1_d32_76p8, -+ "pll1_d32_76p8", "pll1_d8_307p2", -+ 4, 1); -+ -+static SPACEMIT_CCU_FACTOR(pll1_d40_61p44, -+ "pll1_d40_61p44", "pll1_d8_307p2", -+ 5, 1); -+ -+static SPACEMIT_CCU_FACTOR(pll1_d16_153p6, -+ "pll1_d16_153p6", "pll1_d8", -+ 2, 1); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_d24_102p4, -+ "pll1_d24_102p4", "pll1_d8", -+ BASE_TYPE_MPMU, MPMU_ACGR, -+ BIT(12), BIT(12), 0x0, -+ 3, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_d48_51p2, -+ "pll1_d48_51p2", "pll1_d8", -+ BASE_TYPE_MPMU, MPMU_ACGR, -+ BIT(7), BIT(7), 0x0, -+ 6, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_d48_51p2_ap, -+ "pll1_d48_51p2_ap", "pll1_d8", -+ BASE_TYPE_MPMU, MPMU_ACGR, -+ BIT(11), BIT(11), 0x0, -+ 6, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_m3d128_57p6, -+ "pll1_m3d128_57p6", "pll1_d8", -+ BASE_TYPE_MPMU, MPMU_ACGR, -+ BIT(8), BIT(8), 0x0, -+ 16, 3, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_d96_25p6, -+ "pll1_d96_25p6", "pll1_d8", -+ BASE_TYPE_MPMU, MPMU_ACGR, -+ BIT(4), BIT(4), 0x0, -+ 12, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_d192_12p8, -+ "pll1_d192_12p8", "pll1_d8", -+ BASE_TYPE_MPMU, MPMU_ACGR, -+ BIT(3), BIT(3), 0x0, -+ 24, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_d192_12p8_wdt, -+ "pll1_d192_12p8_wdt", -+ "pll1_d8", -+ BASE_TYPE_MPMU, MPMU_ACGR, -+ BIT(19), BIT(19), 0x0, -+ 24, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_d384_6p4, -+ "pll1_d384_6p4", "pll1_d8", -+ BASE_TYPE_MPMU, MPMU_ACGR, -+ BIT(2), BIT(2), 0x0, -+ 48, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_FACTOR(pll1_d768_3p2, -+ "pll1_d768_3p2", "pll1_d384_6p4", -+ 2, 1); -+ -+static SPACEMIT_CCU_FACTOR(pll1_d1536_1p6, -+ "pll1_d1536_1p6", "pll1_d384_6p4", -+ 4, 1); -+ -+static SPACEMIT_CCU_FACTOR(pll1_d3072_0p8, -+ "pll1_d3072_0p8", "pll1_d384_6p4", -+ 8, 1); -+ -+/* pll1_d7 */ -+static SPACEMIT_CCU_FACTOR(pll1_d7_351p08, -+ "pll1_d7_351p08", "pll1_d7", -+ 1, 1); -+ -+/* pll1_d6 */ -+static SPACEMIT_CCU_GATE(pll1_d6_409p6, -+ "pll1_d6_409p6", "pll1_d6", -+ BASE_TYPE_MPMU, MPMU_ACGR, -+ BIT(0), BIT(0), 0x0, -+ CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_d12_204p8, -+ "pll1_d12_204p8", "pll1_d6", -+ BASE_TYPE_MPMU, MPMU_ACGR, -+ BIT(5), BIT(5), 0x0, -+ 2, 1, CLK_IGNORE_UNUSED); -+ -+/* pll1_d5 */ -+static SPACEMIT_CCU_GATE(pll1_d5_491p52, -+ "pll1_d5_491p52", "pll1_d5", -+ BASE_TYPE_MPMU, MPMU_ACGR, -+ BIT(21), BIT(21), 0x0, -+ CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_d10_245p76, -+ "pll1_d10_245p76", "pll1_d5", -+ BASE_TYPE_MPMU, MPMU_ACGR, -+ BIT(18), BIT(18), 0x0, -+ 2, 1, CLK_IGNORE_UNUSED); -+ -+/* pll1_d4 */ -+static SPACEMIT_CCU_GATE(pll1_d4_614p4, -+ "pll1_d4_614p4", "pll1_d4", -+ BASE_TYPE_MPMU, MPMU_ACGR, -+ BIT(15), BIT(15), 0x0, -+ CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_d52_47p26, -+ "pll1_d52_47p26", "pll1_d4", -+ BASE_TYPE_MPMU, MPMU_ACGR, -+ BIT(10), BIT(10), 0x0, -+ 13, 1, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_GATE_FACTOR(pll1_d78_31p5, -+ "pll1_d78_31p5", "pll1_d4", -+ BASE_TYPE_MPMU, MPMU_ACGR, -+ BIT(6), BIT(6), 0x0, -+ 39, 2, CLK_IGNORE_UNUSED); -+ -+/* pll1_d3 */ -+static SPACEMIT_CCU_GATE(pll1_d3_819p2, -+ "pll1_d3_819p2", "pll1_d3", -+ BASE_TYPE_MPMU, MPMU_ACGR, -+ BIT(14), BIT(14), 0x0, -+ CLK_IGNORE_UNUSED); -+ -+/* pll1_d2 */ -+static SPACEMIT_CCU_GATE(pll1_d2_1228p8, -+ "pll1_d2_1228p8", "pll1_d2", -+ BASE_TYPE_MPMU, MPMU_ACGR, -+ BIT(16), BIT(16), 0x0, -+ CLK_IGNORE_UNUSED); -+ -+/* dpll */ -+static const struct ccu_dpll_rate_tbl dpll1_rate_tbl[] = { -+ DPLL_RATE(2400000000UL, 0x00, 0x00, 0x20, -+ 0x2a, 0x32, 0x64, 0xdd, 0x50), -+ DPLL_RATE(2400000000UL, 0x00, 0x3b, 0x20, -+ 0x2a, 0x32, 0x64, 0xdd, 0x50), -+}; -+ -+static const struct ccu_dpll_rate_tbl dpll2_rate_tbl[] = { -+ DPLL_RATE(3200000000UL, 0x55, 0x55, 0x3d, -+ 0x2a, 0x43, 0x67, 0xdd, 0x50), -+}; -+ -+static SPACEMIT_CCU_DPLL(dpll1, "dpll1", &dpll1_rate_tbl, -+ ARRAY_SIZE(dpll1_rate_tbl), -+ BASE_TYPE_APMU, APMU_DPLL1_CLK_CTRL1, APMU_DPLL1_CLK_CTRL2, -+ 0, CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_DPLL(dpll2, "dpll2", &dpll2_rate_tbl, -+ ARRAY_SIZE(dpll2_rate_tbl), -+ BASE_TYPE_APMU, APMU_DPLL2_CLK_CTRL1, APMU_DPLL2_CLK_CTRL2, -+ 0, CLK_IGNORE_UNUSED); -+ -+static const char * const dfc_lvl_parents[] = { -+ "dpll2", "dpll1" -+}; -+ -+static SPACEMIT_CCU_DIV_MUX(dfc_lvl0, "dfc_lvl0", -+ dfc_lvl_parents, BASE_TYPE_APMU, APMU_DFC_LEVEL0, -+ 14, 2, 8, 1, 0); -+ -+static SPACEMIT_CCU_DIV_MUX(dfc_lvl1, "dfc_lvl1", -+ dfc_lvl_parents, BASE_TYPE_APMU, APMU_DFC_LEVEL1, -+ 14, 2, 8, 1, 0); -+ -+static SPACEMIT_CCU_DIV_MUX(dfc_lvl2, "dfc_lvl2", -+ dfc_lvl_parents, BASE_TYPE_APMU, APMU_DFC_LEVEL2, -+ 14, 2, 8, 1, 0); -+ -+static SPACEMIT_CCU_DIV_MUX(dfc_lvl3, "dfc_lvl3", -+ dfc_lvl_parents, BASE_TYPE_APMU, APMU_DFC_LEVEL3, -+ 14, 2, 8, 1, 0); -+ -+static SPACEMIT_CCU_DIV_MUX(dfc_lvl4, "dfc_lvl4", -+ dfc_lvl_parents, BASE_TYPE_APMU, APMU_DFC_LEVEL4, -+ 14, 2, 8, 1, 0); -+ -+static SPACEMIT_CCU_DIV_MUX(dfc_lvl5, "dfc_lvl5", -+ dfc_lvl_parents, BASE_TYPE_APMU, APMU_DFC_LEVEL5, -+ 14, 2, 8, 1, 0); -+ -+static SPACEMIT_CCU_DIV_MUX(dfc_lvl6, "dfc_lvl6", -+ dfc_lvl_parents, BASE_TYPE_APMU, APMU_DFC_LEVEL6, -+ 14, 2, 8, 1, 0); -+ -+static SPACEMIT_CCU_DIV_MUX(dfc_lvl7, "dfc_lvl7", -+ dfc_lvl_parents, BASE_TYPE_APMU, APMU_DFC_LEVEL7, -+ 14, 2, 8, 1, 0); -+ -+static const char * const ddr_clk_parents[] = { -+ "dfc_lvl0", "dfc_lvl1", "dfc_lvl2", "dfc_lvl3", -+ "dfc_lvl4", "dfc_lvl5", "dfc_lvl6", "dfc_lvl7" -+}; -+ -+static SPACEMIT_CCU_DDR_FC(ddr, "ddr", ddr_clk_parents, -+ BASE_TYPE_APMU, APMU_DFC_AP, BIT(0), -+ 1, 3, 0); -+ -+static struct ccu_ddn_info uart_ddn_mask_info = { -+ .factor = 2, -+ .num_mask = 0x1fff, -+ .den_mask = 0x1fff, -+ .num_shift = 16, -+ .den_shift = 0, -+}; -+ -+static struct ccu_ddn_tbl slow_uart1_tbl[] = { -+ {.num = 125, .den = 24}, -+}; -+ -+static struct ccu_ddn_tbl slow_uart2_tbl[] = { -+ {.num = 6144, .den = 960}, -+}; -+ -+static SPACEMIT_CCU_GATE_NO_PARENT(slow_uart, -+ "slow_uart", NULL, -+ BASE_TYPE_MPMU, MPMU_ACGR, -+ BIT(1), BIT(1), 0x0, -+ 0); -+ -+static SPACEMIT_CCU_DDN(slow_uart1_14p74, -+ "slow_uart1_14p74", "pll1_d16_153p6", -+ &uart_ddn_mask_info, &slow_uart1_tbl, -+ ARRAY_SIZE(slow_uart1_tbl), -+ BASE_TYPE_MPMU, MPMU_SUCCR, -+ CLK_IGNORE_UNUSED); -+ -+static SPACEMIT_CCU_DDN(slow_uart2_48, -+ "slow_uart2_48", "pll1_d4_614p4", -+ &uart_ddn_mask_info, &slow_uart2_tbl, -+ ARRAY_SIZE(slow_uart2_tbl), -+ BASE_TYPE_MPMU, MPMU_SUCCR_1, -+ CLK_IGNORE_UNUSED); -+ -+static const char * const uart_parent_names[] = { -+ "pll1_m3d128_57p6", "slow_uart1_14p74", "slow_uart2_48" -+}; -+ -+static SPACEMIT_CCU_MUX_GATE(uart1_clk, "uart1_clk", -+ uart_parent_names, BASE_TYPE_APBC, APBC_UART1_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(uart2_clk, "uart2_clk", -+ uart_parent_names, BASE_TYPE_APBC, APBC_UART2_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(uart3_clk, "uart3_clk", -+ uart_parent_names, BASE_TYPE_APBC, APBC_UART3_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(uart4_clk, "uart4_clk", -+ uart_parent_names, BASE_TYPE_APBC, APBC_UART4_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(uart5_clk, "uart5_clk", -+ uart_parent_names, BASE_TYPE_APBC, APBC_UART5_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(uart6_clk, "uart6_clk", -+ uart_parent_names, BASE_TYPE_APBC, APBC_UART6_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(uart7_clk, "uart7_clk", -+ uart_parent_names, BASE_TYPE_APBC, APBC_UART7_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(uart8_clk, "uart8_clk", -+ uart_parent_names, BASE_TYPE_APBC, APBC_UART8_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(uart9_clk, "uart9_clk", -+ uart_parent_names, BASE_TYPE_APBC, APBC_UART9_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_GATE(gpio_clk, "gpio_clk", "vctcxo_24", -+ BASE_TYPE_APBC, APBC_GPIO_CLK_RST, -+ 0x3, 0x3, 0x0, -+ 0); -+ -+static const char * const pwm_parent_names[] = { -+ "pll1_d192_12p8", "clk_32k" -+}; -+ -+static SPACEMIT_CCU_MUX_GATE(pwm0_clk, "pwm0_clk", -+ pwm_parent_names, BASE_TYPE_APBC, APBC_PWM0_CLK_RST, -+ 4, 3, 0x2, 0x2, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(pwm1_clk, "pwm1_clk", -+ pwm_parent_names, BASE_TYPE_APBC, APBC_PWM1_CLK_RST, -+ 4, 3, 0x2, 0x2, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(pwm2_clk, "pwm2_clk", -+ pwm_parent_names, BASE_TYPE_APBC, APBC_PWM2_CLK_RST, -+ 4, 3, 0x2, 0x2, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(pwm3_clk, "pwm3_clk", -+ pwm_parent_names, BASE_TYPE_APBC, APBC_PWM3_CLK_RST, -+ 4, 3, 0x2, 0x2, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(pwm4_clk, "pwm4_clk", -+ pwm_parent_names, BASE_TYPE_APBC, APBC_PWM4_CLK_RST, -+ 4, 3, 0x2, 0x2, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(pwm5_clk, "pwm5_clk", -+ pwm_parent_names, BASE_TYPE_APBC, APBC_PWM5_CLK_RST, -+ 4, 3, 0x2, 0x2, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(pwm6_clk, "pwm6_clk", -+ pwm_parent_names, BASE_TYPE_APBC, APBC_PWM6_CLK_RST, -+ 4, 3, 0x2, 0x2, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(pwm7_clk, "pwm7_clk", -+ pwm_parent_names, BASE_TYPE_APBC, APBC_PWM7_CLK_RST, -+ 4, 3, 0x2, 0x2, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(pwm8_clk, "pwm8_clk", -+ pwm_parent_names, BASE_TYPE_APBC, APBC_PWM8_CLK_RST, -+ 4, 3, 0x2, 0x2, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(pwm9_clk, "pwm9_clk", -+ pwm_parent_names, BASE_TYPE_APBC, APBC_PWM9_CLK_RST, -+ 4, 3, 0x2, 0x2, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(pwm10_clk, "pwm10_clk", -+ pwm_parent_names, BASE_TYPE_APBC, APBC_PWM10_CLK_RST, -+ 4, 3, 0x2, 0x2, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(pwm11_clk, "pwm11_clk", -+ pwm_parent_names, BASE_TYPE_APBC, APBC_PWM11_CLK_RST, -+ 4, 3, 0x2, 0x2, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(pwm12_clk, "pwm12_clk", -+ pwm_parent_names, BASE_TYPE_APBC, APBC_PWM12_CLK_RST, -+ 4, 3, 0x2, 0x2, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(pwm13_clk, "pwm13_clk", -+ pwm_parent_names, BASE_TYPE_APBC, APBC_PWM13_CLK_RST, -+ 4, 3, 0x2, 0x2, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(pwm14_clk, "pwm14_clk", -+ pwm_parent_names, BASE_TYPE_APBC, APBC_PWM14_CLK_RST, -+ 4, 3, 0x2, 0x2, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(pwm15_clk, "pwm15_clk", -+ pwm_parent_names, BASE_TYPE_APBC, APBC_PWM15_CLK_RST, -+ 4, 3, 0x2, 0x2, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(pwm16_clk, "pwm16_clk", -+ pwm_parent_names, BASE_TYPE_APBC, APBC_PWM16_CLK_RST, -+ 4, 3, 0x2, 0x2, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(pwm17_clk, "pwm17_clk", -+ pwm_parent_names, BASE_TYPE_APBC, APBC_PWM17_CLK_RST, -+ 4, 3, 0x2, 0x2, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(pwm18_clk, "pwm18_clk", -+ pwm_parent_names, BASE_TYPE_APBC, APBC_PWM18_CLK_RST, -+ 4, 3, 0x2, 0x2, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(pwm19_clk, "pwm19_clk", -+ pwm_parent_names, BASE_TYPE_APBC, APBC_PWM19_CLK_RST, -+ 4, 3, 0x2, 0x2, 0x0, -+ 0); -+ -+static const char * const ssp_parent_names[] = { -+ "pll1_d384_6p4", "pll1_d192_12p8", "pll1_d96_25p6", -+ "pll1_d48_51p2", "pll1_d768_3p2", "pll1_d1536_1p6", -+ "pll1_d3072_0p8" -+}; -+ -+static SPACEMIT_CCU_MUX_GATE(ssp3_clk, -+ "ssp3_clk", ssp_parent_names, -+ BASE_TYPE_APBC, APBC_SSP3_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_GATE(rtc_clk, "rtc_clk", "clk_32k", -+ BASE_TYPE_APBC, APBC_RTC_CLK_RST, -+ 0x83, 0x83, 0x0, 0); -+ -+static const char * const twsi_parent_names[] = { -+ "pll1_d78_31p5", "pll1_d48_51p2", "pll1_d40_61p44" -+}; -+ -+static SPACEMIT_CCU_MUX_GATE(twsi0_clk, "twsi0_clk", -+ twsi_parent_names, BASE_TYPE_APBC, APBC_TWSI0_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(twsi1_clk, "twsi1_clk", -+ twsi_parent_names, BASE_TYPE_APBC, APBC_TWSI1_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(twsi2_clk, "twsi2_clk", -+ twsi_parent_names, BASE_TYPE_APBC, APBC_TWSI2_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(twsi4_clk, "twsi4_clk", -+ twsi_parent_names, BASE_TYPE_APBC, APBC_TWSI4_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(twsi5_clk, "twsi5_clk", -+ twsi_parent_names, BASE_TYPE_APBC, APBC_TWSI5_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(twsi6_clk, "twsi6_clk", -+ twsi_parent_names, BASE_TYPE_APBC, APBC_TWSI6_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(twsi7_clk, "twsi7_clk", -+ twsi_parent_names, BASE_TYPE_APBC, APBC_TWSI7_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(twsi8_clk, "twsi8_clk", -+ twsi_parent_names, BASE_TYPE_APBC, APBC_TWSI8_CLK_RST, -+ 4, 3, 0x7, 0x3, 0x4, -+ 0); -+ -+static const char * const timer_parent_names[] = { -+ "pll1_d192_12p8", "clk_32k", "pll1_d384_6p4", -+ "vctcxo_3", "vctcxo_1" -+}; -+ -+static SPACEMIT_CCU_MUX_GATE(timers1_clk, "timers1_clk", -+ timer_parent_names, BASE_TYPE_APBC, APBC_TIMERS1_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(timers2_clk, -+ "timers2_clk", timer_parent_names, -+ BASE_TYPE_APBC, APBC_TIMERS2_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_GATE(aib_clk, "aib_clk", "vctcxo_24", -+ BASE_TYPE_APBC, APBC_AIB_CLK_RST, -+ 0x3, 0x3, 0x0, 0); -+ -+static SPACEMIT_CCU_GATE_NO_PARENT(onewire_clk, -+ "onewire_clk", NULL, -+ BASE_TYPE_APBC, APBC_ONEWIRE_CLK_RST, -+ 0x3, 0x3, 0x0, 0); -+ -+static SPACEMIT_CCU_GATE_FACTOR(i2s_sysclk, -+ "i2s_sysclk", "pll1_d8_307p2", -+ BASE_TYPE_MPMU, MPMU_ISCCR, -+ BIT(31), BIT(31), 0x0, -+ 200, 1, 0); -+ -+static SPACEMIT_CCU_GATE_FACTOR(i2s_bclk, -+ "i2s_bclk", "i2s_sysclk", -+ BASE_TYPE_MPMU, MPMU_ISCCR, -+ BIT(29), BIT(29), 0x0, -+ 1, 1, 0); -+ -+static const char * const sspa_parent_names[] = { -+ "pll1_d384_6p4", "pll1_d192_12p8", "pll1_d96_25p6", -+ "pll1_d48_51p2", "pll1_d768_3p2", "pll1_d1536_1p6", -+ "pll1_d3072_0p8", "i2s_bclk" -+}; -+ -+static SPACEMIT_CCU_MUX_GATE(sspa0_clk, "sspa0_clk", sspa_parent_names, -+ BASE_TYPE_APBC, APBC_SSPA0_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_MUX_GATE(sspa1_clk, "sspa1_clk", sspa_parent_names, -+ BASE_TYPE_APBC, APBC_SSPA1_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_GATE_NO_PARENT(dro_clk, "dro_clk", NULL, -+ BASE_TYPE_APBC, APBC_DRO_CLK_RST, -+ 0x1, 0x1, 0x0, 0); -+ -+static SPACEMIT_CCU_GATE_NO_PARENT(ir_clk, "ir_clk", NULL, -+ BASE_TYPE_APBC, APBC_IR_CLK_RST, -+ 0x1, 0x1, 0x0, 0); -+ -+static SPACEMIT_CCU_GATE_NO_PARENT(tsen_clk, "tsen_clk", NULL, -+ BASE_TYPE_APBC, APBC_TSEN_CLK_RST, -+ 0x3, 0x3, 0x0, 0); -+ -+static SPACEMIT_CCU_GATE_NO_PARENT(ipc_ap2aud_clk, "ipc_ap2aud_clk", -+ NULL, BASE_TYPE_APBC, APBC_IPC_AP2AUD_CLK_RST, -+ 0x3, 0x3, 0x0, 0); -+ -+static const char * const can_parent_names[] = { -+ "pll3_20", "pll3_40", "pll3_80" -+}; -+ -+static SPACEMIT_CCU_MUX_GATE(can0_clk, "can0_clk", can_parent_names, -+ BASE_TYPE_APBC, APBC_CAN0_CLK_RST, -+ 4, 3, BIT(1), BIT(1), 0x0, -+ 0); -+ -+static SPACEMIT_CCU_GATE_NO_PARENT(can0_bus_clk, "can0_bus_clk", NULL, -+ BASE_TYPE_APBC, APBC_CAN0_CLK_RST, -+ BIT(0), BIT(0), 0x0, 0); -+ -+static SPACEMIT_CCU_GATE(wdt_clk, "wdt_clk", "pll1_d96_25p6", -+ BASE_TYPE_MPMU, MPMU_WDTPCR, -+ 0x3, 0x3, 0x0, 0); -+ -+static SPACEMIT_CCU_GATE_NO_PARENT(ripc_clk, "ripc_clk", NULL, -+ BASE_TYPE_MPMU, MPMU_RIPCCR, -+ 0x3, 0x3, 0x0, 0); -+ -+static const char * const jpg_parent_names[] = { -+ "pll1_d4_614p4", "pll1_d6_409p6", "pll1_d5_491p52", -+ "pll1_d3_819p2", "pll1_d2_1228p8", "pll2_d4", "pll2_d3" -+}; -+ -+static SPACEMIT_CCU_DIV_FC_MUX_GATE(jpg_clk, "jpg_clk", -+ jpg_parent_names, BASE_TYPE_APMU, APMU_JPG_CLK_RES_CTRL, -+ 5, 3, BIT(15), -+ 2, 3, BIT(1), BIT(1), 0x0, -+ 0); -+ -+static SPACEMIT_CCU_GATE_NO_PARENT(jpg_4kafbc_clk, "jpg_4kafbc_clk", -+ NULL, BASE_TYPE_APMU, APMU_JPG_CLK_RES_CTRL, -+ BIT(16), BIT(16), 0x0, 0); -+ -+static SPACEMIT_CCU_GATE_NO_PARENT(jpg_2kafbc_clk, "jpg_2kafbc_clk", -+ NULL, BASE_TYPE_APMU, APMU_JPG_CLK_RES_CTRL, -+ BIT(17), BIT(17), 0x0, 0); -+ -+static const char * const ccic2phy_parent_names[] = { -+ "pll1_d24_102p4", "pll1_d48_51p2_ap" -+}; -+ -+static SPACEMIT_CCU_MUX_GATE(ccic2phy_clk, "ccic2phy_clk", -+ ccic2phy_parent_names, -+ BASE_TYPE_APMU, APMU_CSI_CCIC2_CLK_RES_CTRL, -+ 7, 1, BIT(5), BIT(5), 0x0, -+ 0); -+ -+static const char * const ccic3phy_parent_names[] = { -+ "pll1_d24_102p4", "pll1_d48_51p2_ap" -+}; -+ -+static SPACEMIT_CCU_MUX_GATE(ccic3phy_clk, "ccic3phy_clk", -+ ccic3phy_parent_names, -+ BASE_TYPE_APMU, APMU_CSI_CCIC2_CLK_RES_CTRL, -+ 31, 1, BIT(30), BIT(30), 0x0, 0); -+ -+static const char * const csi_parent_names[] = { -+ "pll1_d5_491p52", "pll1_d6_409p6", "pll1_d4_614p4", -+ "pll1_d3_819p2", "pll2_d2", "pll2_d3", "pll2_d4", -+ "pll1_d2_1228p8" -+}; -+ -+static SPACEMIT_CCU_DIV_FC_MUX_GATE(csi_clk, "csi_clk", -+ csi_parent_names, BASE_TYPE_APMU, APMU_CSI_CCIC2_CLK_RES_CTRL, -+ 20, 3, BIT(15), -+ 16, 3, BIT(4), BIT(4), 0x0, -+ 0); -+ -+static const char * const camm_parent_names[] = { -+ "pll1_d8_307p2", "pll2_d5", "pll1_d6_409p6", "vctcxo_24" -+}; -+ -+static SPACEMIT_CCU_DIV_MUX_GATE(camm0_clk, "camm0_clk", -+ camm_parent_names, BASE_TYPE_APMU, APMU_CSI_CCIC2_CLK_RES_CTRL, -+ 23, 4, 8, 2, -+ BIT(28), BIT(28), 0x0, -+ 0); -+ -+static SPACEMIT_CCU_DIV_MUX_GATE(camm1_clk, "camm1_clk", -+ camm_parent_names, BASE_TYPE_APMU, APMU_CSI_CCIC2_CLK_RES_CTRL, -+ 23, 4, 8, 2, -+ BIT(6), BIT(6), 0x0, -+ 0); -+ -+static SPACEMIT_CCU_DIV_MUX_GATE(camm2_clk, "camm2_clk", -+ camm_parent_names, BASE_TYPE_APMU, APMU_CSI_CCIC2_CLK_RES_CTRL, -+ 23, 4, 8, 2, -+ BIT(3), BIT(3), 0x0, -+ 0); -+ -+static const char * const isp_cpp_parent_names[] = { -+ "pll1_d8_307p2", "pll1_d6_409p6" -+}; ++#include ++#include + -+static SPACEMIT_CCU_DIV_MUX_GATE(isp_cpp_clk, "isp_cpp_clk", -+ isp_cpp_parent_names, -+ BASE_TYPE_APMU, APMU_ISP_CLK_RES_CTRL, -+ 24, 2, 26, 1, -+ BIT(28), BIT(28), 0x0, -+ 0); + -+static const char * const isp_bus_parent_names[] = { -+ "pll1_d6_409p6", "pll1_d5_491p52", "pll1_d8_307p2", -+ "pll1_d10_245p76" -+}; ++#include "ccu_common.h" ++#include "ccu_pll.h" ++#include "ccu_mix.h" ++#include "ccu_ddn.h" + -+static SPACEMIT_CCU_DIV_FC_MUX_GATE(isp_bus_clk, "isp_bus_clk", -+ isp_bus_parent_names, -+ BASE_TYPE_APMU, APMU_ISP_CLK_RES_CTRL, -+ 18, 3, BIT(23), -+ 21, 2, BIT(17), BIT(17), 0x0, -+ 0); ++#include + -+static const char * const isp_parent_names[] = { -+ "pll1_d6_409p6", "pll1_d5_491p52", "pll1_d4_614p4", -+ "pll1_d8_307p2" ++struct spacemit_ccu_data { ++ const char *reset_name; ++ struct clk_hw **hws; ++ size_t num; +}; + -+static SPACEMIT_CCU_DIV_FC_MUX_GATE(isp_clk, "isp_clk", -+ isp_parent_names, BASE_TYPE_APMU, APMU_ISP_CLK_RES_CTRL, -+ 4, 3, BIT(7), -+ 8, 2, BIT(1), BIT(1), 0x0, -+ 0); ++/* APBS clocks start, APBS region contains and only contains all PLL clocks */ + -+static const char * const dpumclk_parent_names[] = { -+ "pll1_d6_409p6", "pll1_d5_491p52", "pll1_d4_614p4", -+ "pll1_d8_307p2" ++/* ++ * PLL{1,2} must run at fixed frequencies to provide clocks in correct rates for ++ * peripherals. ++ */ ++static const struct ccu_pll_rate_tbl pll1_rate_tbl[] = { ++ CCU_PLL_RATE(2457600000UL, 0x0050dd64, 0x330ccccd), +}; + -+static SPACEMIT_CCU_DIV2_FC_MUX_GATE(dpu_mclk, "dpu_mclk", -+ dpumclk_parent_names, BASE_TYPE_APMU, -+ APMU_LCD_CLK_RES_CTRL1, APMU_LCD_CLK_RES_CTRL2, -+ 1, 4, BIT(29), -+ 5, 3, BIT(0), BIT(0), 0x0, -+ 0); -+ -+static const char * const dpuesc_parent_names[] = { -+ "pll1_d48_51p2_ap", "pll1_d52_47p26", "pll1_d96_25p6", -+ "pll1_d32_76p8" ++static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = { ++ CCU_PLL_RATE(3000000000UL, 0x0050dd66, 0x3fe00000), +}; + -+static SPACEMIT_CCU_MUX_GATE(dpu_esc_clk, "dpu_esc_clk", dpuesc_parent_names, -+ BASE_TYPE_APMU, APMU_LCD_CLK_RES_CTRL1, -+ 0, 2, BIT(2), BIT(2), 0x0, -+ 0); -+ -+static const char * const dpubit_parent_names[] = { -+ "pll1_d3_819p2", "pll2_d2", "pll2_d3", "pll1_d2_1228p8", -+ "pll2_d4", "pll2_d5", "pll2_d8", "pll2_d8" -+}; ++static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = { ++ CCU_PLL_RATE(1600000000UL, 0x0050cd61, 0x43eaaaab), ++ CCU_PLL_RATE(1800000000UL, 0x0050cd61, 0x4b000000), ++ CCU_PLL_RATE(2000000000UL, 0x0050dd62, 0x2aeaaaab), ++ CCU_PLL_RATE(2457600000UL, 0x0050dd64, 0x330ccccd), ++ CCU_PLL_RATE(3000000000UL, 0x0050dd66, 0x3fe00000), ++ CCU_PLL_RATE(3200000000UL, 0x0050dd67, 0x43eaaaab), ++}; ++ ++CCU_PLL_DEFINE(pll1, pll1_rate_tbl, APBS_PLL1_SWCR1, APBS_PLL1_SWCR3, MPMU_POSR, POSR_PLL1_LOCK, ++ CLK_SET_RATE_GATE); ++CCU_PLL_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR3, MPMU_POSR, POSR_PLL2_LOCK, ++ CLK_SET_RATE_GATE); ++CCU_PLL_DEFINE(pll3, pll3_rate_tbl, APBS_PLL3_SWCR1, APBS_PLL3_SWCR3, MPMU_POSR, POSR_PLL3_LOCK, ++ CLK_SET_RATE_GATE); ++ ++CCU_FACTOR_GATE_DEFINE(pll1_d2, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d3, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d6, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_FLAGS_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(7), 8, 1, ++ CLK_IS_CRITICAL); ++CCU_FACTOR_GATE_DEFINE(pll1_d11_223p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(15), 11, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d13_189, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(16), 13, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d23_106p8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(20), 23, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d64_38p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(0), 64, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_aud_245p7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(10), 10, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_aud_24p5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(11), 100, 1); + -+static SPACEMIT_CCU_DIV_FC_MUX_GATE(dpu_bit_clk, "dpu_bit_clk", -+ dpubit_parent_names, -+ BASE_TYPE_APMU, APMU_LCD_CLK_RES_CTRL1, -+ 17, 3, BIT(31), -+ 20, 3, BIT(16), BIT(16), 0x0, -+ 0); ++CCU_FACTOR_GATE_DEFINE(pll2_d1, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d2, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d3, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d4, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d5, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d6, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d7, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d8, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(7), 8, 1); + -+static const char * const dpupx_parent_names[] = { -+ "pll1_d6_409p6", "pll1_d5_491p52", "pll1_d4_614p4", -+ "pll1_d8_307p2", "pll2_d7", "pll2_d8" -+}; -+ -+static SPACEMIT_CCU_DIV2_FC_MUX_GATE(dpu_pxclk, "dpu_pxclk", dpupx_parent_names, -+ BASE_TYPE_APMU, APMU_LCD_CLK_RES_CTRL1, APMU_LCD_CLK_RES_CTRL2, -+ 17, 4, BIT(30), -+ 21, 3, BIT(16), BIT(16), 0x0, -+ 0); -+ -+static SPACEMIT_CCU_GATE_NO_PARENT(dpu_hclk, "dpu_hclk", NULL, -+ BASE_TYPE_APMU, APMU_LCD_CLK_RES_CTRL1, -+ BIT(5), BIT(5), 0x0, -+ 0); -+ -+static const char * const dpu_spi_parent_names[] = { -+ "pll1_d8_307p2", "pll1_d6_409p6", "pll1_d10_245p76", -+ "pll1_d11_223p4", "pll1_d13_189", "pll1_d23_106p8", -+ "pll2_d3", "pll2_d5" -+}; -+ -+static SPACEMIT_CCU_DIV_FC_MUX_GATE(dpu_spi_clk, "dpu_spi_clk", -+ dpu_spi_parent_names, -+ BASE_TYPE_APMU, APMU_LCD_SPI_CLK_RES_CTRL, -+ 8, 3, BIT(7), -+ 12, 3, BIT(1), BIT(1), 0x0, -+ 0); -+ -+static SPACEMIT_CCU_GATE_NO_PARENT(dpu_spi_hbus_clk, "dpu_spi_hbus_clk", NULL, -+ BASE_TYPE_APMU, APMU_LCD_SPI_CLK_RES_CTRL, -+ BIT(3), BIT(3), 0x0, -+ 0); ++CCU_FACTOR_GATE_DEFINE(pll3_d1, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d2, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d3, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d4, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d5, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d6, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d7, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d8, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(7), 8, 1); ++ ++CCU_FACTOR_DEFINE(pll3_20, CCU_PARENT_HW(pll3_d8), 20, 1); ++CCU_FACTOR_DEFINE(pll3_40, CCU_PARENT_HW(pll3_d8), 10, 1); ++CCU_FACTOR_DEFINE(pll3_80, CCU_PARENT_HW(pll3_d8), 5, 1); ++ ++/* APBS clocks end */ ++ ++/* MPMU clocks start */ ++CCU_GATE_DEFINE(pll1_d8_307p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(13), 0); ++ ++CCU_FACTOR_DEFINE(pll1_d32_76p8, CCU_PARENT_HW(pll1_d8_307p2), 4, 1); ++ ++CCU_FACTOR_DEFINE(pll1_d40_61p44, CCU_PARENT_HW(pll1_d8_307p2), 5, 1); ++ ++CCU_FACTOR_DEFINE(pll1_d16_153p6, CCU_PARENT_HW(pll1_d8), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d24_102p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(12), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(7), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2_ap, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(11), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_m3d128_57p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(8), 16, 3); ++CCU_FACTOR_GATE_DEFINE(pll1_d96_25p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(4), 12, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(3), 24, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8_wdt, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(19), 24, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d384_6p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(2), 48, 1); ++ ++CCU_FACTOR_DEFINE(pll1_d768_3p2, CCU_PARENT_HW(pll1_d384_6p4), 2, 1); ++CCU_FACTOR_DEFINE(pll1_d1536_1p6, CCU_PARENT_HW(pll1_d384_6p4), 4, 1); ++CCU_FACTOR_DEFINE(pll1_d3072_0p8, CCU_PARENT_HW(pll1_d384_6p4), 8, 1); ++ ++CCU_GATE_DEFINE(pll1_d6_409p6, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(0), 0); ++CCU_FACTOR_GATE_DEFINE(pll1_d12_204p8, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(5), 2, 1); ++ ++CCU_GATE_DEFINE(pll1_d5_491p52, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(21), 0); ++CCU_FACTOR_GATE_DEFINE(pll1_d10_245p76, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(18), 2, 1); ++ ++CCU_GATE_DEFINE(pll1_d4_614p4, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(15), 0); ++CCU_FACTOR_GATE_DEFINE(pll1_d52_47p26, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(10), 13, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d78_31p5, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(6), 39, 2); ++ ++CCU_GATE_DEFINE(pll1_d3_819p2, CCU_PARENT_HW(pll1_d3), MPMU_ACGR, BIT(14), 0); ++ ++CCU_GATE_DEFINE(pll1_d2_1228p8, CCU_PARENT_HW(pll1_d2), MPMU_ACGR, BIT(16), 0); ++ ++CCU_GATE_DEFINE(slow_uart, CCU_PARENT_NAME(osc), MPMU_ACGR, BIT(1), CLK_IGNORE_UNUSED); ++CCU_DDN_DEFINE(slow_uart1_14p74, pll1_d16_153p6, MPMU_SUCCR, 16, 13, 0, 13, 2, 0); ++CCU_DDN_DEFINE(slow_uart2_48, pll1_d4_614p4, MPMU_SUCCR_1, 16, 13, 0, 13, 2, 0); ++ ++CCU_GATE_DEFINE(wdt_clk, CCU_PARENT_HW(pll1_d96_25p6), MPMU_WDTPCR, BIT(1), 0); ++ ++CCU_FACTOR_DEFINE(i2s_153p6, CCU_PARENT_HW(pll1_d8_307p2), 2, 1); ++ ++static const struct clk_parent_data i2s_153p6_base_parents[] = { ++ CCU_PARENT_HW(i2s_153p6), ++ CCU_PARENT_HW(pll1_d8_307p2), ++}; ++CCU_MUX_DEFINE(i2s_153p6_base, i2s_153p6_base_parents, MPMU_FCCR, 29, 1, 0); ++ ++static const struct clk_parent_data i2s_sysclk_src_parents[] = { ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(i2s_153p6_base) ++}; ++CCU_MUX_GATE_DEFINE(i2s_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR, 30, 1, BIT(31), 0); ++ ++CCU_DDN_DEFINE(i2s_sysclk, i2s_sysclk_src, MPMU_ISCCR, 0, 15, 15, 12, 1, 0); ++ ++CCU_FACTOR_DEFINE(i2s_bclk_factor, CCU_PARENT_HW(i2s_sysclk), 2, 1); ++/* ++ * Divider of i2s_bclk always implies a 1/2 factor, which is ++ * described by i2s_bclk_factor. ++ */ ++CCU_DIV_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s_bclk_factor), MPMU_ISCCR, 27, 2, BIT(29), 0); ++ ++static const struct clk_parent_data apb_parents[] = { ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d24_102p4), ++}; ++CCU_MUX_DEFINE(apb_clk, apb_parents, MPMU_APBCSCR, 0, 2, 0); ++ ++CCU_GATE_DEFINE(wdt_bus_clk, CCU_PARENT_HW(apb_clk), MPMU_WDTPCR, BIT(0), 0); ++ ++CCU_GATE_DEFINE(ripc_clk, CCU_PARENT_HW(apb_clk), MPMU_RIPCCR, 0x1, 0); ++/* MPMU clocks end */ ++ ++/* APBC clocks start */ ++static const struct clk_parent_data uart_clk_parents[] = { ++ CCU_PARENT_HW(pll1_m3d128_57p6), ++ CCU_PARENT_HW(slow_uart1_14p74), ++ CCU_PARENT_HW(slow_uart2_48), ++}; ++CCU_MUX_GATE_DEFINE(uart0_clk, uart_clk_parents, APBC_UART1_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart2_clk, uart_clk_parents, APBC_UART2_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart3_clk, uart_clk_parents, APBC_UART3_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart4_clk, uart_clk_parents, APBC_UART4_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart5_clk, uart_clk_parents, APBC_UART5_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart6_clk, uart_clk_parents, APBC_UART6_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart7_clk, uart_clk_parents, APBC_UART7_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart8_clk, uart_clk_parents, APBC_UART8_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart9_clk, uart_clk_parents, APBC_UART9_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(gpio_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_GPIO_CLK_RST, BIT(1), 0); ++ ++static const struct clk_parent_data pwm_parents[] = { ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_NAME(osc), ++}; ++CCU_MUX_GATE_DEFINE(pwm0_clk, pwm_parents, APBC_PWM0_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm1_clk, pwm_parents, APBC_PWM1_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm2_clk, pwm_parents, APBC_PWM2_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm3_clk, pwm_parents, APBC_PWM3_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm4_clk, pwm_parents, APBC_PWM4_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm5_clk, pwm_parents, APBC_PWM5_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm6_clk, pwm_parents, APBC_PWM6_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm7_clk, pwm_parents, APBC_PWM7_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm8_clk, pwm_parents, APBC_PWM8_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm9_clk, pwm_parents, APBC_PWM9_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm10_clk, pwm_parents, APBC_PWM10_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm11_clk, pwm_parents, APBC_PWM11_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm12_clk, pwm_parents, APBC_PWM12_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm13_clk, pwm_parents, APBC_PWM13_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm14_clk, pwm_parents, APBC_PWM14_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm15_clk, pwm_parents, APBC_PWM15_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm16_clk, pwm_parents, APBC_PWM16_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm17_clk, pwm_parents, APBC_PWM17_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm18_clk, pwm_parents, APBC_PWM18_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm19_clk, pwm_parents, APBC_PWM19_CLK_RST, 4, 3, BIT(1), 0); ++ ++static const struct clk_parent_data ssp_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++}; ++CCU_MUX_GATE_DEFINE(ssp3_clk, ssp_parents, APBC_SSP3_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(rtc_clk, CCU_PARENT_NAME(osc), APBC_RTC_CLK_RST, ++ BIT(7) | BIT(1), 0); ++ ++static const struct clk_parent_data twsi_parents[] = { ++ CCU_PARENT_HW(pll1_d78_31p5), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d40_61p44), ++}; ++CCU_MUX_GATE_DEFINE(twsi0_clk, twsi_parents, APBC_TWSI0_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi1_clk, twsi_parents, APBC_TWSI1_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi2_clk, twsi_parents, APBC_TWSI2_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi4_clk, twsi_parents, APBC_TWSI4_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi5_clk, twsi_parents, APBC_TWSI5_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi6_clk, twsi_parents, APBC_TWSI6_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi7_clk, twsi_parents, APBC_TWSI7_CLK_RST, 4, 3, BIT(1), 0); ++/* ++ * APBC_TWSI8_CLK_RST has a quirk that reading always results in zero. ++ * Combine functional and bus bits together as a gate to avoid sharing the ++ * write-only register between different clock hardwares. ++ */ ++CCU_GATE_DEFINE(twsi8_clk, CCU_PARENT_HW(pll1_d78_31p5), APBC_TWSI8_CLK_RST, BIT(1) | BIT(0), 0); ++ ++static const struct clk_parent_data timer_parents[] = { ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_NAME(osc), ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_NAME(vctcxo_3m), ++ CCU_PARENT_NAME(vctcxo_1m), ++}; ++CCU_MUX_GATE_DEFINE(timers1_clk, timer_parents, APBC_TIMERS1_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(timers2_clk, timer_parents, APBC_TIMERS2_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(aib_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_AIB_CLK_RST, BIT(1), 0); ++ ++CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK_RST, BIT(1), 0); ++ ++/* ++ * When i2s_bclk is selected as the parent clock of sspa, ++ * the hardware requires bit3 to be set ++ */ ++CCU_GATE_DEFINE(sspa0_i2s_bclk, CCU_PARENT_HW(i2s_bclk), APBC_SSPA0_CLK_RST, BIT(3), 0); ++CCU_GATE_DEFINE(sspa1_i2s_bclk, CCU_PARENT_HW(i2s_bclk), APBC_SSPA1_CLK_RST, BIT(3), 0); ++ ++static const struct clk_parent_data sspa0_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(sspa0_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(sspa0_clk, sspa0_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0); ++ ++static const struct clk_parent_data sspa1_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(sspa1_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(sspa1_clk, sspa1_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(dro_clk, CCU_PARENT_HW(apb_clk), APBC_DRO_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(ir_clk, CCU_PARENT_HW(apb_clk), APBC_IR_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(tsen_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(ipc_ap2aud_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(1), 0); ++ ++static const struct clk_parent_data can_parents[] = { ++ CCU_PARENT_HW(pll3_20), ++ CCU_PARENT_HW(pll3_40), ++ CCU_PARENT_HW(pll3_80), ++}; ++CCU_MUX_GATE_DEFINE(can0_clk, can_parents, APBC_CAN0_CLK_RST, 4, 3, BIT(1), 0); ++CCU_GATE_DEFINE(can0_bus_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_CAN0_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(uart0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART3_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART4_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART5_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART6_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART7_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART8_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART9_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(gpio_bus_clk, CCU_PARENT_HW(apb_clk), APBC_GPIO_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(pwm0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM3_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM4_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM5_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM6_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM7_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM8_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM9_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm10_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM10_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm11_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM11_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm12_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM12_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm13_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM13_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm14_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM14_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm15_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM15_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm16_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM16_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm17_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM17_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm18_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM18_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm19_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM19_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(ssp3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP3_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(rtc_bus_clk, CCU_PARENT_HW(apb_clk), APBC_RTC_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(twsi0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI4_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI5_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI6_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI7_CLK_RST, BIT(0), 0); ++/* Placeholder to workaround quirk of the register */ ++CCU_FACTOR_DEFINE(twsi8_bus_clk, CCU_PARENT_HW(apb_clk), 1, 1); ++ ++CCU_GATE_DEFINE(timers1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(timers2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS2_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(aib_bus_clk, CCU_PARENT_HW(apb_clk), APBC_AIB_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(onewire_bus_clk, CCU_PARENT_HW(apb_clk), APBC_ONEWIRE_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(sspa0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(sspa1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA1_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(tsen_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(ipc_ap2aud_bus_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(0), 0); ++/* APBC clocks end */ ++ ++/* APMU clocks start */ ++static const struct clk_parent_data pmua_aclk_parents[] = { ++ CCU_PARENT_HW(pll1_d10_245p76), ++ CCU_PARENT_HW(pll1_d8_307p2), ++}; ++CCU_MUX_DIV_FC_DEFINE(pmua_aclk, pmua_aclk_parents, APMU_ACLK_CLK_CTRL, 1, 2, BIT(4), 0, 1, 0); ++ ++static const struct clk_parent_data cci550_clk_parents[] = { ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll2_d3), ++}; ++CCU_MUX_DIV_FC_DEFINE(cci550_clk, cci550_clk_parents, APMU_CCI550_CLK_CTRL, 8, 3, BIT(12), 0, 2, ++ CLK_IS_CRITICAL); ++ ++static const struct clk_parent_data cpu_c0_hi_clk_parents[] = { ++ CCU_PARENT_HW(pll3_d2), ++ CCU_PARENT_HW(pll3_d1), ++}; ++CCU_MUX_DEFINE(cpu_c0_hi_clk, cpu_c0_hi_clk_parents, APMU_CPU_C0_CLK_CTRL, 13, 1, 0); ++static const struct clk_parent_data cpu_c0_clk_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll3_d3), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(cpu_c0_hi_clk), ++}; ++CCU_MUX_FC_DEFINE(cpu_c0_core_clk, cpu_c0_clk_parents, APMU_CPU_C0_CLK_CTRL, BIT(12), 0, 3, ++ CLK_IS_CRITICAL); ++CCU_DIV_DEFINE(cpu_c0_ace_clk, CCU_PARENT_HW(cpu_c0_core_clk), APMU_CPU_C0_CLK_CTRL, 6, 3, ++ CLK_IS_CRITICAL); ++CCU_DIV_DEFINE(cpu_c0_tcm_clk, CCU_PARENT_HW(cpu_c0_core_clk), APMU_CPU_C0_CLK_CTRL, 9, 3, ++ CLK_IS_CRITICAL); ++ ++static const struct clk_parent_data cpu_c1_hi_clk_parents[] = { ++ CCU_PARENT_HW(pll3_d2), ++ CCU_PARENT_HW(pll3_d1), ++}; ++CCU_MUX_DEFINE(cpu_c1_hi_clk, cpu_c1_hi_clk_parents, APMU_CPU_C1_CLK_CTRL, 13, 1, 0); ++static const struct clk_parent_data cpu_c1_clk_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll3_d3), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(cpu_c1_hi_clk), ++}; ++CCU_MUX_FC_DEFINE(cpu_c1_core_clk, cpu_c1_clk_parents, APMU_CPU_C1_CLK_CTRL, BIT(12), 0, 3, ++ CLK_IS_CRITICAL); ++CCU_DIV_DEFINE(cpu_c1_ace_clk, CCU_PARENT_HW(cpu_c1_core_clk), APMU_CPU_C1_CLK_CTRL, 6, 3, ++ CLK_IS_CRITICAL); ++ ++static const struct clk_parent_data jpg_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll2_d3), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(jpg_clk, jpg_parents, APMU_JPG_CLK_RES_CTRL, 5, 3, BIT(15), 2, 3, ++ BIT(1), 0); ++ ++static const struct clk_parent_data ccic2phy_parents[] = { ++ CCU_PARENT_HW(pll1_d24_102p4), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++}; ++CCU_MUX_GATE_DEFINE(ccic2phy_clk, ccic2phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 7, 1, BIT(5), 0); ++ ++static const struct clk_parent_data ccic3phy_parents[] = { ++ CCU_PARENT_HW(pll1_d24_102p4), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++}; ++CCU_MUX_GATE_DEFINE(ccic3phy_clk, ccic3phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 31, 1, BIT(30), 0); ++ ++static const struct clk_parent_data csi_parents[] = { ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll2_d2), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(csi_clk, csi_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 20, 3, BIT(15), ++ 16, 3, BIT(4), 0); ++ ++static const struct clk_parent_data camm_parents[] = { ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll2_d5), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_NAME(vctcxo_24m), ++}; ++CCU_MUX_DIV_GATE_DEFINE(camm0_clk, camm_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 23, 4, 8, 2, ++ BIT(28), 0); ++CCU_MUX_DIV_GATE_DEFINE(camm1_clk, camm_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 23, 4, 8, 2, ++ BIT(6), 0); ++CCU_MUX_DIV_GATE_DEFINE(camm2_clk, camm_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 23, 4, 8, 2, ++ BIT(3), 0); ++ ++static const struct clk_parent_data isp_cpp_parents[] = { ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d6_409p6), ++}; ++CCU_MUX_DIV_GATE_DEFINE(isp_cpp_clk, isp_cpp_parents, APMU_ISP_CLK_RES_CTRL, 24, 2, 26, 1, ++ BIT(28), 0); ++static const struct clk_parent_data isp_bus_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d10_245p76), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(isp_bus_clk, isp_bus_parents, APMU_ISP_CLK_RES_CTRL, 18, 3, BIT(23), ++ 21, 2, BIT(17), 0); ++static const struct clk_parent_data isp_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d8_307p2), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(isp_clk, isp_parents, APMU_ISP_CLK_RES_CTRL, 4, 3, BIT(7), 8, 2, ++ BIT(1), 0); ++ ++static const struct clk_parent_data dpumclk_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d8_307p2), ++}; ++CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dpu_mclk, dpumclk_parents, APMU_LCD_CLK_RES_CTRL2, ++ APMU_LCD_CLK_RES_CTRL1, 1, 4, BIT(29), 5, 3, BIT(0), 0); ++ ++static const struct clk_parent_data dpuesc_parents[] = { ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++ CCU_PARENT_HW(pll1_d52_47p26), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d32_76p8), ++}; ++CCU_MUX_GATE_DEFINE(dpu_esc_clk, dpuesc_parents, APMU_LCD_CLK_RES_CTRL1, 0, 2, BIT(2), 0); ++ ++static const struct clk_parent_data dpubit_parents[] = { ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll2_d2), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll2_d5), ++ CCU_PARENT_HW(pll2_d7), ++ CCU_PARENT_HW(pll2_d8), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(dpu_bit_clk, dpubit_parents, APMU_LCD_CLK_RES_CTRL1, 17, 3, BIT(31), ++ 20, 3, BIT(16), 0); ++ ++static const struct clk_parent_data dpupx_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll2_d7), ++ CCU_PARENT_HW(pll2_d8), ++}; ++CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dpu_pxclk, dpupx_parents, APMU_LCD_CLK_RES_CTRL2, ++ APMU_LCD_CLK_RES_CTRL1, 17, 4, BIT(30), 21, 3, BIT(16), 0); ++ ++CCU_GATE_DEFINE(dpu_hclk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_CLK_RES_CTRL1, ++ BIT(5), 0); ++ ++static const struct clk_parent_data dpu_spi_parents[] = { ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d10_245p76), ++ CCU_PARENT_HW(pll1_d11_223p4), ++ CCU_PARENT_HW(pll1_d13_189), ++ CCU_PARENT_HW(pll1_d23_106p8), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll2_d5), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(dpu_spi_clk, dpu_spi_parents, APMU_LCD_SPI_CLK_RES_CTRL, 8, 3, ++ BIT(7), 12, 3, BIT(1), 0); ++CCU_GATE_DEFINE(dpu_spi_hbus_clk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_SPI_CLK_RES_CTRL, BIT(3), 0); ++CCU_GATE_DEFINE(dpu_spi_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_SPI_CLK_RES_CTRL, BIT(5), 0); ++CCU_GATE_DEFINE(dpu_spi_aclk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_SPI_CLK_RES_CTRL, BIT(6), 0); ++ ++static const struct clk_parent_data v2d_parents[] = { ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d4_614p4), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(v2d_clk, v2d_parents, APMU_LCD_CLK_RES_CTRL1, 9, 3, BIT(28), 12, 2, ++ BIT(8), 0); ++ ++static const struct clk_parent_data ccic_4x_parents[] = { ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll2_d2), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(ccic_4x_clk, ccic_4x_parents, APMU_CCIC_CLK_RES_CTRL, 18, 3, ++ BIT(15), 23, 2, BIT(4), 0); ++ ++static const struct clk_parent_data ccic1phy_parents[] = { ++ CCU_PARENT_HW(pll1_d24_102p4), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++}; ++CCU_MUX_GATE_DEFINE(ccic1phy_clk, ccic1phy_parents, APMU_CCIC_CLK_RES_CTRL, 7, 1, BIT(5), 0); ++ ++CCU_GATE_DEFINE(sdh_axi_aclk, CCU_PARENT_HW(pmua_aclk), APMU_SDH0_CLK_RES_CTRL, BIT(3), 0); ++static const struct clk_parent_data sdh01_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll2_d8), ++ CCU_PARENT_HW(pll2_d5), ++ CCU_PARENT_HW(pll1_d11_223p4), ++ CCU_PARENT_HW(pll1_d13_189), ++ CCU_PARENT_HW(pll1_d23_106p8), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(sdh0_clk, sdh01_parents, APMU_SDH0_CLK_RES_CTRL, 8, 3, BIT(11), 5, 3, ++ BIT(4), 0); ++CCU_MUX_DIV_GATE_FC_DEFINE(sdh1_clk, sdh01_parents, APMU_SDH1_CLK_RES_CTRL, 8, 3, BIT(11), 5, 3, ++ BIT(4), 0); ++static const struct clk_parent_data sdh2_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll2_d8), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d11_223p4), ++ CCU_PARENT_HW(pll1_d13_189), ++ CCU_PARENT_HW(pll1_d23_106p8), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(sdh2_clk, sdh2_parents, APMU_SDH2_CLK_RES_CTRL, 8, 3, BIT(11), 5, 3, ++ BIT(4), 0); ++ ++CCU_GATE_DEFINE(usb_axi_clk, CCU_PARENT_HW(pmua_aclk), APMU_USB_CLK_RES_CTRL, BIT(1), 0); ++CCU_GATE_DEFINE(usb_p1_aclk, CCU_PARENT_HW(pmua_aclk), APMU_USB_CLK_RES_CTRL, BIT(5), 0); ++CCU_GATE_DEFINE(usb30_clk, CCU_PARENT_HW(pmua_aclk), APMU_USB_CLK_RES_CTRL, BIT(8), 0); ++ ++static const struct clk_parent_data qspi_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll2_d8), ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d10_245p76), ++ CCU_PARENT_HW(pll1_d11_223p4), ++ CCU_PARENT_HW(pll1_d23_106p8), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d13_189), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(qspi_clk, qspi_parents, APMU_QSPI_CLK_RES_CTRL, 9, 3, BIT(12), 6, 3, ++ BIT(4), 0); ++CCU_GATE_DEFINE(qspi_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_QSPI_CLK_RES_CTRL, BIT(3), 0); ++CCU_GATE_DEFINE(dma_clk, CCU_PARENT_HW(pmua_aclk), APMU_DMA_CLK_RES_CTRL, BIT(3), 0); ++ ++static const struct clk_parent_data aes_parents[] = { ++ CCU_PARENT_HW(pll1_d12_204p8), ++ CCU_PARENT_HW(pll1_d24_102p4), ++}; ++CCU_MUX_GATE_DEFINE(aes_clk, aes_parents, APMU_AES_CLK_RES_CTRL, 6, 1, BIT(5), 0); ++ ++static const struct clk_parent_data vpu_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll3_d6), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll2_d5), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(vpu_clk, vpu_parents, APMU_VPU_CLK_RES_CTRL, 13, 3, BIT(21), 10, 3, ++ BIT(3), 0); ++ ++static const struct clk_parent_data gpu_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll3_d6), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll2_d5), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(gpu_clk, gpu_parents, APMU_GPU_CLK_RES_CTRL, 12, 3, BIT(15), 18, 3, ++ BIT(4), 0); ++ ++static const struct clk_parent_data emmc_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d52_47p26), ++ CCU_PARENT_HW(pll1_d3_819p2), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(emmc_clk, emmc_parents, APMU_PMUA_EM_CLK_RES_CTRL, 8, 3, BIT(11), ++ 6, 2, BIT(4), 0); ++CCU_DIV_GATE_DEFINE(emmc_x_clk, CCU_PARENT_HW(pll1_d2_1228p8), APMU_PMUA_EM_CLK_RES_CTRL, 12, ++ 3, BIT(15), 0); ++ ++static const struct clk_parent_data audio_parents[] = { ++ CCU_PARENT_HW(pll1_aud_245p7), ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d6_409p6), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(audio_clk, audio_parents, APMU_AUDIO_CLK_RES_CTRL, 4, 3, BIT(15), ++ 7, 3, BIT(12), 0); ++ ++static const struct clk_parent_data hdmi_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d8_307p2), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(hdmi_mclk, hdmi_parents, APMU_HDMI_CLK_RES_CTRL, 1, 4, BIT(29), 5, ++ 3, BIT(0), 0); ++ ++CCU_GATE_DEFINE(pcie0_master_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_0, BIT(2), 0); ++CCU_GATE_DEFINE(pcie0_slave_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_0, BIT(1), 0); ++CCU_GATE_DEFINE(pcie0_dbi_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_0, BIT(0), 0); ++ ++CCU_GATE_DEFINE(pcie1_master_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_1, BIT(2), 0); ++CCU_GATE_DEFINE(pcie1_slave_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_1, BIT(1), 0); ++CCU_GATE_DEFINE(pcie1_dbi_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_1, BIT(0), 0); ++ ++CCU_GATE_DEFINE(pcie2_master_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_2, BIT(2), 0); ++CCU_GATE_DEFINE(pcie2_slave_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_2, BIT(1), 0); ++CCU_GATE_DEFINE(pcie2_dbi_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_2, BIT(0), 0); ++ ++CCU_GATE_DEFINE(emac0_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_EMAC0_CLK_RES_CTRL, BIT(0), 0); ++CCU_GATE_DEFINE(emac0_ptp_clk, CCU_PARENT_HW(pll2_d6), APMU_EMAC0_CLK_RES_CTRL, BIT(15), 0); ++CCU_GATE_DEFINE(emac1_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_EMAC1_CLK_RES_CTRL, BIT(0), 0); ++CCU_GATE_DEFINE(emac1_ptp_clk, CCU_PARENT_HW(pll2_d6), APMU_EMAC1_CLK_RES_CTRL, BIT(15), 0); ++ ++CCU_GATE_DEFINE(emmc_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_PMUA_EM_CLK_RES_CTRL, BIT(3), 0); ++/* APMU clocks end */ ++ ++static struct clk_hw *k1_ccu_pll_hws[] = { ++ [CLK_PLL1] = &pll1.common.hw, ++ [CLK_PLL2] = &pll2.common.hw, ++ [CLK_PLL3] = &pll3.common.hw, ++ [CLK_PLL1_D2] = &pll1_d2.common.hw, ++ [CLK_PLL1_D3] = &pll1_d3.common.hw, ++ [CLK_PLL1_D4] = &pll1_d4.common.hw, ++ [CLK_PLL1_D5] = &pll1_d5.common.hw, ++ [CLK_PLL1_D6] = &pll1_d6.common.hw, ++ [CLK_PLL1_D7] = &pll1_d7.common.hw, ++ [CLK_PLL1_D8] = &pll1_d8.common.hw, ++ [CLK_PLL1_D11] = &pll1_d11_223p4.common.hw, ++ [CLK_PLL1_D13] = &pll1_d13_189.common.hw, ++ [CLK_PLL1_D23] = &pll1_d23_106p8.common.hw, ++ [CLK_PLL1_D64] = &pll1_d64_38p4.common.hw, ++ [CLK_PLL1_D10_AUD] = &pll1_aud_245p7.common.hw, ++ [CLK_PLL1_D100_AUD] = &pll1_aud_24p5.common.hw, ++ [CLK_PLL2_D1] = &pll2_d1.common.hw, ++ [CLK_PLL2_D2] = &pll2_d2.common.hw, ++ [CLK_PLL2_D3] = &pll2_d3.common.hw, ++ [CLK_PLL2_D4] = &pll2_d4.common.hw, ++ [CLK_PLL2_D5] = &pll2_d5.common.hw, ++ [CLK_PLL2_D6] = &pll2_d6.common.hw, ++ [CLK_PLL2_D7] = &pll2_d7.common.hw, ++ [CLK_PLL2_D8] = &pll2_d8.common.hw, ++ [CLK_PLL3_D1] = &pll3_d1.common.hw, ++ [CLK_PLL3_D2] = &pll3_d2.common.hw, ++ [CLK_PLL3_D3] = &pll3_d3.common.hw, ++ [CLK_PLL3_D4] = &pll3_d4.common.hw, ++ [CLK_PLL3_D5] = &pll3_d5.common.hw, ++ [CLK_PLL3_D6] = &pll3_d6.common.hw, ++ [CLK_PLL3_D7] = &pll3_d7.common.hw, ++ [CLK_PLL3_D8] = &pll3_d8.common.hw, ++ [CLK_PLL3_80] = &pll3_80.common.hw, ++ [CLK_PLL3_40] = &pll3_40.common.hw, ++ [CLK_PLL3_20] = &pll3_20.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k1_ccu_pll_data = { ++ /* The PLL CCU implements no resets */ ++ .hws = k1_ccu_pll_hws, ++ .num = ARRAY_SIZE(k1_ccu_pll_hws), ++}; ++ ++static struct clk_hw *k1_ccu_mpmu_hws[] = { ++ [CLK_PLL1_307P2] = &pll1_d8_307p2.common.hw, ++ [CLK_PLL1_76P8] = &pll1_d32_76p8.common.hw, ++ [CLK_PLL1_61P44] = &pll1_d40_61p44.common.hw, ++ [CLK_PLL1_153P6] = &pll1_d16_153p6.common.hw, ++ [CLK_PLL1_102P4] = &pll1_d24_102p4.common.hw, ++ [CLK_PLL1_51P2] = &pll1_d48_51p2.common.hw, ++ [CLK_PLL1_51P2_AP] = &pll1_d48_51p2_ap.common.hw, ++ [CLK_PLL1_57P6] = &pll1_m3d128_57p6.common.hw, ++ [CLK_PLL1_25P6] = &pll1_d96_25p6.common.hw, ++ [CLK_PLL1_12P8] = &pll1_d192_12p8.common.hw, ++ [CLK_PLL1_12P8_WDT] = &pll1_d192_12p8_wdt.common.hw, ++ [CLK_PLL1_6P4] = &pll1_d384_6p4.common.hw, ++ [CLK_PLL1_3P2] = &pll1_d768_3p2.common.hw, ++ [CLK_PLL1_1P6] = &pll1_d1536_1p6.common.hw, ++ [CLK_PLL1_0P8] = &pll1_d3072_0p8.common.hw, ++ [CLK_PLL1_409P6] = &pll1_d6_409p6.common.hw, ++ [CLK_PLL1_204P8] = &pll1_d12_204p8.common.hw, ++ [CLK_PLL1_491] = &pll1_d5_491p52.common.hw, ++ [CLK_PLL1_245P76] = &pll1_d10_245p76.common.hw, ++ [CLK_PLL1_614] = &pll1_d4_614p4.common.hw, ++ [CLK_PLL1_47P26] = &pll1_d52_47p26.common.hw, ++ [CLK_PLL1_31P5] = &pll1_d78_31p5.common.hw, ++ [CLK_PLL1_819] = &pll1_d3_819p2.common.hw, ++ [CLK_PLL1_1228] = &pll1_d2_1228p8.common.hw, ++ [CLK_SLOW_UART] = &slow_uart.common.hw, ++ [CLK_SLOW_UART1] = &slow_uart1_14p74.common.hw, ++ [CLK_SLOW_UART2] = &slow_uart2_48.common.hw, ++ [CLK_WDT] = &wdt_clk.common.hw, ++ [CLK_RIPC] = &ripc_clk.common.hw, ++ [CLK_I2S_SYSCLK] = &i2s_sysclk.common.hw, ++ [CLK_I2S_BCLK] = &i2s_bclk.common.hw, ++ [CLK_APB] = &apb_clk.common.hw, ++ [CLK_WDT_BUS] = &wdt_bus_clk.common.hw, ++ [CLK_I2S_153P6] = &i2s_153p6.common.hw, ++ [CLK_I2S_153P6_BASE] = &i2s_153p6_base.common.hw, ++ [CLK_I2S_SYSCLK_SRC] = &i2s_sysclk_src.common.hw, ++ [CLK_I2S_BCLK_FACTOR] = &i2s_bclk_factor.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k1_ccu_mpmu_data = { ++ .reset_name = "mpmu-reset", ++ .hws = k1_ccu_mpmu_hws, ++ .num = ARRAY_SIZE(k1_ccu_mpmu_hws), ++}; ++ ++static struct clk_hw *k1_ccu_apbc_hws[] = { ++ [CLK_UART0] = &uart0_clk.common.hw, ++ [CLK_UART2] = &uart2_clk.common.hw, ++ [CLK_UART3] = &uart3_clk.common.hw, ++ [CLK_UART4] = &uart4_clk.common.hw, ++ [CLK_UART5] = &uart5_clk.common.hw, ++ [CLK_UART6] = &uart6_clk.common.hw, ++ [CLK_UART7] = &uart7_clk.common.hw, ++ [CLK_UART8] = &uart8_clk.common.hw, ++ [CLK_UART9] = &uart9_clk.common.hw, ++ [CLK_GPIO] = &gpio_clk.common.hw, ++ [CLK_PWM0] = &pwm0_clk.common.hw, ++ [CLK_PWM1] = &pwm1_clk.common.hw, ++ [CLK_PWM2] = &pwm2_clk.common.hw, ++ [CLK_PWM3] = &pwm3_clk.common.hw, ++ [CLK_PWM4] = &pwm4_clk.common.hw, ++ [CLK_PWM5] = &pwm5_clk.common.hw, ++ [CLK_PWM6] = &pwm6_clk.common.hw, ++ [CLK_PWM7] = &pwm7_clk.common.hw, ++ [CLK_PWM8] = &pwm8_clk.common.hw, ++ [CLK_PWM9] = &pwm9_clk.common.hw, ++ [CLK_PWM10] = &pwm10_clk.common.hw, ++ [CLK_PWM11] = &pwm11_clk.common.hw, ++ [CLK_PWM12] = &pwm12_clk.common.hw, ++ [CLK_PWM13] = &pwm13_clk.common.hw, ++ [CLK_PWM14] = &pwm14_clk.common.hw, ++ [CLK_PWM15] = &pwm15_clk.common.hw, ++ [CLK_PWM16] = &pwm16_clk.common.hw, ++ [CLK_PWM17] = &pwm17_clk.common.hw, ++ [CLK_PWM18] = &pwm18_clk.common.hw, ++ [CLK_PWM19] = &pwm19_clk.common.hw, ++ [CLK_SSP3] = &ssp3_clk.common.hw, ++ [CLK_RTC] = &rtc_clk.common.hw, ++ [CLK_TWSI0] = &twsi0_clk.common.hw, ++ [CLK_TWSI1] = &twsi1_clk.common.hw, ++ [CLK_TWSI2] = &twsi2_clk.common.hw, ++ [CLK_TWSI4] = &twsi4_clk.common.hw, ++ [CLK_TWSI5] = &twsi5_clk.common.hw, ++ [CLK_TWSI6] = &twsi6_clk.common.hw, ++ [CLK_TWSI7] = &twsi7_clk.common.hw, ++ [CLK_TWSI8] = &twsi8_clk.common.hw, ++ [CLK_TIMERS1] = &timers1_clk.common.hw, ++ [CLK_TIMERS2] = &timers2_clk.common.hw, ++ [CLK_AIB] = &aib_clk.common.hw, ++ [CLK_ONEWIRE] = &onewire_clk.common.hw, ++ [CLK_SSPA0] = &sspa0_clk.common.hw, ++ [CLK_SSPA1] = &sspa1_clk.common.hw, ++ [CLK_DRO] = &dro_clk.common.hw, ++ [CLK_IR] = &ir_clk.common.hw, ++ [CLK_TSEN] = &tsen_clk.common.hw, ++ [CLK_IPC_AP2AUD] = &ipc_ap2aud_clk.common.hw, ++ [CLK_CAN0] = &can0_clk.common.hw, ++ [CLK_CAN0_BUS] = &can0_bus_clk.common.hw, ++ [CLK_UART0_BUS] = &uart0_bus_clk.common.hw, ++ [CLK_UART2_BUS] = &uart2_bus_clk.common.hw, ++ [CLK_UART3_BUS] = &uart3_bus_clk.common.hw, ++ [CLK_UART4_BUS] = &uart4_bus_clk.common.hw, ++ [CLK_UART5_BUS] = &uart5_bus_clk.common.hw, ++ [CLK_UART6_BUS] = &uart6_bus_clk.common.hw, ++ [CLK_UART7_BUS] = &uart7_bus_clk.common.hw, ++ [CLK_UART8_BUS] = &uart8_bus_clk.common.hw, ++ [CLK_UART9_BUS] = &uart9_bus_clk.common.hw, ++ [CLK_GPIO_BUS] = &gpio_bus_clk.common.hw, ++ [CLK_PWM0_BUS] = &pwm0_bus_clk.common.hw, ++ [CLK_PWM1_BUS] = &pwm1_bus_clk.common.hw, ++ [CLK_PWM2_BUS] = &pwm2_bus_clk.common.hw, ++ [CLK_PWM3_BUS] = &pwm3_bus_clk.common.hw, ++ [CLK_PWM4_BUS] = &pwm4_bus_clk.common.hw, ++ [CLK_PWM5_BUS] = &pwm5_bus_clk.common.hw, ++ [CLK_PWM6_BUS] = &pwm6_bus_clk.common.hw, ++ [CLK_PWM7_BUS] = &pwm7_bus_clk.common.hw, ++ [CLK_PWM8_BUS] = &pwm8_bus_clk.common.hw, ++ [CLK_PWM9_BUS] = &pwm9_bus_clk.common.hw, ++ [CLK_PWM10_BUS] = &pwm10_bus_clk.common.hw, ++ [CLK_PWM11_BUS] = &pwm11_bus_clk.common.hw, ++ [CLK_PWM12_BUS] = &pwm12_bus_clk.common.hw, ++ [CLK_PWM13_BUS] = &pwm13_bus_clk.common.hw, ++ [CLK_PWM14_BUS] = &pwm14_bus_clk.common.hw, ++ [CLK_PWM15_BUS] = &pwm15_bus_clk.common.hw, ++ [CLK_PWM16_BUS] = &pwm16_bus_clk.common.hw, ++ [CLK_PWM17_BUS] = &pwm17_bus_clk.common.hw, ++ [CLK_PWM18_BUS] = &pwm18_bus_clk.common.hw, ++ [CLK_PWM19_BUS] = &pwm19_bus_clk.common.hw, ++ [CLK_SSP3_BUS] = &ssp3_bus_clk.common.hw, ++ [CLK_RTC_BUS] = &rtc_bus_clk.common.hw, ++ [CLK_TWSI0_BUS] = &twsi0_bus_clk.common.hw, ++ [CLK_TWSI1_BUS] = &twsi1_bus_clk.common.hw, ++ [CLK_TWSI2_BUS] = &twsi2_bus_clk.common.hw, ++ [CLK_TWSI4_BUS] = &twsi4_bus_clk.common.hw, ++ [CLK_TWSI5_BUS] = &twsi5_bus_clk.common.hw, ++ [CLK_TWSI6_BUS] = &twsi6_bus_clk.common.hw, ++ [CLK_TWSI7_BUS] = &twsi7_bus_clk.common.hw, ++ [CLK_TWSI8_BUS] = &twsi8_bus_clk.common.hw, ++ [CLK_TIMERS1_BUS] = &timers1_bus_clk.common.hw, ++ [CLK_TIMERS2_BUS] = &timers2_bus_clk.common.hw, ++ [CLK_AIB_BUS] = &aib_bus_clk.common.hw, ++ [CLK_ONEWIRE_BUS] = &onewire_bus_clk.common.hw, ++ [CLK_SSPA0_BUS] = &sspa0_bus_clk.common.hw, ++ [CLK_SSPA1_BUS] = &sspa1_bus_clk.common.hw, ++ [CLK_TSEN_BUS] = &tsen_bus_clk.common.hw, ++ [CLK_IPC_AP2AUD_BUS] = &ipc_ap2aud_bus_clk.common.hw, ++ [CLK_SSPA0_I2S_BCLK] = &sspa0_i2s_bclk.common.hw, ++ [CLK_SSPA1_I2S_BCLK] = &sspa1_i2s_bclk.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k1_ccu_apbc_data = { ++ .reset_name = "apbc-reset", ++ .hws = k1_ccu_apbc_hws, ++ .num = ARRAY_SIZE(k1_ccu_apbc_hws), ++}; ++ ++static struct clk_hw *k1_ccu_apmu_hws[] = { ++ [CLK_CCI550] = &cci550_clk.common.hw, ++ [CLK_CPU_C0_HI] = &cpu_c0_hi_clk.common.hw, ++ [CLK_CPU_C0_CORE] = &cpu_c0_core_clk.common.hw, ++ [CLK_CPU_C0_ACE] = &cpu_c0_ace_clk.common.hw, ++ [CLK_CPU_C0_TCM] = &cpu_c0_tcm_clk.common.hw, ++ [CLK_CPU_C1_HI] = &cpu_c1_hi_clk.common.hw, ++ [CLK_CPU_C1_CORE] = &cpu_c1_core_clk.common.hw, ++ [CLK_CPU_C1_ACE] = &cpu_c1_ace_clk.common.hw, ++ [CLK_CCIC_4X] = &ccic_4x_clk.common.hw, ++ [CLK_CCIC1PHY] = &ccic1phy_clk.common.hw, ++ [CLK_SDH_AXI] = &sdh_axi_aclk.common.hw, ++ [CLK_SDH0] = &sdh0_clk.common.hw, ++ [CLK_SDH1] = &sdh1_clk.common.hw, ++ [CLK_SDH2] = &sdh2_clk.common.hw, ++ [CLK_USB_P1] = &usb_p1_aclk.common.hw, ++ [CLK_USB_AXI] = &usb_axi_clk.common.hw, ++ [CLK_USB30] = &usb30_clk.common.hw, ++ [CLK_QSPI] = &qspi_clk.common.hw, ++ [CLK_QSPI_BUS] = &qspi_bus_clk.common.hw, ++ [CLK_DMA] = &dma_clk.common.hw, ++ [CLK_AES] = &aes_clk.common.hw, ++ [CLK_VPU] = &vpu_clk.common.hw, ++ [CLK_GPU] = &gpu_clk.common.hw, ++ [CLK_EMMC] = &emmc_clk.common.hw, ++ [CLK_EMMC_X] = &emmc_x_clk.common.hw, ++ [CLK_AUDIO] = &audio_clk.common.hw, ++ [CLK_HDMI] = &hdmi_mclk.common.hw, ++ [CLK_PMUA_ACLK] = &pmua_aclk.common.hw, ++ [CLK_PCIE0_MASTER] = &pcie0_master_clk.common.hw, ++ [CLK_PCIE0_SLAVE] = &pcie0_slave_clk.common.hw, ++ [CLK_PCIE0_DBI] = &pcie0_dbi_clk.common.hw, ++ [CLK_PCIE1_MASTER] = &pcie1_master_clk.common.hw, ++ [CLK_PCIE1_SLAVE] = &pcie1_slave_clk.common.hw, ++ [CLK_PCIE1_DBI] = &pcie1_dbi_clk.common.hw, ++ [CLK_PCIE2_MASTER] = &pcie2_master_clk.common.hw, ++ [CLK_PCIE2_SLAVE] = &pcie2_slave_clk.common.hw, ++ [CLK_PCIE2_DBI] = &pcie2_dbi_clk.common.hw, ++ [CLK_EMAC0_BUS] = &emac0_bus_clk.common.hw, ++ [CLK_EMAC0_PTP] = &emac0_ptp_clk.common.hw, ++ [CLK_EMAC1_BUS] = &emac1_bus_clk.common.hw, ++ [CLK_EMAC1_PTP] = &emac1_ptp_clk.common.hw, ++ [CLK_JPG] = &jpg_clk.common.hw, ++ [CLK_CCIC2PHY] = &ccic2phy_clk.common.hw, ++ [CLK_CCIC3PHY] = &ccic3phy_clk.common.hw, ++ [CLK_CSI] = &csi_clk.common.hw, ++ [CLK_CAMM0] = &camm0_clk.common.hw, ++ [CLK_CAMM1] = &camm1_clk.common.hw, ++ [CLK_CAMM2] = &camm2_clk.common.hw, ++ [CLK_ISP_CPP] = &isp_cpp_clk.common.hw, ++ [CLK_ISP_BUS] = &isp_bus_clk.common.hw, ++ [CLK_ISP] = &isp_clk.common.hw, ++ [CLK_DPU_MCLK] = &dpu_mclk.common.hw, ++ [CLK_DPU_ESC] = &dpu_esc_clk.common.hw, ++ [CLK_DPU_BIT] = &dpu_bit_clk.common.hw, ++ [CLK_DPU_PXCLK] = &dpu_pxclk.common.hw, ++ [CLK_DPU_HCLK] = &dpu_hclk.common.hw, ++ [CLK_DPU_SPI] = &dpu_spi_clk.common.hw, ++ [CLK_DPU_SPI_HBUS] = &dpu_spi_hbus_clk.common.hw, ++ [CLK_DPU_SPIBUS] = &dpu_spi_bus_clk.common.hw, ++ [CLK_DPU_SPI_ACLK] = &dpu_spi_aclk.common.hw, ++ [CLK_V2D] = &v2d_clk.common.hw, ++ [CLK_EMMC_BUS] = &emmc_bus_clk.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k1_ccu_apmu_data = { ++ .reset_name = "apmu-reset", ++ .hws = k1_ccu_apmu_hws, ++ .num = ARRAY_SIZE(k1_ccu_apmu_hws), ++}; ++ ++static const struct spacemit_ccu_data k1_ccu_rcpu_data = { ++ .reset_name = "rcpu-reset", ++}; ++ ++static const struct spacemit_ccu_data k1_ccu_rcpu2_data = { ++ .reset_name = "rcpu2-reset", ++}; ++ ++static const struct spacemit_ccu_data k1_ccu_apbc2_data = { ++ .reset_name = "apbc2-reset", ++}; ++ ++static int spacemit_ccu_register(struct device *dev, ++ struct regmap *regmap, ++ struct regmap *lock_regmap, ++ const struct spacemit_ccu_data *data) ++{ ++ struct clk_hw_onecell_data *clk_data; ++ int i, ret; + -+static SPACEMIT_CCU_GATE_NO_PARENT(dpu_spi_bus_clk, "dpu_spi_bus_clk", NULL, -+ BASE_TYPE_APMU, APMU_LCD_SPI_CLK_RES_CTRL, -+ BIT(5), BIT(5), 0x0, -+ 0); -+ -+static SPACEMIT_CCU_GATE_NO_PARENT(dpu_spi_aclk, "dpu_spi_aclk", NULL, -+ BASE_TYPE_APMU, APMU_LCD_SPI_CLK_RES_CTRL, -+ BIT(6), BIT(6), 0x0, -+ 0); -+ -+static const char * const v2d_parent_names[] = { -+ "pll1_d5_491p52", "pll1_d6_409p6", "pll1_d8_307p2", -+ "pll1_d4_614p4", -+}; -+ -+static SPACEMIT_CCU_DIV_FC_MUX_GATE(v2d_clk, "v2d_clk", v2d_parent_names, -+ BASE_TYPE_APMU, APMU_LCD_CLK_RES_CTRL1, -+ 9, 3, BIT(28), -+ 12, 2, BIT(8), BIT(8), 0x0, -+ 0); ++ /* Nothing to do if the CCU does not implement any clocks */ ++ if (!data->hws) ++ return 0; + -+static const char * const ccic_4x_parent_names[] = { -+ "pll1_d5_491p52", "pll1_d6_409p6", "pll1_d4_614p4", -+ "pll1_d3_819p2", "pll2_d2", "pll2_d3", "pll2_d4", -+ "pll1_d2_1228p8" -+}; -+ -+static SPACEMIT_CCU_DIV_FC_MUX_GATE(ccic_4x_clk, "ccic_4x_clk", -+ ccic_4x_parent_names, -+ BASE_TYPE_APMU, APMU_CCIC_CLK_RES_CTRL, -+ 18, 3, BIT(15), -+ 23, 2, BIT(4), BIT(4), 0x0, -+ 0); -+ -+static const char * const ccic1phy_parent_names[] = { -+ "pll1_d24_102p4", "pll1_d48_51p2_ap" -+}; -+ -+static SPACEMIT_CCU_MUX_GATE(ccic1phy_clk, "ccic1phy_clk", -+ ccic1phy_parent_names, -+ BASE_TYPE_APMU, APMU_CCIC_CLK_RES_CTRL, -+ 7, 1, BIT(5), BIT(5), 0x0, -+ 0); ++ clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num), ++ GFP_KERNEL); ++ if (!clk_data) ++ return -ENOMEM; + -+static SPACEMIT_CCU_GATE_NO_PARENT(sdh_axi_aclk, "sdh_axi_aclk", NULL, -+ BASE_TYPE_APMU, APMU_SDH0_CLK_RES_CTRL, -+ BIT(3), BIT(3), 0x0, -+ 0); -+ -+static const char * const sdh01_parent_names[] = { -+ "pll1_d6_409p6", "pll1_d4_614p4", "pll2_d8", "pll2_d5", -+ "pll1_d11_223p4", "pll1_d13_189", "pll1_d23_106p8" -+}; ++ clk_data->num = data->num; + -+static SPACEMIT_CCU_DIV_FC_MUX_GATE(sdh0_clk, "sdh0_clk", sdh01_parent_names, -+ BASE_TYPE_APMU, APMU_SDH0_CLK_RES_CTRL, -+ 8, 3, BIT(11), -+ 5, 3, BIT(4), BIT(4), 0x0, -+ 0); -+ -+static SPACEMIT_CCU_DIV_FC_MUX_GATE(sdh1_clk, "sdh1_clk", sdh01_parent_names, -+ BASE_TYPE_APMU, APMU_SDH1_CLK_RES_CTRL, -+ 8, 3, BIT(11), -+ 5, 3, BIT(4), BIT(4), 0x0, -+ 0); -+ -+static const char * const sdh2_parent_names[] = { -+ "pll1_d6_409p6", "pll1_d4_614p4", "pll2_d8", -+ "pll1_d3_819p2", "pll1_d11_223p4", "pll1_d13_189", -+ "pll1_d23_106p8" -+}; -+ -+static SPACEMIT_CCU_DIV_FC_MUX_GATE(sdh2_clk, "sdh2_clk", sdh2_parent_names, -+ BASE_TYPE_APMU, APMU_SDH2_CLK_RES_CTRL, -+ 8, 3, BIT(11), -+ 5, 3, BIT(4), BIT(4), 0x0, -+ 0); -+ -+static SPACEMIT_CCU_GATE_NO_PARENT(usb_axi_clk, "usb_axi_clk", NULL, -+ BASE_TYPE_APMU, APMU_USB_CLK_RES_CTRL, -+ BIT(1), BIT(1), 0x0, -+ 0); -+ -+static SPACEMIT_CCU_GATE_NO_PARENT(usb_p1_aclk, "usb_p1_aclk", NULL, -+ BASE_TYPE_APMU, APMU_USB_CLK_RES_CTRL, -+ BIT(5), BIT(5), 0x0, -+ 0); -+ -+static SPACEMIT_CCU_GATE_NO_PARENT(usb30_clk, "usb30_clk", NULL, -+ BASE_TYPE_APMU, APMU_USB_CLK_RES_CTRL, -+ BIT(8), BIT(8), 0x0, -+ 0); ++ for (i = 0; i < data->num; i++) { ++ struct clk_hw *hw = data->hws[i]; ++ struct ccu_common *common; ++ const char *name; + -+static const char * const qspi_parent_names[] = { -+ "pll1_d6_409p6", "pll2_d8", "pll1_d8_307p2", -+ "pll1_d10_245p76", "pll1_d11_223p4", "pll1_d23_106p8", -+ "pll1_d5_491p52", "pll1_d13_189" -+}; ++ if (!hw) { ++ clk_data->hws[i] = ERR_PTR(-ENOENT); ++ continue; ++ } + -+static SPACEMIT_CCU_DIV_MUX_GATE(qspi_clk, "qspi_clk", qspi_parent_names, -+ BASE_TYPE_APMU, APMU_QSPI_CLK_RES_CTRL, -+ 9, 3, -+ 6, 3, BIT(4), BIT(4), 0x0, -+ 0); ++ name = hw->init->name; + -+static SPACEMIT_CCU_GATE_NO_PARENT(qspi_bus_clk, "qspi_bus_clk", NULL, -+ BASE_TYPE_APMU, APMU_QSPI_CLK_RES_CTRL, -+ BIT(3), BIT(3), 0x0, -+ 0); ++ common = hw_to_ccu_common(hw); ++ common->regmap = regmap; ++ common->lock_regmap = lock_regmap; + -+static SPACEMIT_CCU_GATE_NO_PARENT(dma_clk, "dma_clk", NULL, -+ BASE_TYPE_APMU, APMU_DMA_CLK_RES_CTRL, -+ BIT(3), BIT(3), 0x0, -+ 0); ++ ret = devm_clk_hw_register(dev, hw); ++ if (ret) { ++ dev_err(dev, "Cannot register clock %d - %s\n", ++ i, name); ++ return ret; ++ } + -+static const char * const aes_parent_names[] = { -+ "pll1_d12_204p8", "pll1_d24_102p4" -+}; ++ clk_data->hws[i] = hw; ++ } + -+static SPACEMIT_CCU_MUX_GATE(aes_clk, "aes_clk", aes_parent_names, -+ BASE_TYPE_APMU, APMU_AES_CLK_RES_CTRL, -+ 6, 1, BIT(5), BIT(5), 0x0, -+ 0); ++ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); ++ if (ret) ++ dev_err(dev, "failed to add clock hardware provider (%d)\n", ret); + -+static const char * const vpu_parent_names[] = { -+ "pll1_d4_614p4", "pll1_d5_491p52", "pll1_d3_819p2", -+ "pll1_d6_409p6", "pll3_d6", "pll2_d3", "pll2_d4", "pll2_d5" -+}; ++ return ret; ++} + -+static SPACEMIT_CCU_DIV_FC_MUX_GATE(vpu_clk, "vpu_clk", vpu_parent_names, -+ BASE_TYPE_APMU, APMU_VPU_CLK_RES_CTRL, -+ 13, 3, BIT(21), -+ 10, 3, -+ BIT(3), BIT(3), 0x0, -+ 0); ++static void spacemit_cadev_release(struct device *dev) ++{ ++ struct auxiliary_device *adev = to_auxiliary_dev(dev); + -+static const char * const gpu_parent_names[] = { -+ "pll1_d4_614p4", "pll1_d5_491p52", "pll1_d3_819p2", "pll1_d6_409p6", -+ "pll3_d6", "pll2_d3", "pll2_d4", "pll2_d5" -+}; ++ kfree(to_spacemit_ccu_adev(adev)); ++} + -+static SPACEMIT_CCU_DIV_FC_MUX_GATE(gpu_clk, "gpu_clk", gpu_parent_names, -+ BASE_TYPE_APMU, APMU_GPU_CLK_RES_CTRL, -+ 12, 3, BIT(15), -+ 18, 3, -+ BIT(4), BIT(4), 0x0, -+ 0); ++static void spacemit_adev_unregister(void *data) ++{ ++ struct auxiliary_device *adev = data; + -+static const char * const emmc_parent_names[] = { -+ "pll1_d6_409p6", "pll1_d4_614p4", "pll1_d52_47p26", "pll1_d3_819p2" -+}; ++ auxiliary_device_delete(adev); ++ auxiliary_device_uninit(adev); ++} + -+static SPACEMIT_CCU_DIV_FC_MUX_GATE(emmc_clk, "emmc_clk", emmc_parent_names, -+ BASE_TYPE_APMU, APMU_PMUA_EM_CLK_RES_CTRL, -+ 8, 3, BIT(11), -+ 6, 2, -+ 0x18, 0x18, 0x0, -+ 0); ++static int spacemit_ccu_reset_register(struct device *dev, ++ struct regmap *regmap, ++ const char *reset_name) ++{ ++ struct spacemit_ccu_adev *cadev; ++ struct auxiliary_device *adev; ++ static u32 next_id; ++ int ret; + -+static SPACEMIT_CCU_DIV_GATE(emmc_x_clk, "emmc_x_clk", "pll1_d2_1228p8", -+ BASE_TYPE_APMU, APMU_PMUA_EM_CLK_RES_CTRL, -+ 12, 3, BIT(15), BIT(15), 0x0, -+ 0); ++ /* Nothing to do if the CCU does not implement a reset controller */ ++ if (!reset_name) ++ return 0; + -+static const char * const audio_parent_names[] = { -+ "pll1_aud_245p7", "pll1_d8_307p2", "pll1_d6_409p6" -+}; ++ cadev = devm_kzalloc(dev, sizeof(*cadev), GFP_KERNEL); ++ if (!cadev) ++ return -ENOMEM; ++ cadev->regmap = regmap; + -+static SPACEMIT_CCU_DIV_FC_MUX_GATE(audio_clk, "audio_clk", audio_parent_names, -+ BASE_TYPE_APMU, APMU_AUDIO_CLK_RES_CTRL, -+ 4, 3, BIT(15), -+ 7, 3, -+ BIT(12), BIT(12), 0x0, -+ 0); ++ adev = &cadev->adev; ++ adev->name = reset_name; ++ adev->dev.parent = dev; ++ adev->dev.release = spacemit_cadev_release; ++ adev->dev.of_node = dev->of_node; ++ adev->id = next_id++; + -+static const char * const hdmi_parent_names[] = { -+ "pll1_d6_409p6", "pll1_d5_491p52", "pll1_d4_614p4", "pll1_d8_307p2" -+}; ++ ret = auxiliary_device_init(adev); ++ if (ret) ++ return ret; + -+static SPACEMIT_CCU_DIV_FC_MUX_GATE(hdmi_mclk, "hdmi_mclk", hdmi_parent_names, -+ BASE_TYPE_APMU, APMU_HDMI_CLK_RES_CTRL, -+ 1, 4, BIT(29), -+ 5, 3, -+ BIT(0), BIT(0), 0x0, -+ 0); ++ ret = auxiliary_device_add(adev); ++ if (ret) { ++ auxiliary_device_uninit(adev); ++ return ret; ++ } + -+static const char * const cci550_parent_names[] = { -+ "pll1_d5_491p52", "pll1_d4_614p4", "pll1_d3_819p2", "pll2_d3" -+}; ++ return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev); ++} + -+static SPACEMIT_CCU_DIV_FC_MUX(cci550_clk, "cci550_clk", cci550_parent_names, -+ BASE_TYPE_APMU, APMU_CCI550_CLK_CTRL, -+ 8, 3, BIT(12), -+ 0, 2, -+ 0); ++static int k1_ccu_probe(struct platform_device *pdev) ++{ ++ struct regmap *base_regmap, *lock_regmap = NULL; ++ const struct spacemit_ccu_data *data; ++ struct device *dev = &pdev->dev; ++ int ret; + -+static const char * const pmua_aclk_parent_names[] = { -+ "pll1_d10_245p76", "pll1_d8_307p2" -+}; ++ base_regmap = device_node_to_regmap(dev->of_node); ++ if (IS_ERR(base_regmap)) ++ return dev_err_probe(dev, PTR_ERR(base_regmap), ++ "failed to get regmap\n"); + -+static SPACEMIT_CCU_DIV_FC_MUX(pmua_aclk, "pmua_aclk", pmua_aclk_parent_names, -+ BASE_TYPE_APMU, APMU_ACLK_CLK_CTRL, -+ 1, 2, BIT(4), -+ 0, 1, -+ 0); ++ /* ++ * The lock status of PLLs locate in MPMU region, while PLLs themselves ++ * are in APBS region. Reference to MPMU syscon is required to check PLL ++ * status. ++ */ ++ if (of_device_is_compatible(dev->of_node, "spacemit,k1-pll")) { ++ struct device_node *mpmu = of_parse_phandle(dev->of_node, ++ "spacemit,mpmu", 0); ++ if (!mpmu) ++ return dev_err_probe(dev, -ENODEV, ++ "Cannot parse MPMU region\n"); + -+static const char * const cpu_c0_hi_parent_names[] = { -+ "pll3_d2", "pll3_d1" -+}; ++ lock_regmap = device_node_to_regmap(mpmu); ++ of_node_put(mpmu); + -+static SPACEMIT_CCU_MUX(cpu_c0_hi_clk, "cpu_c0_hi_clk", cpu_c0_hi_parent_names, -+ BASE_TYPE_APMU, APMU_CPU_C0_CLK_CTRL, -+ 13, 1, -+ 0); ++ if (IS_ERR(lock_regmap)) ++ return dev_err_probe(dev, PTR_ERR(lock_regmap), ++ "failed to get lock regmap\n"); ++ } + -+static const char * const cpu_c0_parent_names[] = { -+ "pll1_d4_614p4", "pll1_d3_819p2", "pll1_d6_409p6", -+ "pll1_d5_491p52", "pll1_d2_1228p8", "pll3_d3", -+ "pll2_d3", "cpu_c0_hi_clk" -+}; ++ data = of_device_get_match_data(dev); + -+static SPACEMIT_CCU_MUX_FC(cpu_c0_core_clk, "cpu_c0_core_clk", -+ cpu_c0_parent_names, -+ BASE_TYPE_APMU, APMU_CPU_C0_CLK_CTRL, -+ BIT(12), -+ 0, 3, -+ 0); ++ ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, data); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to register clocks\n"); + -+static SPACEMIT_CCU_DIV(cpu_c0_ace_clk, "cpu_c0_ace_clk", "cpu_c0_core_clk", -+ BASE_TYPE_APMU, APMU_CPU_C0_CLK_CTRL, -+ 6, 3, -+ 0); ++ ret = spacemit_ccu_reset_register(dev, base_regmap, data->reset_name); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to register resets\n"); + -+static SPACEMIT_CCU_DIV(cpu_c0_tcm_clk, "cpu_c0_tcm_clk", "cpu_c0_core_clk", -+ BASE_TYPE_APMU, APMU_CPU_C0_CLK_CTRL, -+ 9, 3, -+ 0); ++ return 0; ++} + -+static const char * const cpu_c1_hi_parent_names[] = { -+ "pll3_d2", "pll3_d1" ++static const struct of_device_id of_k1_ccu_match[] = { ++ { ++ .compatible = "spacemit,k1-pll", ++ .data = &k1_ccu_pll_data, ++ }, ++ { ++ .compatible = "spacemit,k1-syscon-mpmu", ++ .data = &k1_ccu_mpmu_data, ++ }, ++ { ++ .compatible = "spacemit,k1-syscon-apbc", ++ .data = &k1_ccu_apbc_data, ++ }, ++ { ++ .compatible = "spacemit,k1-syscon-apmu", ++ .data = &k1_ccu_apmu_data, ++ }, ++ { ++ .compatible = "spacemit,k1-syscon-rcpu", ++ .data = &k1_ccu_rcpu_data, ++ }, ++ { ++ .compatible = "spacemit,k1-syscon-rcpu2", ++ .data = &k1_ccu_rcpu2_data, ++ }, ++ { ++ .compatible = "spacemit,k1-syscon-apbc2", ++ .data = &k1_ccu_apbc2_data, ++ }, ++ { } +}; ++MODULE_DEVICE_TABLE(of, of_k1_ccu_match); + -+static SPACEMIT_CCU_MUX(cpu_c1_hi_clk, "cpu_c1_hi_clk", cpu_c1_hi_parent_names, -+ BASE_TYPE_APMU, APMU_CPU_C1_CLK_CTRL, -+ 13, 1, -+ 0); -+ -+static const char * const cpu_c1_parent_names[] = { -+ "pll1_d4_614p4", "pll1_d3_819p2", "pll1_d6_409p6", -+ "pll1_d5_491p52", "pll1_d2_1228p8", "pll3_d3", -+ "pll2_d3", "cpu_c1_hi_clk" ++static struct platform_driver k1_ccu_driver = { ++ .driver = { ++ .name = "spacemit,k1-ccu", ++ .of_match_table = of_k1_ccu_match, ++ }, ++ .probe = k1_ccu_probe, +}; ++module_platform_driver(k1_ccu_driver); + -+static SPACEMIT_CCU_MUX_FC(cpu_c1_pclk, "cpu_c1_pclk", cpu_c1_parent_names, -+ BASE_TYPE_APMU, APMU_CPU_C1_CLK_CTRL, -+ BIT(12), -+ 0, 3, -+ 0); -+ -+static SPACEMIT_CCU_DIV(cpu_c1_ace_clk, "cpu_c1_ace_clk", "cpu_c1_pclk", -+ BASE_TYPE_APMU, APMU_CPU_C1_CLK_CTRL, -+ 6, 3, -+ 0); -+ -+static SPACEMIT_CCU_GATE_NO_PARENT(pcie0_clk, "pcie0_clk", NULL, -+ BASE_TYPE_APMU, APMU_PCIE_CLK_RES_CTRL_0, -+ 0x7, 0x7, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_GATE_NO_PARENT(pcie1_clk, "pcie1_clk", NULL, -+ BASE_TYPE_APMU, APMU_PCIE_CLK_RES_CTRL_1, -+ 0x7, 0x7, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_GATE_NO_PARENT(pcie2_clk, "pcie2_clk", NULL, -+ BASE_TYPE_APMU, APMU_PCIE_CLK_RES_CTRL_2, -+ 0x7, 0x7, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_GATE_NO_PARENT(emac0_bus_clk, "emac0_bus_clk", NULL, -+ BASE_TYPE_APMU, APMU_EMAC0_CLK_RES_CTRL, -+ BIT(0), BIT(0), 0x0, -+ 0); ++MODULE_DESCRIPTION("SpacemiT K1 CCU driver"); ++MODULE_AUTHOR("Haylen Chu "); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +new file mode 100644 +index 000000000000..96815566cf17 +--- /dev/null ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -0,0 +1,2106 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2025 SpacemiT Technology Co. Ltd ++ */ + -+static SPACEMIT_CCU_GATE(emac0_ptp_clk, "emac0_ptp_clk", "pll2_d6", -+ BASE_TYPE_APMU, APMU_EMAC0_CLK_RES_CTRL, -+ BIT(15), BIT(15), 0x0, -+ 0); ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include + -+static SPACEMIT_CCU_GATE_NO_PARENT(emac1_bus_clk, "emac1_bus_clk", NULL, -+ BASE_TYPE_APMU, APMU_EMAC1_CLK_RES_CTRL, -+ BIT(0), BIT(0), 0x0, -+ 0); ++#include "ccu_common.h" ++#include "ccu_pll.h" ++#include "ccu_mix.h" ++#include "ccu_ddn.h" + -+static SPACEMIT_CCU_GATE(emac1_ptp_clk, "emac1_ptp_clk", "pll2_d6", -+ BASE_TYPE_APMU, APMU_EMAC1_CLK_RES_CTRL, -+ BIT(15), BIT(15), 0x0, -+ 0); ++#include + -+static const char * const uart1_sec_parent_names[] = { -+ "pll1_m3d128_57p6", "slow_uart1_14p74", "slow_uart2_48" ++struct spacemit_ccu_data { ++ const char *reset_name; ++ struct clk_hw **hws; ++ size_t num; +}; + -+static SPACEMIT_CCU_MUX_GATE(uart1_sec_clk, "uart1_sec_clk", -+ uart1_sec_parent_names, -+ BASE_TYPE_APBC2, APBC2_UART1_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); ++/* APBS clocks start, APBS region contains and only contains all PLL clocks */ + -+static const char * const ssp2_sec_parent_names[] = { -+ "pll1_d384_6p4", "pll1_d192_12p8", "pll1_d96_25p6", -+ "pll1_d48_51p2", "pll1_d768_3p2", "pll1_d1536_1p6", -+ "pll1_d3072_0p8" ++/* ++ * PLL{1,2} must run at fixed frequencies to provide clocks in correct rates for ++ * peripherals. ++ */ ++static const struct ccu_pll_rate_tbl pll1_rate_tbl[] = { ++ CCU_PLLA_RATE(2457600000UL, 0x0b330ccc, 0x0000cd00, 0xa0558989), +}; + -+static SPACEMIT_CCU_MUX_GATE(ssp2_sec_clk, "ssp2_sec_clk", -+ ssp2_sec_parent_names, -+ BASE_TYPE_APBC2, APBC2_SSP2_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static const char * const twsi3_sec_parent_names[] = { -+ "pll1_d78_31p5", "pll1_d48_51p2", "pll1_d40_61p44" ++static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = { ++ CCU_PLLA_RATE(3000000000UL, 0x0b3e2000, 0x00000000, 0xa0558c8c), +}; + -+static SPACEMIT_CCU_MUX_GATE(twsi3_sec_clk, "twsi3_sec_clk", -+ twsi3_sec_parent_names, -+ BASE_TYPE_APBC2, APBC2_TWSI3_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_GATE(rtc_sec_clk, "rtc_sec_clk", "clk_32k", -+ BASE_TYPE_APBC2, APBC2_RTC_CLK_RST, -+ 0x83, 0x83, 0x0, 0); ++static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = { ++ CCU_PLLA_RATE(2200000000UL, 0x0b2d3555, 0x00005500, 0xa0558787), ++}; ++ ++static const struct ccu_pll_rate_tbl pll4_rate_tbl[] = { ++ CCU_PLLA_RATE(2200000000UL, 0x0b2d3555, 0x00005500, 0xa0558787), ++}; ++ ++static const struct ccu_pll_rate_tbl pll5_rate_tbl[] = { ++ CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686), ++}; ++ ++static const struct ccu_pll_rate_tbl pll6_rate_tbl[] = { ++ CCU_PLLA_RATE(3200000000UL, 0x0b422aaa, 0x0000ab00, 0xa0558e8e), ++}; ++ ++static const struct ccu_pll_rate_tbl pll7_rate_tbl[] = { ++ CCU_PLLA_RATE(2800000000UL, 0x0b3a1555, 0x00005500, 0xa0558b8b), ++}; ++ ++static const struct ccu_pll_rate_tbl pll8_rate_tbl[] = { ++ CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686), ++}; ++ ++CCU_PLLA_DEFINE(pll1, pll1_rate_tbl, APBS_PLL1_SWCR1, APBS_PLL1_SWCR2, APBS_PLL1_SWCR3, ++ MPMU_POSR, POSR_PLL1_LOCK, CLK_SET_RATE_GATE); ++CCU_PLLA_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR2, APBS_PLL2_SWCR3, ++ MPMU_POSR, POSR_PLL2_LOCK, CLK_SET_RATE_GATE); ++CCU_PLLA_DEFINE(pll3, pll3_rate_tbl, APBS_PLL3_SWCR1, APBS_PLL3_SWCR2, APBS_PLL3_SWCR3, ++ MPMU_POSR, POSR_PLL3_LOCK, CLK_SET_RATE_GATE); ++CCU_PLLA_DEFINE(pll4, pll4_rate_tbl, APBS_PLL4_SWCR1, APBS_PLL4_SWCR2, APBS_PLL4_SWCR3, ++ MPMU_POSR, POSR_PLL4_LOCK, CLK_SET_RATE_GATE); ++CCU_PLLA_DEFINE(pll5, pll5_rate_tbl, APBS_PLL5_SWCR1, APBS_PLL5_SWCR2, APBS_PLL5_SWCR3, ++ MPMU_POSR, POSR_PLL5_LOCK, CLK_SET_RATE_GATE); ++CCU_PLLA_DEFINE(pll6, pll6_rate_tbl, APBS_PLL6_SWCR1, APBS_PLL6_SWCR2, APBS_PLL6_SWCR3, ++ MPMU_POSR, POSR_PLL6_LOCK, CLK_SET_RATE_GATE); ++CCU_PLLA_DEFINE(pll7, pll7_rate_tbl, APBS_PLL7_SWCR1, APBS_PLL7_SWCR2, APBS_PLL7_SWCR3, ++ MPMU_POSR, POSR_PLL7_LOCK, CLK_SET_RATE_GATE); ++CCU_PLLA_DEFINE(pll8, pll8_rate_tbl, APBS_PLL8_SWCR1, APBS_PLL8_SWCR2, APBS_PLL8_SWCR3, ++ MPMU_POSR, POSR_PLL8_LOCK, CLK_SET_RATE_GATE); ++ ++CCU_FACTOR_GATE_DEFINE(pll1_d2, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d3, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d6, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_FLAGS_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(7), 8, 1, ++ CLK_IS_CRITICAL); ++CCU_DIV_GATE_DEFINE(pll1_dx, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, 23, 5, BIT(22), 0); ++CCU_FACTOR_GATE_DEFINE(pll1_d64_38p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(31), 64, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_aud_245p7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(21), 10, 1); ++CCU_FACTOR_DEFINE(pll1_aud_24p5, CCU_PARENT_HW(pll1_aud_245p7), 10, 1); ++ ++CCU_FACTOR_GATE_DEFINE(pll2_d1, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d2, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d3, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d4, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d5, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d6, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d7, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d8, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(7), 8, 1); ++CCU_FACTOR_DEFINE(pll2_66, CCU_PARENT_HW(pll2_d5), 9, 1); ++CCU_FACTOR_DEFINE(pll2_33, CCU_PARENT_HW(pll2_66), 2, 1); ++CCU_FACTOR_DEFINE(pll2_50, CCU_PARENT_HW(pll2_d5), 12, 1); ++CCU_FACTOR_DEFINE(pll2_25, CCU_PARENT_HW(pll2_50), 2, 1); ++CCU_FACTOR_DEFINE(pll2_20, CCU_PARENT_HW(pll2_d5), 30, 1); ++CCU_FACTOR_DEFINE(pll2_d24_125, CCU_PARENT_HW(pll2_d3), 8, 1); ++CCU_FACTOR_DEFINE(pll2_d120_25, CCU_PARENT_HW(pll2_d3), 40, 1); ++ ++CCU_FACTOR_GATE_DEFINE(pll3_d1, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d2, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d3, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d4, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d5, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d6, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d7, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d8, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(7), 8, 1); ++ ++CCU_FACTOR_GATE_DEFINE(pll4_d1, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll4_d2, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll4_d3, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll4_d4, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll4_d5, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll4_d6, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll4_d7, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll4_d8, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(7), 8, 1); ++ ++CCU_FACTOR_GATE_DEFINE(pll5_d1, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll5_d2, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll5_d3, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll5_d4, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll5_d5, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll5_d6, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll5_d7, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll5_d8, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(7), 8, 1); ++ ++CCU_FACTOR_GATE_DEFINE(pll6_d1, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll6_d2, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll6_d3, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll6_d4, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll6_d5, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll6_d6, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll6_d7, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll6_d8, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(7), 8, 1); ++CCU_FACTOR_DEFINE(pll6_80, CCU_PARENT_HW(pll6_d5), 8, 1); ++CCU_FACTOR_DEFINE(pll6_40, CCU_PARENT_HW(pll6_d5), 16, 1); ++CCU_FACTOR_DEFINE(pll6_20, CCU_PARENT_HW(pll6_d5), 32, 1); ++ ++CCU_FACTOR_GATE_DEFINE(pll7_d1, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll7_d2, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll7_d3, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll7_d4, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll7_d5, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll7_d6, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll7_d7, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll7_d8, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(7), 8, 1); ++ ++CCU_FACTOR_GATE_DEFINE(pll8_d1, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll8_d2, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll8_d3, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll8_d4, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll8_d5, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll8_d6, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll8_d7, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll8_d8, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(7), 8, 1); ++/* APBS clocks end */ ++ ++/* MPMU clocks start */ ++CCU_GATE_DEFINE(pll1_d8_307p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(13), 0); ++CCU_FACTOR_DEFINE(pll1_d32_76p8, CCU_PARENT_HW(pll1_d8_307p2), 4, 1); ++CCU_FACTOR_DEFINE(pll1_d40_61p44, CCU_PARENT_HW(pll1_d8_307p2), 5, 1); ++CCU_FACTOR_DEFINE(pll1_d16_153p6, CCU_PARENT_HW(pll1_d8), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d24_102p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(12), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(7), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2_ap, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(11), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_m3d128_57p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(8), 16, 3); ++CCU_FACTOR_GATE_DEFINE(pll1_d96_25p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(4), 12, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(3), 24, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8_wdt, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(19), 24, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d384_6p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(2), 48, 1); ++ ++CCU_FACTOR_DEFINE(pll1_d768_3p2, CCU_PARENT_HW(pll1_d384_6p4), 2, 1); ++CCU_FACTOR_DEFINE(pll1_d1536_1p6, CCU_PARENT_HW(pll1_d384_6p4), 4, 1); ++CCU_FACTOR_DEFINE(pll1_d3072_0p8, CCU_PARENT_HW(pll1_d384_6p4), 8, 1); ++ ++CCU_GATE_DEFINE(pll1_d6_409p6, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(0), 0); ++CCU_FACTOR_GATE_DEFINE(pll1_d12_204p8, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(5), 2, 1); ++ ++CCU_GATE_DEFINE(pll1_d5_491p52, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(21), 0); ++CCU_FACTOR_GATE_DEFINE(pll1_d10_245p76, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(18), 2, 1); ++ ++CCU_GATE_DEFINE(pll1_d4_614p4, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(15), 0); ++CCU_FACTOR_GATE_DEFINE(pll1_d52_47p26, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(10), 13, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d78_31p5, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(6), 39, 2); ++ ++CCU_GATE_DEFINE(pll1_d3_819p2, CCU_PARENT_HW(pll1_d3), MPMU_ACGR, BIT(14), 0); ++ ++CCU_GATE_DEFINE(pll1_d2_1228p8, CCU_PARENT_HW(pll1_d2), MPMU_ACGR, BIT(16), 0); ++ ++static const struct clk_parent_data apb_parents[] = { ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d24_102p4), ++}; ++CCU_MUX_DEFINE(apb_clk, apb_parents, MPMU_APBCSCR, 0, 2, 0); ++ ++CCU_GATE_DEFINE(slow_uart, CCU_PARENT_NAME(osc_32k), MPMU_ACGR, BIT(1), CLK_IGNORE_UNUSED); ++CCU_DDN_DEFINE(slow_uart1_14p74, pll1_d16_153p6, MPMU_SUCCR, 16, 13, 0, 13, 2, 0); ++CCU_DDN_DEFINE(slow_uart2_48, pll1_d4_614p4, MPMU_SUCCR_1, 16, 13, 0, 13, 2, 0); ++ ++CCU_GATE_DEFINE(wdt_clk, CCU_PARENT_HW(pll1_d96_25p6), MPMU_WDTPCR, BIT(1), 0); ++CCU_GATE_DEFINE(wdt_bus_clk, CCU_PARENT_HW(apb_clk), MPMU_WDTPCR, BIT(0), 0); ++ ++CCU_GATE_DEFINE(r_ipc_clk, CCU_PARENT_HW(apb_clk), MPMU_RIPCCR, BIT(0), 0); ++ ++CCU_FACTOR_DEFINE(i2s_153p6, CCU_PARENT_HW(pll1_d8_307p2), 2, 1); ++ ++static const struct clk_parent_data i2s_153p6_base_parents[] = { ++ CCU_PARENT_HW(i2s_153p6), ++ CCU_PARENT_HW(pll1_d8_307p2), ++}; ++CCU_MUX_DEFINE(i2s_153p6_base, i2s_153p6_base_parents, MPMU_FCCR, 29, 1, 0); ++ ++static const struct clk_parent_data i2s_sysclk_src_parents[] = { ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(i2s_153p6_base), ++}; ++CCU_MUX_GATE_DEFINE(i2s_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR, 30, 1, BIT(31), 0); ++ ++CCU_DDN_DEFINE(i2s1_sysclk, i2s_sysclk_src, MPMU_ISCCR, 0, 15, 15, 12, 1, 0); ++ ++CCU_FACTOR_DEFINE(i2s_bclk_factor, CCU_PARENT_HW(i2s1_sysclk), 2, 1); ++/* ++ * Divider of i2s_bclk always implies a 1/2 factor, which is ++ * described by i2s_bclk_factor. ++ */ ++CCU_DIV_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s_bclk_factor), MPMU_ISCCR, 27, 2, BIT(29), 0); ++ ++static const struct clk_parent_data i2s_sysclk_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_NAME(vctcxo_24m), ++ CCU_PARENT_HW(pll2_d5), ++ CCU_PARENT_NAME(vctcxo_24m), ++}; ++CCU_MUX_DEFINE(i2s0_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 0, 2, 0); ++CCU_MUX_DEFINE(i2s2_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 4, 2, 0); ++CCU_MUX_DEFINE(i2s3_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 12, 2, 0); ++CCU_MUX_DEFINE(i2s4_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 16, 2, 0); ++CCU_MUX_DEFINE(i2s5_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 20, 2, 0); ++ ++CCU_DDN_DEFINE(i2s0_sysclk_div, i2s0_sysclk_sel, MPMU_I2S0_SYSCLK, 0, 16, 16, 16, 1, 0); ++CCU_DDN_DEFINE(i2s2_sysclk_div, i2s2_sysclk_sel, MPMU_I2S2_SYSCLK, 0, 16, 16, 16, 1, 0); ++CCU_DDN_DEFINE(i2s3_sysclk_div, i2s3_sysclk_sel, MPMU_I2S3_SYSCLK, 0, 16, 16, 16, 1, 0); ++CCU_DDN_DEFINE(i2s4_sysclk_div, i2s4_sysclk_sel, MPMU_I2S4_SYSCLK, 0, 16, 16, 16, 1, 0); ++CCU_DDN_DEFINE(i2s5_sysclk_div, i2s5_sysclk_sel, MPMU_I2S5_SYSCLK, 0, 16, 16, 16, 1, 0); ++ ++static const struct clk_parent_data i2s2_sysclk_parents[] = { ++ CCU_PARENT_HW(i2s1_sysclk), ++ CCU_PARENT_HW(i2s2_sysclk_div), ++}; ++ ++CCU_GATE_DEFINE(i2s0_sysclk, CCU_PARENT_HW(i2s0_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(2), 0); ++CCU_MUX_GATE_DEFINE(i2s2_sysclk, i2s2_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 8, 1, BIT(6), 0); ++CCU_GATE_DEFINE(i2s3_sysclk, CCU_PARENT_HW(i2s3_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(14), 0); ++CCU_GATE_DEFINE(i2s4_sysclk, CCU_PARENT_HW(i2s4_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(18), 0); ++CCU_GATE_DEFINE(i2s5_sysclk, CCU_PARENT_HW(i2s5_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(22), 0); ++/* MPMU clocks end */ ++ ++/* APBC clocks start */ ++static const struct clk_parent_data uart_clk_parents[] = { ++ CCU_PARENT_HW(pll1_m3d128_57p6), ++ CCU_PARENT_HW(slow_uart1_14p74), ++ CCU_PARENT_HW(slow_uart2_48), ++}; ++CCU_MUX_GATE_DEFINE(uart0_clk, uart_clk_parents, APBC_UART0_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart2_clk, uart_clk_parents, APBC_UART2_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart3_clk, uart_clk_parents, APBC_UART3_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart4_clk, uart_clk_parents, APBC_UART4_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart5_clk, uart_clk_parents, APBC_UART5_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart6_clk, uart_clk_parents, APBC_UART6_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart7_clk, uart_clk_parents, APBC_UART7_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart8_clk, uart_clk_parents, APBC_UART8_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart9_clk, uart_clk_parents, APBC_UART9_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart10_clk, uart_clk_parents, APBC_UART10_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(uart0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART3_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART4_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART5_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART6_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART7_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART8_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART9_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart10_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART10_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(gpio_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_GPIO_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(gpio_bus_clk, CCU_PARENT_HW(apb_clk), APBC_GPIO_CLK_RST, BIT(0), 0); ++ ++static const struct clk_parent_data pwm_parents[] = { ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_NAME(osc_32k), ++}; ++CCU_MUX_GATE_DEFINE(pwm0_clk, pwm_parents, APBC_PWM0_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm1_clk, pwm_parents, APBC_PWM1_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm2_clk, pwm_parents, APBC_PWM2_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm3_clk, pwm_parents, APBC_PWM3_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm4_clk, pwm_parents, APBC_PWM4_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm5_clk, pwm_parents, APBC_PWM5_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm6_clk, pwm_parents, APBC_PWM6_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm7_clk, pwm_parents, APBC_PWM7_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm8_clk, pwm_parents, APBC_PWM8_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm9_clk, pwm_parents, APBC_PWM9_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm10_clk, pwm_parents, APBC_PWM10_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm11_clk, pwm_parents, APBC_PWM11_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm12_clk, pwm_parents, APBC_PWM12_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm13_clk, pwm_parents, APBC_PWM13_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm14_clk, pwm_parents, APBC_PWM14_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm15_clk, pwm_parents, APBC_PWM15_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm16_clk, pwm_parents, APBC_PWM16_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm17_clk, pwm_parents, APBC_PWM17_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm18_clk, pwm_parents, APBC_PWM18_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm19_clk, pwm_parents, APBC_PWM19_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(pwm0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM3_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM4_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM5_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM6_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM7_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM8_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM9_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm10_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM10_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm11_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM11_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm12_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM12_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm13_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM13_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm14_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM14_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm15_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM15_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm16_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM16_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm17_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM17_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm18_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM18_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm19_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM19_CLK_RST, BIT(0), 0); ++ ++static const struct clk_parent_data i2s_bclk_parents[] = { ++ CCU_PARENT_NAME(vctcxo_1m), ++ CCU_PARENT_HW(i2s_bclk), ++}; ++ ++CCU_MUX_DEFINE(spi0_i2s_bclk, i2s_bclk_parents, APBC_SSP0_CLK_RST, 3, 1, 0); ++CCU_MUX_DEFINE(spi1_i2s_bclk, i2s_bclk_parents, APBC_SSP1_CLK_RST, 3, 1, 0); ++CCU_MUX_DEFINE(spi3_i2s_bclk, i2s_bclk_parents, APBC_SSP3_CLK_RST, 3, 1, 0); ++ ++static const struct clk_parent_data spi0_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(spi0_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(spi0_clk, spi0_parents, APBC_SSP0_CLK_RST, 4, 3, BIT(1), 0); ++static const struct clk_parent_data spi1_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(spi1_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(spi1_clk, spi1_parents, APBC_SSP1_CLK_RST, 4, 3, BIT(1), 0); ++static const struct clk_parent_data spi3_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(spi3_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(spi3_clk, spi3_parents, APBC_SSP3_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(spi0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(spi1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(spi3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP3_CLK_RST, BIT(0), 0); ++ ++ ++CCU_GATE_DEFINE(rtc_clk, CCU_PARENT_NAME(osc_32k), APBC_RTC_CLK_RST, ++ BIT(7) | BIT(1), 0); ++CCU_GATE_DEFINE(rtc_bus_clk, CCU_PARENT_HW(apb_clk), APBC_RTC_CLK_RST, BIT(0), 0); ++ ++static const struct clk_parent_data twsi_parents[] = { ++ CCU_PARENT_HW(pll1_d78_31p5), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d40_61p44), ++}; ++CCU_MUX_GATE_DEFINE(twsi0_clk, twsi_parents, APBC_TWSI0_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi1_clk, twsi_parents, APBC_TWSI1_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi2_clk, twsi_parents, APBC_TWSI2_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi4_clk, twsi_parents, APBC_TWSI4_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi5_clk, twsi_parents, APBC_TWSI5_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi6_clk, twsi_parents, APBC_TWSI6_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi8_clk, twsi_parents, APBC_TWSI8_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(twsi0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI4_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI5_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI6_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI8_CLK_RST, BIT(0), 0); ++ ++static const struct clk_parent_data timer_parents[] = { ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_NAME(osc_32k), ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_NAME(vctcxo_3m), ++ CCU_PARENT_NAME(vctcxo_1m), ++}; ++CCU_MUX_GATE_DEFINE(timers0_clk, timer_parents, APBC_TIMERS0_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(timers1_clk, timer_parents, APBC_TIMERS1_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(timers2_clk, timer_parents, APBC_TIMERS2_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(timers3_clk, timer_parents, APBC_TIMERS3_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(timers4_clk, timer_parents, APBC_TIMERS4_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(timers5_clk, timer_parents, APBC_TIMERS5_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(timers6_clk, timer_parents, APBC_TIMERS6_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(timers7_clk, timer_parents, APBC_TIMERS7_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(timers0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(timers1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(timers2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(timers3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS3_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(timers4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS4_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(timers5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS5_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(timers6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS6_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(timers7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS7_CLK_RST, BIT(0), 0); ++ ++ ++CCU_GATE_DEFINE(aib_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_AIB_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(aib_bus_clk, CCU_PARENT_HW(apb_clk), APBC_AIB_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(onewire_bus_clk, CCU_PARENT_HW(apb_clk), APBC_ONEWIRE_CLK_RST, BIT(0), 0); ++ ++/* ++ * When i2s_bclk is selected as the parent clock of sspa, ++ * the hardware requires bit3 to be set ++ */ ++ ++CCU_MUX_DEFINE(i2s0_i2s_bclk, i2s_bclk_parents, APBC_SSPA0_CLK_RST, 3, 1, 0); ++CCU_MUX_DEFINE(i2s1_i2s_bclk, i2s_bclk_parents, APBC_SSPA1_CLK_RST, 3, 1, 0); ++CCU_MUX_DEFINE(i2s2_i2s_bclk, i2s_bclk_parents, APBC_SSPA2_CLK_RST, 3, 1, 0); ++CCU_MUX_DEFINE(i2s3_i2s_bclk, i2s_bclk_parents, APBC_SSPA3_CLK_RST, 3, 1, 0); ++CCU_MUX_DEFINE(i2s4_i2s_bclk, i2s_bclk_parents, APBC_SSPA4_CLK_RST, 3, 1, 0); ++CCU_MUX_DEFINE(i2s5_i2s_bclk, i2s_bclk_parents, APBC_SSPA5_CLK_RST, 3, 1, 0); ++ ++static const struct clk_parent_data i2s0_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(i2s0_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(i2s0_clk, i2s0_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0); ++ ++static const struct clk_parent_data i2s1_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(i2s1_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(i2s1_clk, i2s1_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0); ++ ++static const struct clk_parent_data i2s2_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(i2s2_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(i2s2_clk, i2s2_parents, APBC_SSPA2_CLK_RST, 4, 3, BIT(1), 0); ++ ++static const struct clk_parent_data i2s3_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(i2s3_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(i2s3_clk, i2s3_parents, APBC_SSPA3_CLK_RST, 4, 3, BIT(1), 0); ++ ++static const struct clk_parent_data i2s4_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(i2s4_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(i2s4_clk, i2s4_parents, APBC_SSPA4_CLK_RST, 4, 3, BIT(1), 0); ++ ++static const struct clk_parent_data i2s5_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(i2s5_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(i2s5_clk, i2s5_parents, APBC_SSPA5_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(i2s0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(i2s1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(i2s2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(i2s3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA3_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(i2s4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA4_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(i2s5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA5_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(dro_clk, CCU_PARENT_HW(apb_clk), APBC_DRO_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(ir0_clk, CCU_PARENT_HW(apb_clk), APBC_IR0_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(ir1_clk, CCU_PARENT_HW(apb_clk), APBC_IR1_CLK_RST, BIT(1), 0); ++ ++CCU_GATE_DEFINE(tsen_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(tsen_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(ipc_ap2rcpu_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(ipc_ap2rcpu_bus_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(0), 0); ++ ++static const struct clk_parent_data can_parents[] = { ++ CCU_PARENT_HW(pll6_20), ++ CCU_PARENT_HW(pll6_40), ++ CCU_PARENT_HW(pll6_80), ++}; ++CCU_MUX_GATE_DEFINE(can0_clk, can_parents, APBC_CAN0_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(can1_clk, can_parents, APBC_CAN1_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(can2_clk, can_parents, APBC_CAN2_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(can3_clk, can_parents, APBC_CAN3_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(can4_clk, can_parents, APBC_CAN4_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(can0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(can1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(can2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(can3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN3_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(can4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN4_CLK_RST, BIT(0), 0); ++/* APBC clocks end */ ++ ++/* APMU clocks start */ ++static const struct clk_parent_data axi_clk_parents[] = { ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d6_409p6), ++}; ++CCU_MUX_DIV_FC_DEFINE(axi_clk, axi_clk_parents, APMU_ACLK_CLK_CTRL, 1, 2, BIT(4), 0, 1, 0); ++ ++static const struct clk_parent_data cci550_clk_parents[] = { ++ CCU_PARENT_HW(pll1_d10_245p76), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll7_d3), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll7_d2), ++}; ++CCU_MUX_DIV_FC_DEFINE(cci550_clk, cci550_clk_parents, APMU_CCI550_CLK_CTRL, 8, 2, BIT(12), 0, 3, ++ CLK_IS_CRITICAL); ++ ++static const struct clk_parent_data cpu_c0_clk_parents[] = { ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll3_d2), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll2_d2), ++ CCU_PARENT_HW(pll3_d1), ++}; ++CCU_MUX_DIV_FC_DEFINE(cpu_c0_core_clk, cpu_c0_clk_parents, APMU_CPU_C0_CLK_CTRL, ++ 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); ++ ++static const struct clk_parent_data cpu_c1_clk_parents[] = { ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll4_d2), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll2_d2), ++ CCU_PARENT_HW(pll4_d1), ++}; ++CCU_MUX_DIV_FC_DEFINE(cpu_c1_core_clk, cpu_c1_clk_parents, APMU_CPU_C1_CLK_CTRL, ++ 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); ++ ++static const struct clk_parent_data cpu_c2_clk_parents[] = { ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll5_d2), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll2_d2), ++ CCU_PARENT_HW(pll5_d1), ++}; ++CCU_MUX_DIV_FC_DEFINE(cpu_c2_core_clk, cpu_c2_clk_parents, APMU_CPU_C2_CLK_CTRL, ++ 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); ++ ++static const struct clk_parent_data cpu_c3_clk_parents[] = { ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll8_d2), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll2_d2), ++ CCU_PARENT_HW(pll8_d1), ++}; ++CCU_MUX_DIV_FC_DEFINE(cpu_c3_core_clk, cpu_c3_clk_parents, APMU_CPU_C3_CLK_CTRL, ++ 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); ++ ++static const struct clk_parent_data ccic2phy_parents[] = { ++ CCU_PARENT_HW(pll1_d24_102p4), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++}; ++CCU_MUX_GATE_DEFINE(ccic2phy_clk, ccic2phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 7, 1, BIT(5), 0); ++ ++static const struct clk_parent_data ccic3phy_parents[] = { ++ CCU_PARENT_HW(pll1_d24_102p4), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++}; ++CCU_MUX_GATE_DEFINE(ccic3phy_clk, ccic3phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 31, 1, BIT(30), 0); ++ ++static const struct clk_parent_data csi_parents[] = { ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll2_d2), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(csi_clk, csi_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 20, 3, BIT(15), ++ 16, 3, BIT(4), 0); ++ ++static const struct clk_parent_data isp_bus_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d10_245p76), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(isp_bus_clk, isp_bus_parents, APMU_ISP_CLK_RES_CTRL, 18, 3, BIT(23), ++ 21, 2, BIT(17), 0); ++ ++CCU_GATE_DEFINE(d1p_1228p8, CCU_PARENT_HW(pll1_d2_1228p8), APMU_PMU_CLK_GATE_CTRL, BIT(31), 0); ++CCU_GATE_DEFINE(d1p_819p2, CCU_PARENT_HW(pll1_d3_819p2), APMU_PMU_CLK_GATE_CTRL, BIT(30), 0); ++CCU_GATE_DEFINE(d1p_614p4, CCU_PARENT_HW(pll1_d4_614p4), APMU_PMU_CLK_GATE_CTRL, BIT(29), 0); ++CCU_GATE_DEFINE(d1p_491p52, CCU_PARENT_HW(pll1_d5_491p52), APMU_PMU_CLK_GATE_CTRL, BIT(28), 0); ++CCU_GATE_DEFINE(d1p_409p6, CCU_PARENT_HW(pll1_d6_409p6), APMU_PMU_CLK_GATE_CTRL, BIT(27), 0); ++CCU_GATE_DEFINE(d1p_307p2, CCU_PARENT_HW(pll1_d8_307p2), APMU_PMU_CLK_GATE_CTRL, BIT(26), 0); ++CCU_GATE_DEFINE(d1p_245p76, CCU_PARENT_HW(pll1_d10_245p76), APMU_PMU_CLK_GATE_CTRL, BIT(22), 0); ++ ++static const struct clk_parent_data v2d_parents[] = { ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d4_614p4), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(v2d_clk, v2d_parents, APMU_LCD_CLK_RES_CTRL1, 9, 3, BIT(28), 12, 2, ++ BIT(8), 0); ++ ++static const struct clk_parent_data dsiesc_parents[] = { ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++ CCU_PARENT_HW(pll1_d52_47p26), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d32_76p8), ++}; ++CCU_MUX_GATE_DEFINE(dsi_esc_clk, dsiesc_parents, APMU_LCD_CLK_RES_CTRL1, 0, 2, BIT(2), 0); ++ ++CCU_GATE_DEFINE(lcd_hclk, CCU_PARENT_HW(axi_clk), APMU_LCD_CLK_RES_CTRL1, BIT(5), 0); ++ ++static const struct clk_parent_data lcd_dsc_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d10_245p76), ++ CCU_PARENT_HW(pll7_d5), ++ CCU_PARENT_HW(pll2_d7), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++ CCU_PARENT_HW(pll2_d8), ++}; ++CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(lcd_dsc_clk, lcd_dsc_parents, APMU_LCD_CLK_RES_CTRL2, ++ APMU_LCD_CLK_RES_CTRL1, 25, 3, BIT(26), 29, 3, BIT(14), 0); ++ ++static const struct clk_parent_data lcdpx_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d10_245p76), ++ CCU_PARENT_HW(pll7_d5), ++ CCU_PARENT_HW(pll2_d7), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++ CCU_PARENT_HW(pll2_d8), ++}; ++CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(lcd_pxclk, lcdpx_parents, APMU_LCD_CLK_RES_CTRL2, ++ APMU_LCD_CLK_RES_CTRL1, 17, 3, BIT(30), 21, 3, BIT(16), 0); ++ ++static const struct clk_parent_data lcdmclk_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d8_307p2), ++}; ++CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(lcd_mclk, lcdmclk_parents, APMU_LCD_CLK_RES_CTRL2, ++ APMU_LCD_CLK_RES_CTRL1, 1, 4, BIT(29), 5, 3, BIT(0), 0); ++ ++static const struct clk_parent_data ccic_4x_parents[] = { ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll2_d2), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(ccic_4x_clk, ccic_4x_parents, APMU_CCIC_CLK_RES_CTRL, 18, 3, ++ BIT(15), 23, 2, BIT(4), 0); ++ ++static const struct clk_parent_data ccic1phy_parents[] = { ++ CCU_PARENT_HW(pll1_d24_102p4), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++}; ++CCU_MUX_GATE_DEFINE(ccic1phy_clk, ccic1phy_parents, APMU_CCIC_CLK_RES_CTRL, 7, 1, BIT(5), 0); ++ ++ ++static const struct clk_parent_data sc2hclk_parents[] = { ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll2_d4), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(sc2_hclk, sc2hclk_parents, APMU_CCIC_CLK_RES_CTRL, 10, 3, ++ BIT(16), 8, 2, BIT(3), 0); ++ ++CCU_GATE_DEFINE(sdh_axi_aclk, CCU_PARENT_HW(axi_clk), APMU_SDH0_CLK_RES_CTRL, BIT(3), 0); ++static const struct clk_parent_data sdh01_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll2_d8), ++ CCU_PARENT_HW(pll2_d5), ++ CCU_PARENT_NAME(reserved_clk), ++ CCU_PARENT_NAME(reserved_clk), ++ CCU_PARENT_HW(pll1_dx), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(sdh0_clk, sdh01_parents, APMU_SDH0_CLK_RES_CTRL, 8, 3, ++ BIT(11), 5, 3, BIT(4), 0); ++CCU_MUX_DIV_GATE_FC_DEFINE(sdh1_clk, sdh01_parents, APMU_SDH1_CLK_RES_CTRL, 8, 3, ++ BIT(11), 5, 3, BIT(4), 0); ++static const struct clk_parent_data sdh2_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll2_d8), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_NAME(reserved_clk), ++ CCU_PARENT_NAME(reserved_clk), ++ CCU_PARENT_HW(pll1_dx), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(sdh2_clk, sdh2_parents, APMU_SDH2_CLK_RES_CTRL, 8, 3, ++ BIT(11), 5, 3, BIT(4), 0); ++ ++CCU_GATE_DEFINE(usb2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(0), 0); ++CCU_GATE_DEFINE(usb3_porta_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(4), 0); ++CCU_GATE_DEFINE(usb3_portb_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(8), 0); ++CCU_GATE_DEFINE(usb3_portc_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(12), 0); ++CCU_GATE_DEFINE(usb3_portd_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(16), 0); ++ ++static const struct clk_parent_data qspi_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll2_d8), ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d10_245p76), ++ CCU_PARENT_NAME(reserved_clk), ++ CCU_PARENT_HW(pll1_dx), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_NAME(reserved_clk), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(qspi_clk, qspi_parents, APMU_QSPI_CLK_RES_CTRL, 9, 3, ++ BIT(12), 6, 3, BIT(4), 0); ++CCU_GATE_DEFINE(qspi_bus_clk, CCU_PARENT_HW(axi_clk), APMU_QSPI_CLK_RES_CTRL, BIT(3), 0); ++ ++CCU_GATE_DEFINE(dma_clk, CCU_PARENT_HW(axi_clk), APMU_DMA_CLK_RES_CTRL, BIT(3), 0); ++ ++static const struct clk_parent_data aes_wtm_parents[] = { ++ CCU_PARENT_HW(pll1_d12_204p8), ++ CCU_PARENT_HW(pll1_d24_102p4), ++}; ++CCU_MUX_GATE_DEFINE(aes_wtm_clk, aes_wtm_parents, APMU_AES_CLK_RES_CTRL, 6, 1, BIT(5), 0); ++ ++static const struct clk_parent_data vpu_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll2_d5), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(vpu_clk, vpu_parents, APMU_VPU_CLK_RES_CTRL, 13, 3, ++ BIT(21), 10, 3, BIT(3), 0); ++ ++CCU_GATE_DEFINE(dtc_clk, CCU_PARENT_HW(axi_clk), APMU_DTC_CLK_RES_CTRL, BIT(3), 0); ++ ++static const struct clk_parent_data gpu_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll2_d5), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(gpu_clk, gpu_parents, APMU_GPU_CLK_RES_CTRL, 12, 3, ++ BIT(15), 18, 3, BIT(4), 0); ++ ++CCU_GATE_DEFINE(mc_ahb_clk, CCU_PARENT_HW(axi_clk), APMU_PMUA_MC_CTRL, BIT(1), 0); ++ ++static const struct clk_parent_data top_parents[] = { ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll3_d4), ++ CCU_PARENT_HW(pll6_d5), ++ CCU_PARENT_HW(pll7_d4), ++ CCU_PARENT_HW(pll6_d4), ++ CCU_PARENT_HW(pll7_d3), ++ CCU_PARENT_HW(pll6_d3), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(top_dclk, top_parents, APMU_TOP_DCLK_CTRL, 5, 3, ++ BIT(8), 2, 3, BIT(1), 0); ++ ++static const struct clk_parent_data ucie_parents[] = { ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll3_d4), ++ CCU_PARENT_HW(pll6_d5), ++ CCU_PARENT_HW(pll7_d4), ++ CCU_PARENT_HW(pll6_d4), ++}; ++CCU_MUX_GATE_DEFINE(ucie_clk, ucie_parents, APMU_UCIE_CTRL, 4, 3, BIT(0), 0); ++CCU_GATE_DEFINE(ucie_sbclk, CCU_PARENT_HW(axi_clk), APMU_UCIE_CTRL, BIT(8), 0); ++ ++static const struct clk_parent_data rcpu_clk_parents[] = { ++ CCU_PARENT_HW(pll1_aud_245p7), ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d6_409p6), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(rcpu_clk, rcpu_clk_parents, APMU_RCPU_CLK_RES_CTRL, ++ 4, 3, BIT(15), 7, 3, BIT(12), 0); ++ ++static const struct clk_parent_data dsi4ln2_dsi_esc_parents[] = { ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++ CCU_PARENT_HW(pll1_d52_47p26), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d32_76p8), ++}; ++CCU_MUX_GATE_DEFINE(dsi4ln2_dsi_esc_clk, dsi4ln2_dsi_esc_parents, APMU_LCD_CLK_RES_CTRL3, ++ 0, 1, BIT(2), 0); ++ ++static const struct clk_parent_data dsi4ln2_lcd_dsc_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll7_d5), ++ CCU_PARENT_HW(pll6_d6), ++ CCU_PARENT_HW(pll2_d7), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++}; ++CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dsi4ln2_lcd_dsc_clk, dsi4ln2_lcd_dsc_parents, ++ APMU_LCD_CLK_RES_CTRL4, APMU_LCD_CLK_RES_CTRL3, ++ 25, 3, BIT(26), 29, 3, BIT(14), 0); ++ ++static const struct clk_parent_data dsi4ln2_lcdpx_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll7_d5), ++ CCU_PARENT_HW(pll6_d6), ++ CCU_PARENT_HW(pll2_d7), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++ CCU_PARENT_HW(pll2_d8), ++}; ++CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dsi4ln2_lcd_pxclk, dsi4ln2_lcdpx_parents, APMU_LCD_CLK_RES_CTRL4, ++ APMU_LCD_CLK_RES_CTRL3, 17, 3, BIT(30), 21, 3, BIT(16), 0); ++ ++static const struct clk_parent_data dsi4ln2_lcd_mclk_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d8_307p2), ++}; ++CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dsi4ln2_lcd_mclk, dsi4ln2_lcd_mclk_parents, APMU_LCD_CLK_RES_CTRL4, ++ APMU_LCD_CLK_RES_CTRL3, 1, 4, BIT(29), 5, 3, BIT(0), 0); ++ ++static const struct clk_parent_data dpu_aclk_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll2_d4), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(dsi4ln2_dpu_aclk, dpu_aclk_parents, APMU_LCD_CLK_RES_CTRL5, ++ 2, 3, BIT(30), 5, 3, BIT(1), 0); ++ ++CCU_MUX_DIV_GATE_FC_DEFINE(dpu_aclk, dpu_aclk_parents, APMU_LCD_CLK_RES_CTRL5, 17, 3, BIT(31), ++ 20, 3, BIT(16), 0); ++ ++static const struct clk_parent_data ufs_aclk_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll2_d4), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(ufs_aclk, ufs_aclk_parents, APMU_UFS_CLK_RES_CTRL, 5, 3, BIT(8), ++ 2, 3, BIT(1), 0); ++ ++static const struct clk_parent_data edp0_pclk_parents[] = { ++ CCU_PARENT_HW(lcd_pxclk), ++ CCU_PARENT_NAME(external_clk), ++}; ++CCU_MUX_GATE_DEFINE(edp0_pxclk, edp0_pclk_parents, APMU_LCD_EDP_CTRL, 2, 1, BIT(1), 0); ++ ++static const struct clk_parent_data edp1_pclk_parents[] = { ++ CCU_PARENT_HW(dsi4ln2_lcd_pxclk), ++ CCU_PARENT_NAME(external_clk), ++}; ++CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT(17), 0); ++ ++CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); ++CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); ++CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); ++CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); ++CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); ++CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); ++CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); ++CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); ++CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); ++CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); ++ ++static const struct clk_parent_data emac_1588_parents[] = { ++ CCU_PARENT_NAME(vctcxo_24m), ++ CCU_PARENT_HW(pll2_d24_125), ++}; ++ ++CCU_GATE_DEFINE(emac0_bus_clk, CCU_PARENT_HW(axi_clk), APMU_EMAC0_CLK_RES_CTRL, BIT(0), 0); ++CCU_GATE_FLAGS_DEFINE(emac0_ref_clk, CCU_PARENT_HW(pll2_d120_25), APMU_EMAC0_CLK_RES_CTRL, ++ BIT(14), CCU_GATE_INVERT_FLAG); ++CCU_MUX_DEFINE(emac0_1588_clk, emac_1588_parents, APMU_EMAC0_CLK_RES_CTRL, 15, 1, 0); ++CCU_GATE_DEFINE(emac0_rgmii_tx_clk, CCU_PARENT_HW(pll2_d24_125), APMU_EMAC0_CLK_RES_CTRL, ++ BIT(8), 0); ++CCU_GATE_DEFINE(emac1_bus_clk, CCU_PARENT_HW(axi_clk), APMU_EMAC1_CLK_RES_CTRL, BIT(0), 0); ++CCU_GATE_FLAGS_DEFINE(emac1_ref_clk, CCU_PARENT_HW(pll2_d120_25), APMU_EMAC1_CLK_RES_CTRL, ++ BIT(14), CCU_GATE_INVERT_FLAG); ++CCU_MUX_DEFINE(emac1_1588_clk, emac_1588_parents, APMU_EMAC1_CLK_RES_CTRL, 15, 1, 0); ++CCU_GATE_DEFINE(emac1_rgmii_tx_clk, CCU_PARENT_HW(pll2_d24_125), APMU_EMAC1_CLK_RES_CTRL, ++ BIT(8), 0); ++CCU_GATE_DEFINE(emac2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_EMAC2_CLK_RES_CTRL, BIT(0), 0); ++CCU_GATE_FLAGS_DEFINE(emac2_ref_clk, CCU_PARENT_HW(pll2_d120_25), APMU_EMAC2_CLK_RES_CTRL, ++ BIT(14), CCU_GATE_INVERT_FLAG); ++CCU_MUX_DEFINE(emac2_1588_clk, emac_1588_parents, APMU_EMAC2_CLK_RES_CTRL, 15, 1, 0); ++CCU_GATE_DEFINE(emac2_rgmii_tx_clk, CCU_PARENT_HW(pll2_d24_125), APMU_EMAC2_CLK_RES_CTRL, ++ BIT(8), 0); ++ ++static const struct clk_parent_data espi_sclk_src_parents[] = { ++ CCU_PARENT_HW(pll2_20), ++ CCU_PARENT_HW(pll2_25), ++ CCU_PARENT_HW(pll2_33), ++ CCU_PARENT_HW(pll2_50), ++ CCU_PARENT_HW(pll2_66), ++}; ++CCU_MUX_DEFINE(espi_sclk_src, espi_sclk_src_parents, APMU_ESPI_CLK_RES_CTRL, 4, 3, 0); ++ ++static const struct clk_parent_data espi_sclk_parents[] = { ++ CCU_PARENT_NAME(external_clk), ++ CCU_PARENT_HW(espi_sclk_src), ++}; ++CCU_MUX_GATE_DEFINE(espi_sclk, espi_sclk_parents, APMU_ESPI_CLK_RES_CTRL, 7, 1, BIT(3), 0); ++ ++CCU_GATE_DEFINE(espi_mclk, CCU_PARENT_HW(axi_clk), APMU_ESPI_CLK_RES_CTRL, BIT(1), 0); ++ ++CCU_FACTOR_DEFINE(cam_src1_clk, CCU_PARENT_HW(pll1_d6_409p6), 15, 1); ++CCU_FACTOR_DEFINE(cam_src2_clk, CCU_PARENT_HW(pll2_d5), 25, 1); ++CCU_FACTOR_DEFINE(cam_src3_clk, CCU_PARENT_HW(pll2_d6), 20, 1); ++CCU_FACTOR_DEFINE(cam_src4_clk, CCU_PARENT_HW(pll1_d6_409p6), 16, 1); ++ ++static const struct clk_parent_data isim_vclk_parents[] = { ++ CCU_PARENT_HW(cam_src1_clk), ++ CCU_PARENT_HW(cam_src2_clk), ++ CCU_PARENT_HW(cam_src3_clk), ++ CCU_PARENT_HW(cam_src4_clk), ++}; ++CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out0, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 3, 4, ++ 1, 2, BIT(0), 0); ++CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out1, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 11, 4, ++ 9, 2, BIT(8), 0); ++CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out2, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 19, 4, ++ 17, 2, BIT(16), 0); ++CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out3, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 27, 4, ++ 25, 2, BIT(24), 0); ++/* APMU clocks end */ ++ ++/* DCIU clocks start */ ++CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), 0); ++CCU_GATE_DEFINE(dma350_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_SDMA_CLK_EN, BIT(0), 0); ++CCU_GATE_DEFINE(c2_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C2_TCM_PIPE_CLK, BIT(0), 0); ++CCU_GATE_DEFINE(c3_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C3_TCM_PIPE_CLK, BIT(0), 0); ++/* DCIU clocks end */ ++ ++/* RPMU clocks start */ ++CCU_DIV_FC_DEFINE(rcpu_apb_clk, CCU_PARENT_HW(rcpu_clk), RCPU5_RCPU_BUS_CLK_CTRL, BIT(8), 3, 3, 0); ++CCU_DIV_FC_DEFINE(rcpu_axi_clk, CCU_PARENT_HW(rcpu_clk), RCPU5_RCPU_BUS_CLK_CTRL, BIT(8), 0, 2, 0); ++ ++CCU_GATE_DEFINE(ripc2msa_clk, CCU_PARENT_HW(rcpu_clk), RCPU5_AON_PER_CLK_RST_CTRL, BIT(5), 0); ++CCU_GATE_DEFINE(ripc2cp_clk, CCU_PARENT_HW(rcpu_clk), RCPU5_AON_PER_CLK_RST_CTRL, BIT(3), 0); ++CCU_GATE_DEFINE(ripc2ap_clk, CCU_PARENT_HW(rcpu_clk), RCPU5_AON_PER_CLK_RST_CTRL, BIT(1), 0); ++ ++static const struct clk_parent_data rtimer_parents[] = { ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d768_3p2), ++}; ++CCU_MUX_DIV_GATE_DEFINE(rtimer1_clk, rtimer_parents, RCPU5_TIMER1_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_GATE_DEFINE(rtimer1_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU5_TIMER1_CLK_RST, BIT(2), 0); ++CCU_MUX_DIV_GATE_DEFINE(rtimer2_clk, rtimer_parents, RCPU5_TIMER2_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_GATE_DEFINE(rtimer2_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU5_TIMER2_CLK_RST, BIT(2), 0); ++CCU_MUX_DIV_GATE_DEFINE(rtimer3_clk, rtimer_parents, RCPU5_TIMER3_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_GATE_DEFINE(rtimer3_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU5_TIMER3_CLK_RST, BIT(2), 0); ++CCU_MUX_DIV_GATE_DEFINE(rtimer4_clk, rtimer_parents, RCPU5_TIMER4_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_GATE_DEFINE(rtimer4_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU5_TIMER4_CLK_RST, BIT(2), 0); ++ ++static const struct clk_parent_data rt24_core_parents[] = { ++ CCU_PARENT_HW(rcpu_clk), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++}; ++CCU_MUX_DIV_FC_DEFINE(rt24_core0_clk, rt24_core_parents, RCPU5_RT24_CORE0_CLK_CTRL, ++ 0, 2, BIT(8), 4, 2, 0); ++CCU_MUX_DIV_FC_DEFINE(rt24_core1_clk, rt24_core_parents, RCPU5_RT24_CORE1_CLK_CTRL, ++ 0, 2, BIT(8), 4, 2, 0); ++ ++CCU_GATE_DEFINE(rgpio_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU5_GPIO_AND_EDGE_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(rgpio_edge_clk, CCU_PARENT_HW(rcpu_apb_clk), ++ RCPU5_GPIO_AND_EDGE_CLK_RST, BIT(3), 0); ++CCU_GATE_DEFINE(rgpio_lp_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU5_GPIO_AND_EDGE_CLK_RST, BIT(4), 0); ++/* RPMU clocks end */ ++ ++/* RCPU SYSCTRL clocks start */ ++static const struct clk_parent_data rcan_parents[] = { ++ CCU_PARENT_HW(pll6_20), ++ CCU_PARENT_HW(pll6_40), ++ CCU_PARENT_HW(pll6_80), ++}; ++CCU_MUX_GATE_DEFINE(rcan0_clk, rcan_parents, RCPU_CAN_CLK_RST, 4, 2, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(rcan1_clk, rcan_parents, RCPU_CAN1_CLK_RST, 4, 2, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(rcan2_clk, rcan_parents, RCPU_CAN2_CLK_RST, 4, 2, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(rcan3_clk, rcan_parents, RCPU_CAN3_CLK_RST, 4, 2, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(rcan4_clk, rcan_parents, RCPU_CAN4_CLK_RST, 4, 2, BIT(1), 0); ++ ++CCU_GATE_DEFINE(rcan0_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU_CAN_CLK_RST, BIT(2), 0); ++CCU_GATE_DEFINE(rcan1_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU_CAN1_CLK_RST, BIT(2), 0); ++CCU_GATE_DEFINE(rcan2_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU_CAN2_CLK_RST, BIT(2), 0); ++CCU_GATE_DEFINE(rcan3_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU_CAN3_CLK_RST, BIT(2), 0); ++CCU_GATE_DEFINE(rcan4_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU_CAN4_CLK_RST, BIT(2), 0); ++ ++CCU_GATE_DEFINE(rirc0_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU_IRC_CLK_RST, BIT(2), 0); ++CCU_GATE_DEFINE(rirc1_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU_IRC1_CLK_RST, BIT(2), 0); ++ ++CCU_MUX_DEFINE(respi_sclk_src, espi_sclk_src_parents, RCPU_ESPI_CLK_RST, 4, 3, 0); ++CCU_MUX_GATE_DEFINE(respi_sclk, espi_sclk_parents, RCPU_ESPI_CLK_RST, 8, 1, BIT(1), 0); ++ ++CCU_GATE_DEFINE(remac_bus_clk, CCU_PARENT_HW(rcpu_axi_clk), RCPU_GMAC_CLK_RST, BIT(0), 0); ++CCU_GATE_FLAGS_DEFINE(remac_ref_clk, CCU_PARENT_HW(pll2_d120_25), RCPU_GMAC_CLK_RST, ++ BIT(14), CCU_GATE_INVERT_FLAG); ++CCU_MUX_DEFINE(remac_1588_clk, emac_1588_parents, RCPU_GMAC_CLK_RST, 15, 1, 0); ++CCU_GATE_DEFINE(remac_rgmii_tx_clk, CCU_PARENT_HW(pll2_d24_125), RCPU_GMAC_CLK_RST, BIT(8), 0); ++ ++static const struct clk_parent_data ri2s01_sysclk_parents[] = { ++ CCU_PARENT_HW(pll1_aud_24p5), ++ CCU_PARENT_HW(pll1_aud_245p7), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d768_3p2), ++}; ++CCU_MUX_DIV_GATE_DEFINE(ri2s0_sysclk, ri2s01_sysclk_parents, RCPU_AUDIO_I2S0_SYS_CLK_CTRL, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_MUX_DIV_GATE_DEFINE(ri2s1_sysclk, ri2s01_sysclk_parents, RCPU_AUDIO_I2S1_SYS_CLK_CTRL, 8, 11, ++ 4, 2, BIT(1), 0); ++/* RCPU SYSCTRL clocks end */ ++ ++/* RCPU UARTCTRL clocks start */ ++static const struct clk_parent_data ruart_clk_parents[] = { ++ CCU_PARENT_HW(slow_uart1_14p74), ++ CCU_PARENT_HW(pll1_aud_245p7), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_m3d128_57p6), ++}; ++CCU_MUX_DIV_GATE_DEFINE(ruart0_clk, ruart_clk_parents, RCPU1_UART0_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_MUX_DIV_GATE_DEFINE(ruart1_clk, ruart_clk_parents, RCPU1_UART1_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_MUX_DIV_GATE_DEFINE(ruart2_clk, ruart_clk_parents, RCPU1_UART2_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_MUX_DIV_GATE_DEFINE(ruart3_clk, ruart_clk_parents, RCPU1_UART3_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_MUX_DIV_GATE_DEFINE(ruart4_clk, ruart_clk_parents, RCPU1_UART4_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_MUX_DIV_GATE_DEFINE(ruart5_clk, ruart_clk_parents, RCPU1_UART5_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_GATE_DEFINE(ruart0_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU1_UART0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(ruart1_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU1_UART1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(ruart2_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU1_UART2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(ruart3_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU1_UART3_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(ruart4_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU1_UART4_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(ruart5_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU1_UART5_CLK_RST, BIT(0), 0); ++/* RCPU UARTCTRLclocks end */ ++ ++/* RCPU I2SCTRL clocks start */ ++static const struct clk_parent_data ri2s_clk_parents[] = { ++ CCU_PARENT_HW(pll1_aud_24p5), ++ CCU_PARENT_HW(pll1_aud_245p7), ++}; ++CCU_MUX_DIV_GATE_DEFINE(ri2s0_clk, ri2s_clk_parents, RCPU2_AUDIO_I2S0_TX_RX_CLK_CTRL, 4, 11, ++ 16, 2, BIT(2), 0); ++CCU_MUX_DIV_GATE_DEFINE(ri2s1_clk, ri2s_clk_parents, RCPU2_AUDIO_I2S1_TX_RX_CLK_CTRL, 4, 11, ++ 16, 2, BIT(2), 0); ++ ++ ++CCU_GATE_DEFINE(ri2s0_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), ++ RCPU2_AUDIO_I2S0_TX_RX_CLK_CTRL, BIT(1), 0); ++CCU_GATE_DEFINE(ri2s1_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), ++ RCPU2_AUDIO_I2S1_TX_RX_CLK_CTRL, BIT(1), 0); ++ ++static const struct clk_parent_data ri2s23_sysclk_parents[] = { ++ CCU_PARENT_HW(pll1_aud_24p5), ++ CCU_PARENT_HW(pll1_aud_245p7), ++}; ++CCU_MUX_DIV_GATE_DEFINE(ri2s2_sysclk, ri2s23_sysclk_parents, RCPU2_AUDIO_I2S2_SYS_CLK_CTRL, ++ 4, 11, 16, 2, BIT(2), 0); ++CCU_MUX_DIV_GATE_DEFINE(ri2s3_sysclk, ri2s23_sysclk_parents, RCPU2_AUDIO_I2S3_SYS_CLK_CTRL, ++ 4, 11, 16, 2, BIT(2), 0); ++ ++CCU_DIV_GATE_DEFINE(ri2s2_clk, CCU_PARENT_HW(ri2s2_sysclk), RCPU2_AUDIO_I2S2_TX_RX_CLK_CTRL, ++ 4, 11, BIT(2), 0); ++CCU_DIV_GATE_DEFINE(ri2s3_clk, CCU_PARENT_HW(ri2s3_sysclk), RCPU2_AUDIO_I2S3_TX_RX_CLK_CTRL, ++ 4, 11, BIT(2), 0); ++CCU_GATE_DEFINE(ri2s2_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU2_AUDIO_I2S2_TX_RX_CLK_CTRL, ++ BIT(1), 0); ++CCU_GATE_DEFINE(ri2s3_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU2_AUDIO_I2S3_TX_RX_CLK_CTRL, ++ BIT(1), 0); ++/* RCPU I2SCTRL clocks end */ ++ ++/* RCPU SPICTRL clocks start */ ++static const struct clk_parent_data rspi_parents[] = { ++ CCU_PARENT_HW(pll1_aud_24p5), ++ CCU_PARENT_HW(pll1_aud_245p7), ++ CCU_PARENT_HW(pll1_d96_25p6), ++}; ++CCU_MUX_DIV_GATE_DEFINE(rspi0_clk, rspi_parents, RCPU3_SSP0_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_MUX_DIV_GATE_DEFINE(rspi1_clk, rspi_parents, RCPU3_SSP1_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_MUX_DIV_GATE_DEFINE(rspi2_clk, rspi_parents, RCPU3_PWR_SSP_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_GATE_DEFINE(rspi0_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU3_SSP0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(rspi1_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU3_SSP1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(rspi2_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU3_PWR_SSP_CLK_RST, BIT(0), 0); ++/* RCPU SPICTRL clocks end */ ++ ++/* RCPU I2CCTRL clocks start */ ++static const struct clk_parent_data ri2c_parents[] = { ++ CCU_PARENT_HW(pll1_aud_24p5), ++ CCU_PARENT_HW(pll1_aud_245p7), ++ CCU_PARENT_HW(pll1_d96_25p6), ++}; ++CCU_MUX_DIV_GATE_DEFINE(ri2c0_clk, ri2c_parents, RCPU4_I2C0_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_MUX_DIV_GATE_DEFINE(ri2c1_clk, ri2c_parents, RCPU4_I2C1_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_MUX_DIV_GATE_DEFINE(ri2c2_clk, ri2c_parents, RCPU4_PWR_I2C_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_GATE_DEFINE(ri2c0_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU4_I2C0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(ri2c1_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU4_I2C1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(ri2c2_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU4_PWR_I2C_CLK_RST, BIT(0), 0); ++/* RCPU I2CCTRL clocks end */ ++ ++/* RCPU PWMCTRL clocks start */ ++static const struct clk_parent_data rpwm_parents[] = { ++ CCU_PARENT_HW(pll1_aud_245p7), ++ CCU_PARENT_HW(pll1_aud_24p5), ++}; ++CCU_MUX_DIV_GATE_DEFINE(rpwm0_clk, rpwm_parents, RCPU6_PWM0_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_MUX_DIV_GATE_DEFINE(rpwm1_clk, rpwm_parents, RCPU6_PWM1_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_MUX_DIV_GATE_DEFINE(rpwm2_clk, rpwm_parents, RCPU6_PWM2_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_MUX_DIV_GATE_DEFINE(rpwm3_clk, rpwm_parents, RCPU6_PWM3_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_MUX_DIV_GATE_DEFINE(rpwm4_clk, rpwm_parents, RCPU6_PWM4_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_MUX_DIV_GATE_DEFINE(rpwm5_clk, rpwm_parents, RCPU6_PWM5_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_MUX_DIV_GATE_DEFINE(rpwm6_clk, rpwm_parents, RCPU6_PWM6_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_MUX_DIV_GATE_DEFINE(rpwm7_clk, rpwm_parents, RCPU6_PWM7_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_MUX_DIV_GATE_DEFINE(rpwm8_clk, rpwm_parents, RCPU6_PWM8_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_MUX_DIV_GATE_DEFINE(rpwm9_clk, rpwm_parents, RCPU6_PWM9_CLK_RST, 8, 11, ++ 4, 2, BIT(1), 0); ++CCU_GATE_DEFINE(rpwm0_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU6_PWM0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(rpwm1_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU6_PWM1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(rpwm2_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU6_PWM2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(rpwm3_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU6_PWM3_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(rpwm4_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU6_PWM4_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(rpwm5_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU6_PWM5_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(rpwm6_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU6_PWM6_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(rpwm7_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU6_PWM7_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(rpwm8_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU6_PWM8_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(rpwm9_bus_clk, CCU_PARENT_HW(rcpu_apb_clk), RCPU6_PWM9_CLK_RST, BIT(0), 0); ++/* RCPU PWMCTRL clocks end */ ++ ++/* APBC2 clocks start */ ++CCU_MUX_GATE_DEFINE(uart1_sec_clk, uart_clk_parents, APBC2_UART1_CLK_RST, 4, 3, BIT(1), 0); ++CCU_GATE_DEFINE(uart1_sec_bus_clk, CCU_PARENT_HW(apb_clk), APBC2_UART1_CLK_RST, BIT(0), 0); ++ ++CCU_MUX_DEFINE(spi2_i2s_bclk, i2s_bclk_parents, APBC2_SSP2_CLK_RST, 3, 1, 0); ++ ++static const struct clk_parent_data spi2_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(spi2_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(spi2_sec_clk, spi2_parents, APBC2_SSP2_CLK_RST, 4, 3, BIT(1), 0); ++CCU_GATE_DEFINE(spi2_sec_bus_clk, CCU_PARENT_HW(apb_clk), APBC2_SSP2_CLK_RST, BIT(0), 0); ++ ++CCU_MUX_GATE_DEFINE(twsi3_sec_clk, twsi_parents, APBC2_TWSI3_CLK_RST, 4, 3, BIT(1), 0); ++CCU_GATE_DEFINE(twsi3_sec_bus_clk, CCU_PARENT_HW(apb_clk), APBC2_TWSI3_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(rtc_sec_clk, CCU_PARENT_NAME(osc_32k), APBC2_RTC_CLK_RST, BIT(7) | BIT(1), 0); ++CCU_GATE_DEFINE(rtc_sec_bus_clk, CCU_PARENT_HW(apb_clk), APBC2_RTC_CLK_RST, BIT(0), 0); ++ ++CCU_MUX_GATE_DEFINE(timers_sec_clk, timer_parents, APBC2_TIMERS_CLK_RST, 4, 3, BIT(1), 0); ++CCU_GATE_DEFINE(timers_sec_bus_clk, CCU_PARENT_HW(apb_clk), APBC2_TIMERS_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(gpio_sec_clk, CCU_PARENT_NAME(vctcxo_24m), APBC2_GPIO_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(gpio_sec_bus_clk, CCU_PARENT_HW(apb_clk), APBC2_GPIO_CLK_RST, BIT(0), 0); ++/* APBC2 clocks end */ ++ ++static struct clk_hw *k3_ccu_pll_hws[] = { ++ [CLK_PLL1] = &pll1.common.hw, ++ [CLK_PLL2] = &pll2.common.hw, ++ [CLK_PLL3] = &pll3.common.hw, ++ [CLK_PLL4] = &pll4.common.hw, ++ [CLK_PLL5] = &pll5.common.hw, ++ [CLK_PLL6] = &pll6.common.hw, ++ [CLK_PLL7] = &pll7.common.hw, ++ [CLK_PLL8] = &pll8.common.hw, ++ [CLK_PLL1_D2] = &pll1_d2.common.hw, ++ [CLK_PLL1_D3] = &pll1_d3.common.hw, ++ [CLK_PLL1_D4] = &pll1_d4.common.hw, ++ [CLK_PLL1_D5] = &pll1_d5.common.hw, ++ [CLK_PLL1_D6] = &pll1_d6.common.hw, ++ [CLK_PLL1_D7] = &pll1_d7.common.hw, ++ [CLK_PLL1_D8] = &pll1_d8.common.hw, ++ [CLK_PLL1_DX] = &pll1_dx.common.hw, ++ [CLK_PLL1_D64] = &pll1_d64_38p4.common.hw, ++ [CLK_PLL1_D10_AUD] = &pll1_aud_245p7.common.hw, ++ [CLK_PLL1_D100_AUD] = &pll1_aud_24p5.common.hw, ++ [CLK_PLL2_D1] = &pll2_d1.common.hw, ++ [CLK_PLL2_D2] = &pll2_d2.common.hw, ++ [CLK_PLL2_D3] = &pll2_d3.common.hw, ++ [CLK_PLL2_D4] = &pll2_d4.common.hw, ++ [CLK_PLL2_D5] = &pll2_d5.common.hw, ++ [CLK_PLL2_D6] = &pll2_d6.common.hw, ++ [CLK_PLL2_D7] = &pll2_d7.common.hw, ++ [CLK_PLL2_D8] = &pll2_d8.common.hw, ++ [CLK_PLL2_66] = &pll2_66.common.hw, ++ [CLK_PLL2_33] = &pll2_33.common.hw, ++ [CLK_PLL2_50] = &pll2_50.common.hw, ++ [CLK_PLL2_25] = &pll2_25.common.hw, ++ [CLK_PLL2_20] = &pll2_20.common.hw, ++ [CLK_PLL2_D24_125] = &pll2_d24_125.common.hw, ++ [CLK_PLL2_D120_25] = &pll2_d120_25.common.hw, ++ [CLK_PLL3_D1] = &pll3_d1.common.hw, ++ [CLK_PLL3_D2] = &pll3_d2.common.hw, ++ [CLK_PLL3_D3] = &pll3_d3.common.hw, ++ [CLK_PLL3_D4] = &pll3_d4.common.hw, ++ [CLK_PLL3_D5] = &pll3_d5.common.hw, ++ [CLK_PLL3_D6] = &pll3_d6.common.hw, ++ [CLK_PLL3_D7] = &pll3_d7.common.hw, ++ [CLK_PLL3_D8] = &pll3_d8.common.hw, ++ [CLK_PLL4_D1] = &pll4_d1.common.hw, ++ [CLK_PLL4_D2] = &pll4_d2.common.hw, ++ [CLK_PLL4_D3] = &pll4_d3.common.hw, ++ [CLK_PLL4_D4] = &pll4_d4.common.hw, ++ [CLK_PLL4_D5] = &pll4_d5.common.hw, ++ [CLK_PLL4_D6] = &pll4_d6.common.hw, ++ [CLK_PLL4_D7] = &pll4_d7.common.hw, ++ [CLK_PLL4_D8] = &pll4_d8.common.hw, ++ [CLK_PLL5_D1] = &pll5_d1.common.hw, ++ [CLK_PLL5_D2] = &pll5_d2.common.hw, ++ [CLK_PLL5_D3] = &pll5_d3.common.hw, ++ [CLK_PLL5_D4] = &pll5_d4.common.hw, ++ [CLK_PLL5_D5] = &pll5_d5.common.hw, ++ [CLK_PLL5_D6] = &pll5_d6.common.hw, ++ [CLK_PLL5_D7] = &pll5_d7.common.hw, ++ [CLK_PLL5_D8] = &pll5_d8.common.hw, ++ [CLK_PLL6_D1] = &pll6_d1.common.hw, ++ [CLK_PLL6_D2] = &pll6_d2.common.hw, ++ [CLK_PLL6_D3] = &pll6_d3.common.hw, ++ [CLK_PLL6_D4] = &pll6_d4.common.hw, ++ [CLK_PLL6_D5] = &pll6_d5.common.hw, ++ [CLK_PLL6_D6] = &pll6_d6.common.hw, ++ [CLK_PLL6_D7] = &pll6_d7.common.hw, ++ [CLK_PLL6_D8] = &pll6_d8.common.hw, ++ [CLK_PLL6_80] = &pll6_80.common.hw, ++ [CLK_PLL6_40] = &pll6_40.common.hw, ++ [CLK_PLL6_20] = &pll6_20.common.hw, ++ [CLK_PLL7_D1] = &pll7_d1.common.hw, ++ [CLK_PLL7_D2] = &pll7_d2.common.hw, ++ [CLK_PLL7_D3] = &pll7_d3.common.hw, ++ [CLK_PLL7_D4] = &pll7_d4.common.hw, ++ [CLK_PLL7_D5] = &pll7_d5.common.hw, ++ [CLK_PLL7_D6] = &pll7_d6.common.hw, ++ [CLK_PLL7_D7] = &pll7_d7.common.hw, ++ [CLK_PLL7_D8] = &pll7_d8.common.hw, ++ [CLK_PLL8_D1] = &pll8_d1.common.hw, ++ [CLK_PLL8_D2] = &pll8_d2.common.hw, ++ [CLK_PLL8_D3] = &pll8_d3.common.hw, ++ [CLK_PLL8_D4] = &pll8_d4.common.hw, ++ [CLK_PLL8_D5] = &pll8_d5.common.hw, ++ [CLK_PLL8_D6] = &pll8_d6.common.hw, ++ [CLK_PLL8_D7] = &pll8_d7.common.hw, ++ [CLK_PLL8_D8] = &pll8_d8.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k3_ccu_pll_data = { ++ /* The PLL CCU implements no resets */ ++ .hws = k3_ccu_pll_hws, ++ .num = ARRAY_SIZE(k3_ccu_pll_hws), ++}; ++ ++static struct clk_hw *k3_ccu_mpmu_hws[] = { ++ [CLK_MPMU_PLL1_307P2] = &pll1_d8_307p2.common.hw, ++ [CLK_MPMU_PLL1_76P8] = &pll1_d32_76p8.common.hw, ++ [CLK_MPMU_PLL1_61P44] = &pll1_d40_61p44.common.hw, ++ [CLK_MPMU_PLL1_153P6] = &pll1_d16_153p6.common.hw, ++ [CLK_MPMU_PLL1_102P4] = &pll1_d24_102p4.common.hw, ++ [CLK_MPMU_PLL1_51P2] = &pll1_d48_51p2.common.hw, ++ [CLK_MPMU_PLL1_51P2_AP] = &pll1_d48_51p2_ap.common.hw, ++ [CLK_MPMU_PLL1_57P6] = &pll1_m3d128_57p6.common.hw, ++ [CLK_MPMU_PLL1_25P6] = &pll1_d96_25p6.common.hw, ++ [CLK_MPMU_PLL1_12P8] = &pll1_d192_12p8.common.hw, ++ [CLK_MPMU_PLL1_12P8_WDT] = &pll1_d192_12p8_wdt.common.hw, ++ [CLK_MPMU_PLL1_6P4] = &pll1_d384_6p4.common.hw, ++ [CLK_MPMU_PLL1_3P2] = &pll1_d768_3p2.common.hw, ++ [CLK_MPMU_PLL1_1P6] = &pll1_d1536_1p6.common.hw, ++ [CLK_MPMU_PLL1_0P8] = &pll1_d3072_0p8.common.hw, ++ [CLK_MPMU_PLL1_409P6] = &pll1_d6_409p6.common.hw, ++ [CLK_MPMU_PLL1_204P8] = &pll1_d12_204p8.common.hw, ++ [CLK_MPMU_PLL1_491] = &pll1_d5_491p52.common.hw, ++ [CLK_MPMU_PLL1_245P76] = &pll1_d10_245p76.common.hw, ++ [CLK_MPMU_PLL1_614] = &pll1_d4_614p4.common.hw, ++ [CLK_MPMU_PLL1_47P26] = &pll1_d52_47p26.common.hw, ++ [CLK_MPMU_PLL1_31P5] = &pll1_d78_31p5.common.hw, ++ [CLK_MPMU_PLL1_819] = &pll1_d3_819p2.common.hw, ++ [CLK_MPMU_PLL1_1228] = &pll1_d2_1228p8.common.hw, ++ [CLK_MPMU_APB] = &apb_clk.common.hw, ++ [CLK_MPMU_SLOW_UART] = &slow_uart.common.hw, ++ [CLK_MPMU_SLOW_UART1] = &slow_uart1_14p74.common.hw, ++ [CLK_MPMU_SLOW_UART2] = &slow_uart2_48.common.hw, ++ [CLK_MPMU_WDT] = &wdt_clk.common.hw, ++ [CLK_MPMU_WDT_BUS] = &wdt_bus_clk.common.hw, ++ [CLK_MPMU_RIPC] = &r_ipc_clk.common.hw, ++ [CLK_MPMU_I2S_153P6] = &i2s_153p6.common.hw, ++ [CLK_MPMU_I2S_153P6_BASE] = &i2s_153p6_base.common.hw, ++ [CLK_MPMU_I2S_SYSCLK_SRC] = &i2s_sysclk_src.common.hw, ++ [CLK_MPMU_I2S1_SYSCLK] = &i2s1_sysclk.common.hw, ++ [CLK_MPMU_I2S_BCLK_FACTOR] = &i2s_bclk_factor.common.hw, ++ [CLK_MPMU_I2S_BCLK] = &i2s_bclk.common.hw, ++ [CLK_MPMU_I2S0_SYSCLK_SEL] = &i2s0_sysclk_sel.common.hw, ++ [CLK_MPMU_I2S2_SYSCLK_SEL] = &i2s2_sysclk_sel.common.hw, ++ [CLK_MPMU_I2S3_SYSCLK_SEL] = &i2s3_sysclk_sel.common.hw, ++ [CLK_MPMU_I2S4_SYSCLK_SEL] = &i2s4_sysclk_sel.common.hw, ++ [CLK_MPMU_I2S5_SYSCLK_SEL] = &i2s5_sysclk_sel.common.hw, ++ [CLK_MPMU_I2S0_SYSCLK_DIV] = &i2s0_sysclk_div.common.hw, ++ [CLK_MPMU_I2S2_SYSCLK_DIV] = &i2s2_sysclk_div.common.hw, ++ [CLK_MPMU_I2S3_SYSCLK_DIV] = &i2s3_sysclk_div.common.hw, ++ [CLK_MPMU_I2S4_SYSCLK_DIV] = &i2s4_sysclk_div.common.hw, ++ [CLK_MPMU_I2S5_SYSCLK_DIV] = &i2s5_sysclk_div.common.hw, ++ [CLK_MPMU_I2S0_SYSCLK] = &i2s0_sysclk.common.hw, ++ [CLK_MPMU_I2S2_SYSCLK] = &i2s2_sysclk.common.hw, ++ [CLK_MPMU_I2S3_SYSCLK] = &i2s3_sysclk.common.hw, ++ [CLK_MPMU_I2S4_SYSCLK] = &i2s4_sysclk.common.hw, ++ [CLK_MPMU_I2S5_SYSCLK] = &i2s5_sysclk.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k3_ccu_mpmu_data = { ++ .reset_name = "mpmu-reset", ++ .hws = k3_ccu_mpmu_hws, ++ .num = ARRAY_SIZE(k3_ccu_mpmu_hws), ++}; ++ ++static struct clk_hw *k3_ccu_apbc_hws[] = { ++ [CLK_APBC_UART0] = &uart0_clk.common.hw, ++ [CLK_APBC_UART2] = &uart2_clk.common.hw, ++ [CLK_APBC_UART3] = &uart3_clk.common.hw, ++ [CLK_APBC_UART4] = &uart4_clk.common.hw, ++ [CLK_APBC_UART5] = &uart5_clk.common.hw, ++ [CLK_APBC_UART6] = &uart6_clk.common.hw, ++ [CLK_APBC_UART7] = &uart7_clk.common.hw, ++ [CLK_APBC_UART8] = &uart8_clk.common.hw, ++ [CLK_APBC_UART9] = &uart9_clk.common.hw, ++ [CLK_APBC_UART10] = &uart10_clk.common.hw, ++ [CLK_APBC_UART0_BUS] = &uart0_bus_clk.common.hw, ++ [CLK_APBC_UART2_BUS] = &uart2_bus_clk.common.hw, ++ [CLK_APBC_UART3_BUS] = &uart3_bus_clk.common.hw, ++ [CLK_APBC_UART4_BUS] = &uart4_bus_clk.common.hw, ++ [CLK_APBC_UART5_BUS] = &uart5_bus_clk.common.hw, ++ [CLK_APBC_UART6_BUS] = &uart6_bus_clk.common.hw, ++ [CLK_APBC_UART7_BUS] = &uart7_bus_clk.common.hw, ++ [CLK_APBC_UART8_BUS] = &uart8_bus_clk.common.hw, ++ [CLK_APBC_UART9_BUS] = &uart9_bus_clk.common.hw, ++ [CLK_APBC_UART10_BUS] = &uart10_bus_clk.common.hw, ++ [CLK_APBC_GPIO] = &gpio_clk.common.hw, ++ [CLK_APBC_GPIO_BUS] = &gpio_bus_clk.common.hw, ++ [CLK_APBC_PWM0] = &pwm0_clk.common.hw, ++ [CLK_APBC_PWM1] = &pwm1_clk.common.hw, ++ [CLK_APBC_PWM2] = &pwm2_clk.common.hw, ++ [CLK_APBC_PWM3] = &pwm3_clk.common.hw, ++ [CLK_APBC_PWM4] = &pwm4_clk.common.hw, ++ [CLK_APBC_PWM5] = &pwm5_clk.common.hw, ++ [CLK_APBC_PWM6] = &pwm6_clk.common.hw, ++ [CLK_APBC_PWM7] = &pwm7_clk.common.hw, ++ [CLK_APBC_PWM8] = &pwm8_clk.common.hw, ++ [CLK_APBC_PWM9] = &pwm9_clk.common.hw, ++ [CLK_APBC_PWM10] = &pwm10_clk.common.hw, ++ [CLK_APBC_PWM11] = &pwm11_clk.common.hw, ++ [CLK_APBC_PWM12] = &pwm12_clk.common.hw, ++ [CLK_APBC_PWM13] = &pwm13_clk.common.hw, ++ [CLK_APBC_PWM14] = &pwm14_clk.common.hw, ++ [CLK_APBC_PWM15] = &pwm15_clk.common.hw, ++ [CLK_APBC_PWM16] = &pwm16_clk.common.hw, ++ [CLK_APBC_PWM17] = &pwm17_clk.common.hw, ++ [CLK_APBC_PWM18] = &pwm18_clk.common.hw, ++ [CLK_APBC_PWM19] = &pwm19_clk.common.hw, ++ [CLK_APBC_PWM0_BUS] = &pwm0_bus_clk.common.hw, ++ [CLK_APBC_PWM1_BUS] = &pwm1_bus_clk.common.hw, ++ [CLK_APBC_PWM2_BUS] = &pwm2_bus_clk.common.hw, ++ [CLK_APBC_PWM3_BUS] = &pwm3_bus_clk.common.hw, ++ [CLK_APBC_PWM4_BUS] = &pwm4_bus_clk.common.hw, ++ [CLK_APBC_PWM5_BUS] = &pwm5_bus_clk.common.hw, ++ [CLK_APBC_PWM6_BUS] = &pwm6_bus_clk.common.hw, ++ [CLK_APBC_PWM7_BUS] = &pwm7_bus_clk.common.hw, ++ [CLK_APBC_PWM8_BUS] = &pwm8_bus_clk.common.hw, ++ [CLK_APBC_PWM9_BUS] = &pwm9_bus_clk.common.hw, ++ [CLK_APBC_PWM10_BUS] = &pwm10_bus_clk.common.hw, ++ [CLK_APBC_PWM11_BUS] = &pwm11_bus_clk.common.hw, ++ [CLK_APBC_PWM12_BUS] = &pwm12_bus_clk.common.hw, ++ [CLK_APBC_PWM13_BUS] = &pwm13_bus_clk.common.hw, ++ [CLK_APBC_PWM14_BUS] = &pwm14_bus_clk.common.hw, ++ [CLK_APBC_PWM15_BUS] = &pwm15_bus_clk.common.hw, ++ [CLK_APBC_PWM16_BUS] = &pwm16_bus_clk.common.hw, ++ [CLK_APBC_PWM17_BUS] = &pwm17_bus_clk.common.hw, ++ [CLK_APBC_PWM18_BUS] = &pwm18_bus_clk.common.hw, ++ [CLK_APBC_PWM19_BUS] = &pwm19_bus_clk.common.hw, ++ [CLK_APBC_SPI0_I2S_BCLK] = &spi0_i2s_bclk.common.hw, ++ [CLK_APBC_SPI1_I2S_BCLK] = &spi1_i2s_bclk.common.hw, ++ [CLK_APBC_SPI3_I2S_BCLK] = &spi3_i2s_bclk.common.hw, ++ [CLK_APBC_SPI0] = &spi0_clk.common.hw, ++ [CLK_APBC_SPI1] = &spi1_clk.common.hw, ++ [CLK_APBC_SPI3] = &spi3_clk.common.hw, ++ [CLK_APBC_SPI0_BUS] = &spi0_bus_clk.common.hw, ++ [CLK_APBC_SPI1_BUS] = &spi1_bus_clk.common.hw, ++ [CLK_APBC_SPI3_BUS] = &spi3_bus_clk.common.hw, ++ [CLK_APBC_RTC] = &rtc_clk.common.hw, ++ [CLK_APBC_RTC_BUS] = &rtc_bus_clk.common.hw, ++ [CLK_APBC_TWSI0] = &twsi0_clk.common.hw, ++ [CLK_APBC_TWSI1] = &twsi1_clk.common.hw, ++ [CLK_APBC_TWSI2] = &twsi2_clk.common.hw, ++ [CLK_APBC_TWSI4] = &twsi4_clk.common.hw, ++ [CLK_APBC_TWSI5] = &twsi5_clk.common.hw, ++ [CLK_APBC_TWSI6] = &twsi6_clk.common.hw, ++ [CLK_APBC_TWSI8] = &twsi8_clk.common.hw, ++ [CLK_APBC_TWSI0_BUS] = &twsi0_bus_clk.common.hw, ++ [CLK_APBC_TWSI1_BUS] = &twsi1_bus_clk.common.hw, ++ [CLK_APBC_TWSI2_BUS] = &twsi2_bus_clk.common.hw, ++ [CLK_APBC_TWSI4_BUS] = &twsi4_bus_clk.common.hw, ++ [CLK_APBC_TWSI5_BUS] = &twsi5_bus_clk.common.hw, ++ [CLK_APBC_TWSI6_BUS] = &twsi6_bus_clk.common.hw, ++ [CLK_APBC_TWSI8_BUS] = &twsi8_bus_clk.common.hw, ++ [CLK_APBC_TIMERS0] = &timers0_clk.common.hw, ++ [CLK_APBC_TIMERS1] = &timers1_clk.common.hw, ++ [CLK_APBC_TIMERS2] = &timers2_clk.common.hw, ++ [CLK_APBC_TIMERS3] = &timers3_clk.common.hw, ++ [CLK_APBC_TIMERS4] = &timers4_clk.common.hw, ++ [CLK_APBC_TIMERS5] = &timers5_clk.common.hw, ++ [CLK_APBC_TIMERS6] = &timers6_clk.common.hw, ++ [CLK_APBC_TIMERS7] = &timers7_clk.common.hw, ++ [CLK_APBC_TIMERS0_BUS] = &timers0_bus_clk.common.hw, ++ [CLK_APBC_TIMERS1_BUS] = &timers1_bus_clk.common.hw, ++ [CLK_APBC_TIMERS2_BUS] = &timers2_bus_clk.common.hw, ++ [CLK_APBC_TIMERS3_BUS] = &timers3_bus_clk.common.hw, ++ [CLK_APBC_TIMERS4_BUS] = &timers4_bus_clk.common.hw, ++ [CLK_APBC_TIMERS5_BUS] = &timers5_bus_clk.common.hw, ++ [CLK_APBC_TIMERS6_BUS] = &timers6_bus_clk.common.hw, ++ [CLK_APBC_TIMERS7_BUS] = &timers7_bus_clk.common.hw, ++ [CLK_APBC_AIB] = &aib_clk.common.hw, ++ [CLK_APBC_AIB_BUS] = &aib_bus_clk.common.hw, ++ [CLK_APBC_ONEWIRE] = &onewire_clk.common.hw, ++ [CLK_APBC_ONEWIRE_BUS] = &onewire_bus_clk.common.hw, ++ [CLK_APBC_I2S0_BCLK] = &i2s0_i2s_bclk.common.hw, ++ [CLK_APBC_I2S1_BCLK] = &i2s1_i2s_bclk.common.hw, ++ [CLK_APBC_I2S2_BCLK] = &i2s2_i2s_bclk.common.hw, ++ [CLK_APBC_I2S3_BCLK] = &i2s3_i2s_bclk.common.hw, ++ [CLK_APBC_I2S4_BCLK] = &i2s4_i2s_bclk.common.hw, ++ [CLK_APBC_I2S5_BCLK] = &i2s5_i2s_bclk.common.hw, ++ [CLK_APBC_I2S0] = &i2s0_clk.common.hw, ++ [CLK_APBC_I2S1] = &i2s1_clk.common.hw, ++ [CLK_APBC_I2S2] = &i2s2_clk.common.hw, ++ [CLK_APBC_I2S3] = &i2s3_clk.common.hw, ++ [CLK_APBC_I2S4] = &i2s4_clk.common.hw, ++ [CLK_APBC_I2S5] = &i2s5_clk.common.hw, ++ [CLK_APBC_I2S0_BUS] = &i2s0_bus_clk.common.hw, ++ [CLK_APBC_I2S1_BUS] = &i2s1_bus_clk.common.hw, ++ [CLK_APBC_I2S2_BUS] = &i2s2_bus_clk.common.hw, ++ [CLK_APBC_I2S3_BUS] = &i2s3_bus_clk.common.hw, ++ [CLK_APBC_I2S4_BUS] = &i2s4_bus_clk.common.hw, ++ [CLK_APBC_I2S5_BUS] = &i2s5_bus_clk.common.hw, ++ [CLK_APBC_DRO] = &dro_clk.common.hw, ++ [CLK_APBC_IR0] = &ir0_clk.common.hw, ++ [CLK_APBC_IR1] = &ir1_clk.common.hw, ++ [CLK_APBC_TSEN] = &tsen_clk.common.hw, ++ [CLK_APBC_TSEN_BUS] = &tsen_bus_clk.common.hw, ++ [CLK_APBC_IPC_AP2RCPU] = &ipc_ap2rcpu_clk.common.hw, ++ [CLK_APBC_IPC_AP2RCPU_BUS] = &ipc_ap2rcpu_bus_clk.common.hw, ++ [CLK_APBC_CAN0] = &can0_clk.common.hw, ++ [CLK_APBC_CAN1] = &can1_clk.common.hw, ++ [CLK_APBC_CAN2] = &can2_clk.common.hw, ++ [CLK_APBC_CAN3] = &can3_clk.common.hw, ++ [CLK_APBC_CAN4] = &can4_clk.common.hw, ++ [CLK_APBC_CAN0_BUS] = &can0_bus_clk.common.hw, ++ [CLK_APBC_CAN1_BUS] = &can1_bus_clk.common.hw, ++ [CLK_APBC_CAN2_BUS] = &can2_bus_clk.common.hw, ++ [CLK_APBC_CAN3_BUS] = &can3_bus_clk.common.hw, ++ [CLK_APBC_CAN4_BUS] = &can4_bus_clk.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k3_ccu_apbc_data = { ++ .reset_name = "apbc-reset", ++ .hws = k3_ccu_apbc_hws, ++ .num = ARRAY_SIZE(k3_ccu_apbc_hws), ++}; ++ ++static struct clk_hw *k3_ccu_apmu_hws[] = { ++ [CLK_APMU_AXICLK] = &axi_clk.common.hw, ++ [CLK_APMU_CCI550] = &cci550_clk.common.hw, ++ [CLK_APMU_CPU_C0_CORE] = &cpu_c0_core_clk.common.hw, ++ [CLK_APMU_CPU_C1_CORE] = &cpu_c1_core_clk.common.hw, ++ [CLK_APMU_CPU_C2_CORE] = &cpu_c2_core_clk.common.hw, ++ [CLK_APMU_CPU_C3_CORE] = &cpu_c3_core_clk.common.hw, ++ [CLK_APMU_CCIC2PHY] = &ccic2phy_clk.common.hw, ++ [CLK_APMU_CCIC3PHY] = &ccic3phy_clk.common.hw, ++ [CLK_APMU_CSI] = &csi_clk.common.hw, ++ [CLK_APMU_ISP_BUS] = &isp_bus_clk.common.hw, ++ [CLK_APMU_D1P_1228P8] = &d1p_1228p8.common.hw, ++ [CLK_APMU_D1P_819P2] = &d1p_819p2.common.hw, ++ [CLK_APMU_D1P_614P4] = &d1p_614p4.common.hw, ++ [CLK_APMU_D1P_491P52] = &d1p_491p52.common.hw, ++ [CLK_APMU_D1P_409P6] = &d1p_409p6.common.hw, ++ [CLK_APMU_D1P_307P2] = &d1p_307p2.common.hw, ++ [CLK_APMU_D1P_245P76] = &d1p_245p76.common.hw, ++ [CLK_APMU_V2D] = &v2d_clk.common.hw, ++ [CLK_APMU_DSI_ESC] = &dsi_esc_clk.common.hw, ++ [CLK_APMU_LCD_HCLK] = &lcd_hclk.common.hw, ++ [CLK_APMU_LCD_DSC] = &lcd_dsc_clk.common.hw, ++ [CLK_APMU_LCD_PXCLK] = &lcd_pxclk.common.hw, ++ [CLK_APMU_LCD_MCLK] = &lcd_mclk.common.hw, ++ [CLK_APMU_CCIC_4X] = &ccic_4x_clk.common.hw, ++ [CLK_APMU_CCIC1PHY] = &ccic1phy_clk.common.hw, ++ [CLK_APMU_SC2_HCLK] = &sc2_hclk.common.hw, ++ [CLK_APMU_SDH_AXI] = &sdh_axi_aclk.common.hw, ++ [CLK_APMU_SDH0] = &sdh0_clk.common.hw, ++ [CLK_APMU_SDH1] = &sdh1_clk.common.hw, ++ [CLK_APMU_SDH2] = &sdh2_clk.common.hw, ++ [CLK_APMU_USB2_BUS] = &usb2_bus_clk.common.hw, ++ [CLK_APMU_USB3_PORTA_BUS] = &usb3_porta_bus_clk.common.hw, ++ [CLK_APMU_USB3_PORTB_BUS] = &usb3_portb_bus_clk.common.hw, ++ [CLK_APMU_USB3_PORTC_BUS] = &usb3_portc_bus_clk.common.hw, ++ [CLK_APMU_USB3_PORTD_BUS] = &usb3_portd_bus_clk.common.hw, ++ [CLK_APMU_QSPI] = &qspi_clk.common.hw, ++ [CLK_APMU_QSPI_BUS] = &qspi_bus_clk.common.hw, ++ [CLK_APMU_DMA] = &dma_clk.common.hw, ++ [CLK_APMU_AES_WTM] = &aes_wtm_clk.common.hw, ++ [CLK_APMU_VPU] = &vpu_clk.common.hw, ++ [CLK_APMU_DTC] = &dtc_clk.common.hw, ++ [CLK_APMU_GPU] = &gpu_clk.common.hw, ++ [CLK_APMU_MC_AHB] = &mc_ahb_clk.common.hw, ++ [CLK_APMU_TOP_DCLK] = &top_dclk.common.hw, ++ [CLK_APMU_UCIE] = &ucie_clk.common.hw, ++ [CLK_APMU_UCIE_SBCLK] = &ucie_sbclk.common.hw, ++ [CLK_APMU_RCPU] = &rcpu_clk.common.hw, ++ [CLK_APMU_DSI4LN2_DSI_ESC] = &dsi4ln2_dsi_esc_clk.common.hw, ++ [CLK_APMU_DSI4LN2_LCD_DSC] = &dsi4ln2_lcd_dsc_clk.common.hw, ++ [CLK_APMU_DSI4LN2_LCD_PXCLK] = &dsi4ln2_lcd_pxclk.common.hw, ++ [CLK_APMU_DSI4LN2_LCD_MCLK] = &dsi4ln2_lcd_mclk.common.hw, ++ [CLK_APMU_DSI4LN2_DPU_ACLK] = &dsi4ln2_dpu_aclk.common.hw, ++ [CLK_APMU_DPU_ACLK] = &dpu_aclk.common.hw, ++ [CLK_APMU_UFS_ACLK] = &ufs_aclk.common.hw, ++ [CLK_APMU_EDP0_PXCLK] = &edp0_pxclk.common.hw, ++ [CLK_APMU_EDP1_PXCLK] = &edp1_pxclk.common.hw, ++ [CLK_APMU_PCIE_PORTA_MSTE] = &pciea_mstr_clk.common.hw, ++ [CLK_APMU_PCIE_PORTA_SLV] = &pciea_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTB_MSTE] = &pcieb_mstr_clk.common.hw, ++ [CLK_APMU_PCIE_PORTB_SLV] = &pcieb_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTC_MSTE] = &pciec_mstr_clk.common.hw, ++ [CLK_APMU_PCIE_PORTC_SLV] = &pciec_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTD_MSTE] = &pcied_mstr_clk.common.hw, ++ [CLK_APMU_PCIE_PORTD_SLV] = &pcied_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTE_MSTE] = &pciee_mstr_clk.common.hw, ++ [CLK_APMU_PCIE_PORTE_SLV] = &pciee_slv_clk.common.hw, ++ [CLK_APMU_EMAC0_BUS] = &emac0_bus_clk.common.hw, ++ [CLK_APMU_EMAC0_REF] = &emac0_ref_clk.common.hw, ++ [CLK_APMU_EMAC0_1588] = &emac0_1588_clk.common.hw, ++ [CLK_APMU_EMAC0_RGMII_TX] = &emac0_rgmii_tx_clk.common.hw, ++ [CLK_APMU_EMAC1_BUS] = &emac1_bus_clk.common.hw, ++ [CLK_APMU_EMAC1_REF] = &emac1_ref_clk.common.hw, ++ [CLK_APMU_EMAC1_1588] = &emac1_1588_clk.common.hw, ++ [CLK_APMU_EMAC1_RGMII_TX] = &emac1_rgmii_tx_clk.common.hw, ++ [CLK_APMU_EMAC2_BUS] = &emac2_bus_clk.common.hw, ++ [CLK_APMU_EMAC2_REF] = &emac2_ref_clk.common.hw, ++ [CLK_APMU_EMAC2_1588] = &emac2_1588_clk.common.hw, ++ [CLK_APMU_EMAC2_RGMII_TX] = &emac2_rgmii_tx_clk.common.hw, ++ [CLK_APMU_ESPI_SCLK_SRC] = &espi_sclk_src.common.hw, ++ [CLK_APMU_ESPI_SCLK] = &espi_sclk.common.hw, ++ [CLK_APMU_ESPI_MCLK] = &espi_mclk.common.hw, ++ [CLK_APMU_CAM_SRC1] = &cam_src1_clk.common.hw, ++ [CLK_APMU_CAM_SRC2] = &cam_src2_clk.common.hw, ++ [CLK_APMU_CAM_SRC3] = &cam_src3_clk.common.hw, ++ [CLK_APMU_CAM_SRC4] = &cam_src4_clk.common.hw, ++ [CLK_APMU_ISIM_VCLK0] = &isim_vclk_out0.common.hw, ++ [CLK_APMU_ISIM_VCLK1] = &isim_vclk_out1.common.hw, ++ [CLK_APMU_ISIM_VCLK2] = &isim_vclk_out2.common.hw, ++ [CLK_APMU_ISIM_VCLK3] = &isim_vclk_out3.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k3_ccu_apmu_data = { ++ .reset_name = "apmu-reset", ++ .hws = k3_ccu_apmu_hws, ++ .num = ARRAY_SIZE(k3_ccu_apmu_hws), ++}; ++ ++static struct clk_hw *k3_ccu_dciu_hws[] = { ++ [CLK_DCIU_HDMA] = &hdma_clk.common.hw, ++ [CLK_DCIU_DMA350] = &dma350_clk.common.hw, ++ [CLK_DCIU_C2_TCM_PIPE] = &c2_tcm_pipe_clk.common.hw, ++ [CLK_DCIU_C3_TCM_PIPE] = &c3_tcm_pipe_clk.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k3_ccu_dciu_data = { ++ .reset_name = "dciu-reset", ++ .hws = k3_ccu_dciu_hws, ++ .num = ARRAY_SIZE(k3_ccu_dciu_hws), ++}; ++ ++static struct clk_hw *k3_ccu_rcpu_sysctrl_hws[] = { ++ [CLK_RCPU_SYSCTRL_RCAN0] = &rcan0_clk.common.hw, ++ [CLK_RCPU_SYSCTRL_RCAN1] = &rcan1_clk.common.hw, ++ [CLK_RCPU_SYSCTRL_RCAN2] = &rcan2_clk.common.hw, ++ [CLK_RCPU_SYSCTRL_RCAN3] = &rcan3_clk.common.hw, ++ [CLK_RCPU_SYSCTRL_RCAN4] = &rcan4_clk.common.hw, ++ [CLK_RCPU_SYSCTRL_RCAN0_BUS] = &rcan0_bus_clk.common.hw, ++ [CLK_RCPU_SYSCTRL_RCAN1_BUS] = &rcan1_bus_clk.common.hw, ++ [CLK_RCPU_SYSCTRL_RCAN2_BUS] = &rcan2_bus_clk.common.hw, ++ [CLK_RCPU_SYSCTRL_RCAN3_BUS] = &rcan3_bus_clk.common.hw, ++ [CLK_RCPU_SYSCTRL_RCAN4_BUS] = &rcan4_bus_clk.common.hw, ++ [CLK_RCPU_SYSCTRL_RIRC0] = &rirc0_clk.common.hw, ++ [CLK_RCPU_SYSCTRL_RIRC1] = &rirc1_clk.common.hw, ++ [CLK_RCPU_SYSCTRL_RESPI_SCLK_SRC] = &respi_sclk_src.common.hw, ++ [CLK_RCPU_SYSCTRL_RESPI_SCLK] = &respi_sclk.common.hw, ++ [CLK_RCPU_SYSCTRL_REMAC_BUS] = &remac_bus_clk.common.hw, ++ [CLK_RCPU_SYSCTRL_REMAC_REF] = &remac_ref_clk.common.hw, ++ [CLK_RCPU_SYSCTRL_REMAC_1588] = &remac_1588_clk.common.hw, ++ [CLK_RCPU_SYSCTRL_REMAC_RGMII_TX] = &remac_rgmii_tx_clk.common.hw, ++ [CLK_RCPU_SYSCTRL_RI2S0_SYSCLK] = &ri2s0_sysclk.common.hw, ++ [CLK_RCPU_SYSCTRL_RI2S1_SYSCLK] = &ri2s1_sysclk.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k3_ccu_rcpu_sysctrl_data = { ++ .reset_name = "rsysctrl-reset", ++ .hws = k3_ccu_rcpu_sysctrl_hws, ++ .num = ARRAY_SIZE(k3_ccu_rcpu_sysctrl_hws), ++}; ++ ++static struct clk_hw *k3_ccu_rcpu_uartctrl_hws[] = { ++ [CLK_RCPU_UARTCTRL_RUART0] = &ruart0_clk.common.hw, ++ [CLK_RCPU_UARTCTRL_RUART1] = &ruart1_clk.common.hw, ++ [CLK_RCPU_UARTCTRL_RUART2] = &ruart2_clk.common.hw, ++ [CLK_RCPU_UARTCTRL_RUART3] = &ruart3_clk.common.hw, ++ [CLK_RCPU_UARTCTRL_RUART4] = &ruart4_clk.common.hw, ++ [CLK_RCPU_UARTCTRL_RUART5] = &ruart5_clk.common.hw, ++ [CLK_RCPU_UARTCTRL_RUART0_BUS] = &ruart0_bus_clk.common.hw, ++ [CLK_RCPU_UARTCTRL_RUART1_BUS] = &ruart1_bus_clk.common.hw, ++ [CLK_RCPU_UARTCTRL_RUART2_BUS] = &ruart2_bus_clk.common.hw, ++ [CLK_RCPU_UARTCTRL_RUART3_BUS] = &ruart3_bus_clk.common.hw, ++ [CLK_RCPU_UARTCTRL_RUART4_BUS] = &ruart4_bus_clk.common.hw, ++ [CLK_RCPU_UARTCTRL_RUART5_BUS] = &ruart5_bus_clk.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k3_ccu_rcpu_uartctrl_data = { ++ .reset_name = "ruartctrl-reset", ++ .hws = k3_ccu_rcpu_uartctrl_hws, ++ .num = ARRAY_SIZE(k3_ccu_rcpu_uartctrl_hws), ++}; ++ ++static struct clk_hw *k3_ccu_rcpu_i2sctrl_hws[] = { ++ [CLK_RCPU_I2SCTRL_RI2S0] = &ri2s0_clk.common.hw, ++ [CLK_RCPU_I2SCTRL_RI2S1] = &ri2s1_clk.common.hw, ++ [CLK_RCPU_I2SCTRL_RI2S2] = &ri2s2_clk.common.hw, ++ [CLK_RCPU_I2SCTRL_RI2S3] = &ri2s3_clk.common.hw, ++ [CLK_RCPU_I2SCTRL_RI2S0_BUS] = &ri2s0_bus_clk.common.hw, ++ [CLK_RCPU_I2SCTRL_RI2S1_BUS] = &ri2s1_bus_clk.common.hw, ++ [CLK_RCPU_I2SCTRL_RI2S2_BUS] = &ri2s2_bus_clk.common.hw, ++ [CLK_RCPU_I2SCTRL_RI2S3_BUS] = &ri2s3_bus_clk.common.hw, ++ [CLK_RCPU_I2SCTRL_RI2S2_SYSCLK] = &ri2s2_sysclk.common.hw, ++ [CLK_RCPU_I2SCTRL_RI2S3_SYSCLK] = &ri2s3_sysclk.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k3_ccu_rcpu_i2sctrl_data = { ++ .reset_name = "ri2sctrl-reset", ++ .hws = k3_ccu_rcpu_i2sctrl_hws, ++ .num = ARRAY_SIZE(k3_ccu_rcpu_i2sctrl_hws), ++}; ++ ++static struct clk_hw *k3_ccu_rcpu_spictrl_hws[] = { ++ [CLK_RCPU_SPICTRL_RSPI0] = &rspi0_clk.common.hw, ++ [CLK_RCPU_SPICTRL_RSPI1] = &rspi1_clk.common.hw, ++ [CLK_RCPU_SPICTRL_RSPI2] = &rspi2_clk.common.hw, ++ [CLK_RCPU_SPICTRL_RSPI0_BUS] = &rspi0_bus_clk.common.hw, ++ [CLK_RCPU_SPICTRL_RSPI1_BUS] = &rspi1_bus_clk.common.hw, ++ [CLK_RCPU_SPICTRL_RSPI2_BUS] = &rspi2_bus_clk.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k3_ccu_rcpu_spictrl_data = { ++ .reset_name = "rspictrl-reset", ++ .hws = k3_ccu_rcpu_spictrl_hws, ++ .num = ARRAY_SIZE(k3_ccu_rcpu_spictrl_hws), ++}; ++ ++static struct clk_hw *k3_ccu_rcpu_i2cctrl_hws[] = { ++ [CLK_RCPU_I2CCTRL_RI2C0] = &ri2c0_clk.common.hw, ++ [CLK_RCPU_I2CCTRL_RI2C1] = &ri2c1_clk.common.hw, ++ [CLK_RCPU_I2CCTRL_RI2C2] = &ri2c2_clk.common.hw, ++ [CLK_RCPU_I2CCTRL_RI2C0_BUS] = &ri2c0_bus_clk.common.hw, ++ [CLK_RCPU_I2CCTRL_RI2C1_BUS] = &ri2c1_bus_clk.common.hw, ++ [CLK_RCPU_I2CCTRL_RI2C2_BUS] = &ri2c2_bus_clk.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k3_ccu_rcpu_i2cctrl_data = { ++ .reset_name = "ri2cctrl-reset", ++ .hws = k3_ccu_rcpu_i2cctrl_hws, ++ .num = ARRAY_SIZE(k3_ccu_rcpu_i2cctrl_hws), ++}; ++ ++static struct clk_hw *k3_ccu_rpmu_hws[] = { ++ [CLK_RPMU_RCPU_APB] = &rcpu_apb_clk.common.hw, ++ [CLK_RPMU_RCPU_AXI] = &rcpu_axi_clk.common.hw, ++ [CLK_RPMU_RIPC2MSA] = &ripc2msa_clk.common.hw, ++ [CLK_RPMU_RIPC2CP] = &ripc2cp_clk.common.hw, ++ [CLK_RPMU_RIPC2AP] = &ripc2ap_clk.common.hw, ++ [CLK_RPMU_RTIMER1] = &rtimer1_clk.common.hw, ++ [CLK_RPMU_RTIMER2] = &rtimer2_clk.common.hw, ++ [CLK_RPMU_RTIMER3] = &rtimer3_clk.common.hw, ++ [CLK_RPMU_RTIMER4] = &rtimer4_clk.common.hw, ++ [CLK_RPMU_RTIMER1_BUS] = &rtimer1_bus_clk.common.hw, ++ [CLK_RPMU_RTIMER2_BUS] = &rtimer2_bus_clk.common.hw, ++ [CLK_RPMU_RTIMER3_BUS] = &rtimer3_bus_clk.common.hw, ++ [CLK_RPMU_RTIMER4_BUS] = &rtimer4_bus_clk.common.hw, ++ [CLK_RPMU_RT24_CORE0] = &rt24_core0_clk.common.hw, ++ [CLK_RPMU_RT24_CORE1] = &rt24_core1_clk.common.hw, ++ [CLK_RPMU_RGPIO] = &rgpio_clk.common.hw, ++ [CLK_RPMU_RGPIO_EDGE] = &rgpio_edge_clk.common.hw, ++ [CLK_RPMU_RGPIO_LP] = &rgpio_lp_clk.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k3_ccu_rpmu_data = { ++ .reset_name = "rpmu-reset", ++ .hws = k3_ccu_rpmu_hws, ++ .num = ARRAY_SIZE(k3_ccu_rpmu_hws), ++}; ++ ++static struct clk_hw *k3_ccu_rcpu_pwmctrl_hws[] = { ++ [CLK_RCPU_PWMCTRL_RPWM0] = &rpwm0_clk.common.hw, ++ [CLK_RCPU_PWMCTRL_RPWM1] = &rpwm1_clk.common.hw, ++ [CLK_RCPU_PWMCTRL_RPWM2] = &rpwm2_clk.common.hw, ++ [CLK_RCPU_PWMCTRL_RPWM3] = &rpwm3_clk.common.hw, ++ [CLK_RCPU_PWMCTRL_RPWM4] = &rpwm4_clk.common.hw, ++ [CLK_RCPU_PWMCTRL_RPWM5] = &rpwm5_clk.common.hw, ++ [CLK_RCPU_PWMCTRL_RPWM6] = &rpwm6_clk.common.hw, ++ [CLK_RCPU_PWMCTRL_RPWM7] = &rpwm7_clk.common.hw, ++ [CLK_RCPU_PWMCTRL_RPWM8] = &rpwm8_clk.common.hw, ++ [CLK_RCPU_PWMCTRL_RPWM9] = &rpwm9_clk.common.hw, ++ [CLK_RCPU_PWMCTRL_RPWM0_BUS] = &rpwm0_bus_clk.common.hw, ++ [CLK_RCPU_PWMCTRL_RPWM1_BUS] = &rpwm1_bus_clk.common.hw, ++ [CLK_RCPU_PWMCTRL_RPWM2_BUS] = &rpwm2_bus_clk.common.hw, ++ [CLK_RCPU_PWMCTRL_RPWM3_BUS] = &rpwm3_bus_clk.common.hw, ++ [CLK_RCPU_PWMCTRL_RPWM4_BUS] = &rpwm4_bus_clk.common.hw, ++ [CLK_RCPU_PWMCTRL_RPWM5_BUS] = &rpwm5_bus_clk.common.hw, ++ [CLK_RCPU_PWMCTRL_RPWM6_BUS] = &rpwm6_bus_clk.common.hw, ++ [CLK_RCPU_PWMCTRL_RPWM7_BUS] = &rpwm7_bus_clk.common.hw, ++ [CLK_RCPU_PWMCTRL_RPWM8_BUS] = &rpwm8_bus_clk.common.hw, ++ [CLK_RCPU_PWMCTRL_RPWM9_BUS] = &rpwm9_bus_clk.common.hw, ++}; ++static const struct spacemit_ccu_data k3_ccu_rcpu_pwmctrl_data = { ++ .reset_name = "rpwmctrl-reset", ++ .hws = k3_ccu_rcpu_pwmctrl_hws, ++ .num = ARRAY_SIZE(k3_ccu_rcpu_pwmctrl_hws), ++}; ++ ++static struct clk_hw *k3_ccu_apbc2_hws[] = { ++ [CLK_APBC2_SEC_UART1] = &uart1_sec_clk.common.hw, ++ [CLK_APBC2_SEC_UART1_BUS] = &uart1_sec_bus_clk.common.hw, ++ [CLK_APBC2_SEC_SPI2_I2S_BCLK] = &spi2_i2s_bclk.common.hw, ++ [CLK_APBC2_SEC_SPI2] = &spi2_sec_clk.common.hw, ++ [CLK_APBC2_SEC_SPI2_BUS] = &spi2_sec_bus_clk.common.hw, ++ [CLK_APBC2_SEC_TWSI3] = &twsi3_sec_clk.common.hw, ++ [CLK_APBC2_SEC_TWSI3_BUS] = &twsi3_sec_bus_clk.common.hw, ++ [CLK_APBC2_SEC_RTC] = &rtc_sec_clk.common.hw, ++ [CLK_APBC2_SEC_RTC_BUS] = &rtc_sec_bus_clk.common.hw, ++ [CLK_APBC2_SEC_TIMERS] = &timers_sec_clk.common.hw, ++ [CLK_APBC2_SEC_TIMERS_BUS] = &timers_sec_bus_clk.common.hw, ++ [CLK_APBC2_SEC_GPIO] = &gpio_sec_clk.common.hw, ++ [CLK_APBC2_SEC_GPIO_BUS] = &gpio_sec_bus_clk.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k3_ccu_apbc2_data = { ++ .reset_name = "apbc2-reset", ++ .hws = k3_ccu_apbc2_hws, ++ .num = ARRAY_SIZE(k3_ccu_apbc2_hws), ++}; ++ ++static int spacemit_ccu_register(struct device *dev, ++ struct regmap *regmap, ++ struct regmap *lock_regmap, ++ const struct spacemit_ccu_data *data) ++{ ++ struct clk_hw_onecell_data *clk_data; ++ int i, ret; + -+static const char * const timer_sec_parent_names[] = { -+ "pll1_d192_12p8", "clk_32k", "pll1_d384_6p4", "vctcxo_3", "vctcxo_1" -+}; ++ /* Nothing to do if the CCU does not implement any clocks */ ++ if (!data->hws) ++ return 0; + -+static SPACEMIT_CCU_MUX_GATE(timers0_sec_clk, "timers0_sec_clk", -+ timer_sec_parent_names, -+ BASE_TYPE_APBC2, APBC2_TIMERS0_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static const char * const kpc_sec_parent_names[] = { -+ "pll1_d192_12p8", "clk_32k", "pll1_d384_6p4", "vctcxo_3", "vctcxo_1" -+}; -+ -+static SPACEMIT_CCU_MUX_GATE(kpc_sec_clk, "kpc_sec_clk", kpc_sec_parent_names, -+ BASE_TYPE_APBC2, APBC2_KPC_CLK_RST, -+ 4, 3, 0x3, 0x3, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_GATE(gpio_sec_clk, "gpio_sec_clk", "vctcxo_24", -+ BASE_TYPE_APBC2, APBC2_GPIO_CLK_RST, -+ 0x3, 0x3, 0x0, -+ 0); -+ -+static const char * const apb_parent_names[] = { -+ "pll1_d96_25p6", "pll1_d48_51p2", "pll1_d96_25p6", "pll1_d24_102p4" -+}; -+ -+static SPACEMIT_CCU_MUX(apb_clk, "apb_clk", apb_parent_names, -+ BASE_TYPE_MPMU, MPMU_APBCSCR, -+ 0, 2, 0); -+ -+static const char * const rhdmi_audio_parent_names[] = { -+ "pll1_aud_24p5", "pll1_aud_245p7" -+}; ++ clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num), ++ GFP_KERNEL); ++ if (!clk_data) ++ return -ENOMEM; + -+static SPACEMIT_CCU_DIV_MUX_GATE(rhdmi_audio_clk, "rhdmi_audio_clk", -+ rhdmi_audio_parent_names, -+ BASE_TYPE_RCPU, RCPU_HDMI_CLK_RST, -+ 4, 11, 16, 2, -+ 0x6, 0x6, 0x0, -+ 0); ++ clk_data->num = data->num; + -+static const char * const rcan_parent_names[] = { -+ "pll3_20", "pll3_40", "pll3_80" -+}; ++ for (i = 0; i < data->num; i++) { ++ struct clk_hw *hw = data->hws[i]; ++ struct ccu_common *common; ++ const char *name; + -+static SPACEMIT_CCU_DIV_MUX_GATE(rcan_clk, "rcan_clk", rcan_parent_names, -+ BASE_TYPE_RCPU, RCPU_CAN_CLK_RST, -+ 8, 11, 4, 2, -+ BIT(1), BIT(1), 0x0, -+ 0); ++ if (!hw) { ++ clk_data->hws[i] = ERR_PTR(-ENOENT); ++ continue; ++ } + -+static SPACEMIT_CCU_GATE_NO_PARENT(rcan_bus_clk, "rcan_bus_clk", NULL, -+ BASE_TYPE_RCPU, RCPU_CAN_CLK_RST, -+ BIT(2), BIT(2), 0x0, 0); ++ name = hw->init->name; + -+static const char * const rpwm_parent_names[] = { -+ "pll1_aud_245p7", "pll1_aud_24p5" -+}; ++ common = hw_to_ccu_common(hw); ++ common->regmap = regmap; ++ common->lock_regmap = lock_regmap; + -+static SPACEMIT_CCU_DIV_MUX_GATE(rpwm0_clk, "rpwm0_clk", rpwm_parent_names, -+ BASE_TYPE_RCPU2, RCPU2_PWM0_CLK_RST, -+ 8, 11, 4, 2, -+ BIT(1), BIT(1), 0x0, -+ 0); ++ ret = devm_clk_hw_register(dev, hw); ++ if (ret) { ++ dev_err(dev, "Cannot register clock %d - %s\n", ++ i, name); ++ return ret; ++ } + -+static SPACEMIT_CCU_DIV_MUX_GATE(rpwm1_clk, "rpwm1_clk", rpwm_parent_names, -+ BASE_TYPE_RCPU2, RCPU2_PWM1_CLK_RST, -+ 8, 11, 4, 2, -+ BIT(1), BIT(1), 0x0, -+ 0); ++ clk_data->hws[i] = hw; ++ } + -+static SPACEMIT_CCU_DIV_MUX_GATE(rpwm2_clk, "rpwm2_clk", rpwm_parent_names, -+ BASE_TYPE_RCPU2, RCPU2_PWM2_CLK_RST, -+ 8, 11, 4, 2, -+ BIT(1), BIT(1), 0x0, -+ 0); -+ -+static SPACEMIT_CCU_DIV_MUX_GATE(rpwm3_clk, "rpwm3_clk", rpwm_parent_names, -+ BASE_TYPE_RCPU2, RCPU2_PWM3_CLK_RST, -+ 8, 11, 4, 2, -+ BIT(1), BIT(1), 0x0, -+ 0); -+ -+static SPACEMIT_CCU_DIV_MUX_GATE(rpwm4_clk, "rpwm4_clk", rpwm_parent_names, -+ BASE_TYPE_RCPU2, RCPU2_PWM4_CLK_RST, -+ 8, 11, 4, 2, -+ BIT(1), BIT(1), 0x0, -+ 0); -+ -+static SPACEMIT_CCU_DIV_MUX_GATE(rpwm5_clk, "rpwm5_clk", rpwm_parent_names, -+ BASE_TYPE_RCPU2, RCPU2_PWM5_CLK_RST, -+ 8, 11, 4, 2, -+ BIT(1), BIT(1), 0x0, -+ 0); -+ -+static SPACEMIT_CCU_DIV_MUX_GATE(rpwm6_clk, "rpwm6_clk", rpwm_parent_names, -+ BASE_TYPE_RCPU2, RCPU2_PWM6_CLK_RST, -+ 8, 11, 4, 2, -+ BIT(1), BIT(1), 0x0, -+ 0); -+ -+static SPACEMIT_CCU_DIV_MUX_GATE(rpwm7_clk, "rpwm7_clk", rpwm_parent_names, -+ BASE_TYPE_RCPU2, RCPU2_PWM7_CLK_RST, -+ 8, 11, 4, 2, -+ BIT(1), BIT(1), 0x0, -+ 0); -+ -+static SPACEMIT_CCU_DIV_MUX_GATE(rpwm8_clk, "rpwm8_clk", rpwm_parent_names, -+ BASE_TYPE_RCPU2, RCPU2_PWM8_CLK_RST, -+ 8, 11, 4, 2, -+ BIT(1), BIT(1), 0x0, -+ 0); -+ -+static SPACEMIT_CCU_DIV_MUX_GATE(rpwm9_clk, "rpwm9_clk", rpwm_parent_names, -+ BASE_TYPE_RCPU2, RCPU2_PWM9_CLK_RST, -+ 8, 11, 4, 2, -+ BIT(1), BIT(1), 0x0, -+ 0); -+ -+static const char * const ri2c_parent_names[] = { -+ "pll1_d40_61p44", "pll1_d96_25p6", "pll1_d192_12p8", "vctcxo_3" -+}; -+ -+static SPACEMIT_CCU_DIV_MUX_GATE(ri2c0_clk, "ri2c0_clk", ri2c_parent_names, -+ BASE_TYPE_RCPU, RCPU_I2C0_CLK_RST, -+ 8, 11, 4, 2, -+ 0x6, 0x6, 0x0, -+ 0); -+ -+static const char * const rssp0_parent_names[] = { -+ "pll1_d40_61p44", "pll1_d96_25p6", "pll1_d192_12p8", "vctcxo_3" -+}; -+ -+static SPACEMIT_CCU_DIV_MUX_GATE(rssp0_clk, "rssp0_clk", rssp0_parent_names, -+ BASE_TYPE_RCPU, RCPU_SSP0_CLK_RST, -+ 8, 11, 4, 2, -+ 0x6, 0x6, 0x0, -+ 0); -+ -+static SPACEMIT_CCU_GATE_NO_PARENT(rir_clk, "rir_clk", NULL, -+ BASE_TYPE_RCPU, RCPU_IR_CLK_RST, -+ BIT(2), BIT(2), 0x0, -+ 0); -+ -+static const char * const ruart0_parent_names[] = { -+ "pll1_aud_24p5", "pll1_aud_245p7", "vctcxo_24", "vctcxo_3" -+}; -+ -+static SPACEMIT_CCU_DIV_MUX_GATE(ruart0_clk, "ruart0_clk", ruart0_parent_names, -+ BASE_TYPE_RCPU, RCPU_UART0_CLK_RST, -+ 8, 11, 4, 2, -+ 0x6, 0x6, 0x0, -+ 0); -+ -+static const char * const ruart1_parent_names[] = { -+ "pll1_aud_24p5", "pll1_aud_245p7", "vctcxo_24", "vctcxo_3" -+}; -+ -+static SPACEMIT_CCU_DIV_MUX_GATE(ruart1_clk, "ruart1_clk", ruart1_parent_names, -+ BASE_TYPE_RCPU, RCPU_UART1_CLK_RST, -+ 8, 11, 4, 2, -+ 0x6, 0x6, 0x0, -+ 0); -+ -+static struct clk_hw_onecell_data spacemit_k1_hw_clks = { -+ .hws = { -+ [CLK_PLL2] = &pll2.common.hw, -+ [CLK_PLL3] = &pll3.common.hw, -+ [CLK_PLL1_D2] = &pll1_d2.common.hw, -+ [CLK_PLL1_D3] = &pll1_d3.common.hw, -+ [CLK_PLL1_D4] = &pll1_d4.common.hw, -+ [CLK_PLL1_D5] = &pll1_d5.common.hw, -+ [CLK_PLL1_D6] = &pll1_d6.common.hw, -+ [CLK_PLL1_D7] = &pll1_d7.common.hw, -+ [CLK_PLL1_D8] = &pll1_d8.common.hw, -+ [CLK_PLL1_D11] = &pll1_d11_223p4.common.hw, -+ [CLK_PLL1_D13] = &pll1_d13_189.common.hw, -+ [CLK_PLL1_D23] = &pll1_d23_106p8.common.hw, -+ [CLK_PLL1_D64] = &pll1_d64_38p4.common.hw, -+ [CLK_PLL1_D10_AUD] = &pll1_aud_245p7.common.hw, -+ [CLK_PLL1_D100_AUD] = &pll1_aud_24p5.common.hw, -+ [CLK_PLL2_D1] = &pll2_d1.common.hw, -+ [CLK_PLL2_D2] = &pll2_d2.common.hw, -+ [CLK_PLL2_D3] = &pll2_d3.common.hw, -+ [CLK_PLL2_D4] = &pll2_d4.common.hw, -+ [CLK_PLL2_D5] = &pll2_d5.common.hw, -+ [CLK_PLL2_D6] = &pll2_d6.common.hw, -+ [CLK_PLL2_D7] = &pll2_d7.common.hw, -+ [CLK_PLL2_D8] = &pll2_d8.common.hw, -+ [CLK_PLL3_D1] = &pll3_d1.common.hw, -+ [CLK_PLL3_D2] = &pll3_d2.common.hw, -+ [CLK_PLL3_D3] = &pll3_d3.common.hw, -+ [CLK_PLL3_D4] = &pll3_d4.common.hw, -+ [CLK_PLL3_D5] = &pll3_d5.common.hw, -+ [CLK_PLL3_D6] = &pll3_d6.common.hw, -+ [CLK_PLL3_D7] = &pll3_d7.common.hw, -+ [CLK_PLL3_D8] = &pll3_d8.common.hw, -+ [CLK_PLL3_80] = &pll3_80.common.hw, -+ [CLK_PLL3_40] = &pll3_40.common.hw, -+ [CLK_PLL3_20] = &pll3_20.common.hw, -+ [CLK_PLL1_307P2] = &pll1_d8_307p2.common.hw, -+ [CLK_PLL1_76P8] = &pll1_d32_76p8.common.hw, -+ [CLK_PLL1_61P44] = &pll1_d40_61p44.common.hw, -+ [CLK_PLL1_153P6] = &pll1_d16_153p6.common.hw, -+ [CLK_PLL1_102P4] = &pll1_d24_102p4.common.hw, -+ [CLK_PLL1_51P2] = &pll1_d48_51p2.common.hw, -+ [CLK_PLL1_51P2_AP] = &pll1_d48_51p2_ap.common.hw, -+ [CLK_PLL1_57P6] = &pll1_m3d128_57p6.common.hw, -+ [CLK_PLL1_25P6] = &pll1_d96_25p6.common.hw, -+ [CLK_PLL1_12P8] = &pll1_d192_12p8.common.hw, -+ [CLK_PLL1_12P8_WDT] = &pll1_d192_12p8_wdt.common.hw, -+ [CLK_PLL1_6P4] = &pll1_d384_6p4.common.hw, -+ [CLK_PLL1_3P2] = &pll1_d768_3p2.common.hw, -+ [CLK_PLL1_1P6] = &pll1_d1536_1p6.common.hw, -+ [CLK_PLL1_0P8] = &pll1_d3072_0p8.common.hw, -+ [CLK_PLL1_351] = &pll1_d7_351p08.common.hw, -+ [CLK_PLL1_409P6] = &pll1_d6_409p6.common.hw, -+ [CLK_PLL1_204P8] = &pll1_d12_204p8.common.hw, -+ [CLK_PLL1_491] = &pll1_d5_491p52.common.hw, -+ [CLK_PLL1_245P76] = &pll1_d10_245p76.common.hw, -+ [CLK_PLL1_614] = &pll1_d4_614p4.common.hw, -+ [CLK_PLL1_47P26] = &pll1_d52_47p26.common.hw, -+ [CLK_PLL1_31P5] = &pll1_d78_31p5.common.hw, -+ [CLK_PLL1_819] = &pll1_d3_819p2.common.hw, -+ [CLK_PLL1_1228] = &pll1_d2_1228p8.common.hw, -+ [CLK_SLOW_UART1] = &slow_uart1_14p74.common.hw, -+ [CLK_SLOW_UART2] = &slow_uart2_48.common.hw, -+ [CLK_UART1] = &uart1_clk.common.hw, -+ [CLK_UART2] = &uart2_clk.common.hw, -+ [CLK_UART3] = &uart3_clk.common.hw, -+ [CLK_UART4] = &uart4_clk.common.hw, -+ [CLK_UART5] = &uart5_clk.common.hw, -+ [CLK_UART6] = &uart6_clk.common.hw, -+ [CLK_UART7] = &uart7_clk.common.hw, -+ [CLK_UART8] = &uart8_clk.common.hw, -+ [CLK_UART9] = &uart9_clk.common.hw, -+ [CLK_GPIO] = &gpio_clk.common.hw, -+ [CLK_PWM0] = &pwm0_clk.common.hw, -+ [CLK_PWM1] = &pwm1_clk.common.hw, -+ [CLK_PWM2] = &pwm2_clk.common.hw, -+ [CLK_PWM3] = &pwm3_clk.common.hw, -+ [CLK_PWM4] = &pwm4_clk.common.hw, -+ [CLK_PWM5] = &pwm5_clk.common.hw, -+ [CLK_PWM6] = &pwm6_clk.common.hw, -+ [CLK_PWM7] = &pwm7_clk.common.hw, -+ [CLK_PWM8] = &pwm8_clk.common.hw, -+ [CLK_PWM9] = &pwm9_clk.common.hw, -+ [CLK_PWM10] = &pwm10_clk.common.hw, -+ [CLK_PWM11] = &pwm11_clk.common.hw, -+ [CLK_PWM12] = &pwm12_clk.common.hw, -+ [CLK_PWM13] = &pwm13_clk.common.hw, -+ [CLK_PWM14] = &pwm14_clk.common.hw, -+ [CLK_PWM15] = &pwm15_clk.common.hw, -+ [CLK_PWM16] = &pwm16_clk.common.hw, -+ [CLK_PWM17] = &pwm17_clk.common.hw, -+ [CLK_PWM18] = &pwm18_clk.common.hw, -+ [CLK_PWM19] = &pwm19_clk.common.hw, -+ [CLK_SSP3] = &ssp3_clk.common.hw, -+ [CLK_RTC] = &rtc_clk.common.hw, -+ [CLK_TWSI0] = &twsi0_clk.common.hw, -+ [CLK_TWSI1] = &twsi1_clk.common.hw, -+ [CLK_TWSI2] = &twsi2_clk.common.hw, -+ [CLK_TWSI4] = &twsi4_clk.common.hw, -+ [CLK_TWSI5] = &twsi5_clk.common.hw, -+ [CLK_TWSI6] = &twsi6_clk.common.hw, -+ [CLK_TWSI7] = &twsi7_clk.common.hw, -+ [CLK_TWSI8] = &twsi8_clk.common.hw, -+ [CLK_TIMERS1] = &timers1_clk.common.hw, -+ [CLK_TIMERS2] = &timers2_clk.common.hw, -+ [CLK_AIB] = &aib_clk.common.hw, -+ [CLK_ONEWIRE] = &onewire_clk.common.hw, -+ [CLK_SSPA0] = &sspa0_clk.common.hw, -+ [CLK_SSPA1] = &sspa1_clk.common.hw, -+ [CLK_DRO] = &dro_clk.common.hw, -+ [CLK_IR] = &ir_clk.common.hw, -+ [CLK_TSEN] = &tsen_clk.common.hw, -+ [CLK_IPC_AP2AUD] = &ipc_ap2aud_clk.common.hw, -+ [CLK_CAN0] = &can0_clk.common.hw, -+ [CLK_CAN0_BUS] = &can0_bus_clk.common.hw, -+ [CLK_WDT] = &wdt_clk.common.hw, -+ [CLK_RIPC] = &ripc_clk.common.hw, -+ [CLK_JPG] = &jpg_clk.common.hw, -+ [CLK_JPF_4KAFBC] = &jpg_4kafbc_clk.common.hw, -+ [CLK_JPF_2KAFBC] = &jpg_2kafbc_clk.common.hw, -+ [CLK_CCIC2PHY] = &ccic2phy_clk.common.hw, -+ [CLK_CCIC3PHY] = &ccic3phy_clk.common.hw, -+ [CLK_CSI] = &csi_clk.common.hw, -+ [CLK_CAMM0] = &camm0_clk.common.hw, -+ [CLK_CAMM1] = &camm1_clk.common.hw, -+ [CLK_CAMM2] = &camm2_clk.common.hw, -+ [CLK_ISP_CPP] = &isp_cpp_clk.common.hw, -+ [CLK_ISP_BUS] = &isp_bus_clk.common.hw, -+ [CLK_ISP] = &isp_clk.common.hw, -+ [CLK_DPU_MCLK] = &dpu_mclk.common.hw, -+ [CLK_DPU_ESC] = &dpu_esc_clk.common.hw, -+ [CLK_DPU_BIT] = &dpu_bit_clk.common.hw, -+ [CLK_DPU_PXCLK] = &dpu_pxclk.common.hw, -+ [CLK_DPU_HCLK] = &dpu_hclk.common.hw, -+ [CLK_DPU_SPI] = &dpu_spi_clk.common.hw, -+ [CLK_DPU_SPI_HBUS] = &dpu_spi_hbus_clk.common.hw, -+ [CLK_DPU_SPIBUS] = &dpu_spi_bus_clk.common.hw, -+ [CLK_SPU_SPI_ACLK] = &dpu_spi_aclk.common.hw, -+ [CLK_V2D] = &v2d_clk.common.hw, -+ [CLK_CCIC_4X] = &ccic_4x_clk.common.hw, -+ [CLK_CCIC1PHY] = &ccic1phy_clk.common.hw, -+ [CLK_SDH_AXI] = &sdh_axi_aclk.common.hw, -+ [CLK_SDH0] = &sdh0_clk.common.hw, -+ [CLK_SDH1] = &sdh1_clk.common.hw, -+ [CLK_SDH2] = &sdh2_clk.common.hw, -+ [CLK_USB_P1] = &usb_p1_aclk.common.hw, -+ [CLK_USB_AXI] = &usb_axi_clk.common.hw, -+ [CLK_USB30] = &usb30_clk.common.hw, -+ [CLK_QSPI] = &qspi_clk.common.hw, -+ [CLK_QSPI_BUS] = &qspi_bus_clk.common.hw, -+ [CLK_DMA] = &dma_clk.common.hw, -+ [CLK_AES] = &aes_clk.common.hw, -+ [CLK_VPU] = &vpu_clk.common.hw, -+ [CLK_GPU] = &gpu_clk.common.hw, -+ [CLK_EMMC] = &emmc_clk.common.hw, -+ [CLK_EMMC_X] = &emmc_x_clk.common.hw, -+ [CLK_AUDIO] = &audio_clk.common.hw, -+ [CLK_HDMI] = &hdmi_mclk.common.hw, -+ [CLK_CCI550] = &cci550_clk.common.hw, -+ [CLK_PMUA_ACLK] = &pmua_aclk.common.hw, -+ [CLK_CPU_C0_HI] = &cpu_c0_hi_clk.common.hw, -+ [CLK_CPU_C0_CORE] = &cpu_c0_core_clk.common.hw, -+ [CLK_CPU_C0_ACE] = &cpu_c0_ace_clk.common.hw, -+ [CLK_CPU_C0_TCM] = &cpu_c0_tcm_clk.common.hw, -+ [CLK_CPU_C1_HI] = &cpu_c1_hi_clk.common.hw, -+ [CLK_CPU_C1_CORE] = &cpu_c1_pclk.common.hw, -+ [CLK_CPU_C1_ACE] = &cpu_c1_ace_clk.common.hw, -+ [CLK_PCIE0] = &pcie0_clk.common.hw, -+ [CLK_PCIE1] = &pcie1_clk.common.hw, -+ [CLK_PCIE2] = &pcie2_clk.common.hw, -+ [CLK_EMAC0_BUS] = &emac0_bus_clk.common.hw, -+ [CLK_EMAC0_PTP] = &emac0_ptp_clk.common.hw, -+ [CLK_EMAC1_BUS] = &emac1_bus_clk.common.hw, -+ [CLK_EMAC1_PTP] = &emac1_ptp_clk.common.hw, -+ [CLK_SEC_UART1] = &uart1_sec_clk.common.hw, -+ [CLK_SEC_SSP2] = &ssp2_sec_clk.common.hw, -+ [CLK_SEC_TWSI3] = &twsi3_sec_clk.common.hw, -+ [CLK_SEC_RTC] = &rtc_sec_clk.common.hw, -+ [CLK_SEC_TIMERS0] = &timers0_sec_clk.common.hw, -+ [CLK_SEC_KPC] = &kpc_sec_clk.common.hw, -+ [CLK_SEC_GPIO] = &gpio_sec_clk.common.hw, -+ [CLK_APB] = &apb_clk.common.hw, -+ [CLK_SLOW_UART] = &slow_uart.common.hw, -+ [CLK_I2S_SYSCLK] = &i2s_sysclk.common.hw, -+ [CLK_I2S_BCLK] = &i2s_bclk.common.hw, -+ [CLK_RCPU_HDMIAUDIO] = &rhdmi_audio_clk.common.hw, -+ [CLK_RCPU_CAN] = &rcan_clk.common.hw, -+ [CLK_RCPU_CAN_BUS] = &rcan_bus_clk.common.hw, -+ [CLK_RCPU_I2C0] = &ri2c0_clk.common.hw, -+ [CLK_RCPU_SSP0] = &rssp0_clk.common.hw, -+ [CLK_RCPU_IR] = &rir_clk.common.hw, -+ [CLK_RCPU_UART0] = &ruart0_clk.common.hw, -+ [CLK_RCPU_UART1] = &ruart1_clk.common.hw, -+ [CLK_DPLL1] = &dpll1.common.hw, -+ [CLK_DPLL2] = &dpll2.common.hw, -+ [CLK_DFC_LVL0] = &dfc_lvl0.common.hw, -+ [CLK_DFC_LVL1] = &dfc_lvl1.common.hw, -+ [CLK_DFC_LVL2] = &dfc_lvl2.common.hw, -+ [CLK_DFC_LVL3] = &dfc_lvl3.common.hw, -+ [CLK_DFC_LVL4] = &dfc_lvl4.common.hw, -+ [CLK_DFC_LVL5] = &dfc_lvl5.common.hw, -+ [CLK_DFC_LVL6] = &dfc_lvl6.common.hw, -+ [CLK_DFC_LVL7] = &dfc_lvl7.common.hw, -+ [CLK_DDR] = &ddr.common.hw, -+ [CLK_RCPU2_PWM0] = &rpwm0_clk.common.hw, -+ [CLK_RCPU2_PWM1] = &rpwm1_clk.common.hw, -+ [CLK_RCPU2_PWM2] = &rpwm2_clk.common.hw, -+ [CLK_RCPU2_PWM3] = &rpwm3_clk.common.hw, -+ [CLK_RCPU2_PWM4] = &rpwm4_clk.common.hw, -+ [CLK_RCPU2_PWM5] = &rpwm5_clk.common.hw, -+ [CLK_RCPU2_PWM6] = &rpwm6_clk.common.hw, -+ [CLK_RCPU2_PWM7] = &rpwm7_clk.common.hw, -+ [CLK_RCPU2_PWM8] = &rpwm8_clk.common.hw, -+ [CLK_RCPU2_PWM9] = &rpwm9_clk.common.hw, -+ }, -+ .num = CLK_MAX_NO, -+}; -+ -+static struct clk_hw_table bootup_enable_clk_table[] = { -+ {"pll1_d8_307p2", CLK_PLL1_307P2}, -+ {"pll1_d6_409p6", CLK_PLL1_409P6}, -+ {"pll1_d5_491p52", CLK_PLL1_491}, -+ {"pll1_d4_614p4", CLK_PLL1_614}, -+ {"pll1_d3_819p2", CLK_PLL1_819}, -+ {"pll1_d2_1228p8", CLK_PLL1_1228}, -+ {"pll1_d10_245p76", CLK_PLL1_245P76}, -+ {"pll1_d48_51p2", CLK_PLL1_51P2}, -+ {"pll1_d48_51p2_ap", CLK_PLL1_51P2_AP}, -+ {"pll1_d96_25p6", CLK_PLL1_25P6}, -+ {"pll3_d1", CLK_PLL3_D1}, -+ {"pll3_d2", CLK_PLL3_D2}, -+ {"pll3_d3", CLK_PLL3_D3}, -+ {"pll2_d3", CLK_PLL2_D3}, -+ {"apb_clk", CLK_APB}, -+ {"pmua_aclk", CLK_PMUA_ACLK}, -+ {"dma_clk", CLK_DMA}, -+}; -+ -+void spacemit_clocks_enable(struct clk_hw_table *tbl, int tbl_size) -+{ -+ int i; -+ struct clk *clk; -+ struct clk_hw *hw_clk; ++ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); ++ if (ret) ++ dev_err(dev, "failed to add clock hardware provider (%d)\n", ret); + -+ for (i = 0; i < tbl_size; i++) { -+ hw_clk = spacemit_k1_hw_clks.hws[tbl[i].clk_hw_id]; -+ clk = clk_hw_get_clk(hw_clk, tbl[i].name); -+ if (!IS_ERR_OR_NULL(clk)) -+ clk_prepare_enable(clk); -+ else -+ pr_err("%s : can't find clk %s\n", -+ __func__, tbl[i].name); -+ } ++ return ret; +} + -+unsigned long spacemit_k1_ddr_freq_tbl[MAX_FREQ_LV + 1] = {0}; -+ -+void spacemit_fill_ddr_freq_tbl(void) ++static void spacemit_cadev_release(struct device *dev) +{ -+ int i; -+ struct clk *clk; -+ struct clk_hw *hw_clk; -+ -+ for (i = 0; i < ARRAY_SIZE(spacemit_k1_ddr_freq_tbl); i++) { -+ hw_clk = spacemit_k1_hw_clks.hws[CLK_DFC_LVL0 + i]; -+ clk = clk_hw_get_clk(hw_clk, ddr_clk_parents[i]); ++ struct auxiliary_device *adev = to_auxiliary_dev(dev); + -+ if (!IS_ERR_OR_NULL(clk)) -+ spacemit_k1_ddr_freq_tbl[i] = clk_get_rate(clk); -+ else -+ pr_err("%s : can't find clk %s\n", -+ __func__, ddr_clk_parents[i]); -+ } ++ kfree(to_spacemit_ccu_adev(adev)); +} + -+int ccu_common_init(struct clk_hw *hw, struct spacemit_k1_clk *clk_info) ++static void spacemit_adev_unregister(void *data) +{ -+ struct ccu_common *common = hw_to_ccu_common(hw); -+ struct ccu_pll *pll = hw_to_ccu_pll(hw); -+ -+ if (!common) -+ return -1; -+ -+ common->lock = &g_cru_lock; -+ -+ switch (common->base_type) { -+ case BASE_TYPE_MPMU: -+ common->base = clk_info->mpmu_base; -+ break; -+ case BASE_TYPE_APMU: -+ common->base = clk_info->apmu_base; -+ break; -+ case BASE_TYPE_APBC: -+ common->base = clk_info->apbc_base; -+ break; -+ case BASE_TYPE_APBS: -+ common->base = clk_info->apbs_base; -+ break; -+ case BASE_TYPE_CIU: -+ common->base = clk_info->ciu_base; -+ break; -+ case BASE_TYPE_DCIU: -+ common->base = clk_info->dciu_base; -+ break; -+ case BASE_TYPE_DDRC: -+ common->base = clk_info->ddrc_base; -+ break; -+ case BASE_TYPE_AUDC: -+ common->base = clk_info->audio_ctrl_base; -+ break; -+ case BASE_TYPE_APBC2: -+ common->base = clk_info->apbc2_base; -+ break; -+ case BASE_TYPE_RCPU: -+ common->base = clk_info->rcpu_base; -+ break; -+ case BASE_TYPE_RCPU2: -+ common->base = clk_info->rcpu2_base; -+ break; -+ default: -+ common->base = clk_info->apbc_base; -+ break; -+ } -+ -+ if (common->is_pll) -+ pll->pll.lock_base = clk_info->mpmu_base; ++ struct auxiliary_device *adev = data; + -+ return 0; ++ auxiliary_device_delete(adev); ++ auxiliary_device_uninit(adev); +} + -+int spacemit_ccu_probe(struct device_node *node, -+ struct spacemit_k1_clk *clk_info, -+ struct clk_hw_onecell_data *hw_clks) ++static int spacemit_ccu_reset_register(struct device *dev, ++ struct regmap *regmap, ++ const char *reset_name) +{ -+ int i, ret; ++ struct spacemit_ccu_adev *cadev; ++ struct auxiliary_device *adev; ++ static u32 next_id; ++ int ret; + -+ for (i = 0; i < hw_clks->num; i++) { -+ struct clk_hw *hw = hw_clks->hws[i]; -+ const char *name; ++ /* Nothing to do if the CCU does not implement a reset controller */ ++ if (!reset_name) ++ return 0; + -+ if (!hw) -+ continue; -+ if (!hw->init) -+ continue; ++ cadev = devm_kzalloc(dev, sizeof(*cadev), GFP_KERNEL); ++ if (!cadev) ++ return -ENOMEM; ++ cadev->regmap = regmap; + -+ ccu_common_init(hw, clk_info); -+ name = hw->init->name; ++ adev = &cadev->adev; ++ adev->name = reset_name; ++ adev->dev.parent = dev; ++ adev->dev.release = spacemit_cadev_release; ++ adev->dev.of_node = dev->of_node; ++ adev->id = next_id++; + -+ ret = of_clk_hw_register(node, hw); -+ if (ret) { -+ pr_err("Couldn't register clock %d - %s\n", i, name); -+ goto err_clk_unreg; -+ } -+ } -+ ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, hw_clks); ++ ret = auxiliary_device_init(adev); + if (ret) -+ goto err_clk_unreg; -+ -+ spacemit_clocks_enable(bootup_enable_clk_table, -+ ARRAY_SIZE(bootup_enable_clk_table)); -+ spacemit_fill_ddr_freq_tbl(); -+ -+ return 0; -+ -+err_clk_unreg: -+ while (--i >= 0) { -+ struct clk_hw *hw = hw_clks->hws[i]; ++ return ret; + -+ if (!hw) -+ continue; -+ clk_hw_unregister(hw); ++ ret = auxiliary_device_add(adev); ++ if (ret) { ++ auxiliary_device_uninit(adev); ++ return ret; + } + -+ return ret; ++ return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev); +} + -+static void spacemit_k1_ccu_probe(struct device_node *np) ++static int k3_ccu_probe(struct platform_device *pdev) +{ ++ struct regmap *base_regmap, *lock_regmap = NULL; ++ const struct spacemit_ccu_data *data; ++ struct device *dev = &pdev->dev; + int ret; -+ struct spacemit_k1_clk *clk_info; -+ struct clk_hw_onecell_data *hw_clks = &spacemit_k1_hw_clks; -+ -+ if (of_device_is_compatible(np, "spacemit,k1-clock")) { -+ clk_info = &k1_clock_controller; -+ -+ clk_info->mpmu_base = of_iomap(np, 0); -+ if (!clk_info->mpmu_base) { -+ pr_err("failed to map mpmu registers\n"); -+ goto out; -+ } -+ -+ clk_info->apmu_base = of_iomap(np, 1); -+ if (!clk_info->apmu_base) { -+ pr_err("failed to map apmu registers\n"); -+ goto out; -+ } -+ -+ clk_info->apbc_base = of_iomap(np, 2); -+ if (!clk_info->apbc_base) { -+ pr_err("failed to map apbc registers\n"); -+ goto out; -+ } -+ -+ clk_info->apbs_base = of_iomap(np, 3); -+ if (!clk_info->apbs_base) { -+ pr_err("failed to map apbs registers\n"); -+ goto out; -+ } + -+ clk_info->ciu_base = of_iomap(np, 4); -+ if (!clk_info->ciu_base) { -+ pr_err("failed to map ciu registers\n"); -+ goto out; -+ } -+ -+ clk_info->dciu_base = of_iomap(np, 5); -+ if (!clk_info->dciu_base) { -+ pr_err("failed to map dragon ciu registers\n"); -+ goto out; -+ } -+ -+ clk_info->ddrc_base = of_iomap(np, 6); -+ if (!clk_info->ddrc_base) { -+ pr_err("failed to map ddrc registers\n"); -+ goto out; -+ } ++ base_regmap = device_node_to_regmap(dev->of_node); ++ if (IS_ERR(base_regmap)) ++ return dev_err_probe(dev, PTR_ERR(base_regmap), ++ "failed to get regmap\n"); ++ /* ++ * The lock status of PLLs locate in MPMU region, while PLLs themselves ++ * are in APBS region. Reference to MPMU syscon is required to check PLL ++ * status. ++ */ ++ if (of_device_is_compatible(dev->of_node, "spacemit,k3-pll")) { ++ struct device_node *mpmu = of_parse_phandle(dev->of_node, ++ "spacemit,mpmu", 0); + -+ clk_info->apbc2_base = of_iomap(np, 7); -+ if (!clk_info->apbc2_base) { -+ pr_err("failed to map apbc2 registers\n"); -+ goto out; -+ } ++ if (!mpmu) ++ return dev_err_probe(dev, -ENODEV, ++ "Cannot parse MPMU region\n"); + -+ clk_info->rcpu_base = of_iomap(np, 8); -+ if (!clk_info->rcpu_base) { -+ pr_err("failed to map rcpu registers\n"); -+ goto out; -+ } ++ lock_regmap = device_node_to_regmap(mpmu); ++ of_node_put(mpmu); + -+ clk_info->rcpu2_base = of_iomap(np, 9); -+ if (!clk_info->rcpu2_base) { -+ pr_err("failed to map rcpu2 registers\n"); -+ goto out; -+ } -+ } else { -+ pr_err("not spacemit,k1-clock\n"); -+ goto out; ++ if (IS_ERR(lock_regmap)) ++ return dev_err_probe(dev, PTR_ERR(lock_regmap), ++ "failed to get lock regmap\n"); + } -+ ret = spacemit_ccu_probe(np, clk_info, hw_clks); -+ if (ret) -+ return; -+out: -+ return; -+} -+ -+void *spacemit_get_ddr_freq_tbl(void) -+{ -+ return spacemit_k1_ddr_freq_tbl; -+} -+EXPORT_SYMBOL_GPL(spacemit_get_ddr_freq_tbl); -+ -+u32 spacemit_get_ddr_freq_level(void) -+{ -+ u32 ddr_freq_lvl = 0; -+ struct clk_hw *hw = spacemit_k1_hw_clks.hws[CLK_DDR]; -+ -+ ddr_freq_lvl = clk_hw_get_parent_index(hw); -+ -+ return ddr_freq_lvl; -+} -+EXPORT_SYMBOL_GPL(spacemit_get_ddr_freq_level); + -+int spacemit_set_ddr_freq_level(u32 level) -+{ -+ int ret = 0; -+ struct clk_hw *hw = spacemit_k1_hw_clks.hws[CLK_DDR]; ++ data = of_device_get_match_data(dev); + -+ if (level < 0 || level > MAX_FREQ_LV) -+ return -EINVAL; ++ ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, data); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to register clocks\n"); + -+ ret = clk_hw_set_parent(hw, clk_hw_get_parent_by_index(hw, level)); ++ ret = spacemit_ccu_reset_register(dev, base_regmap, data->reset_name); + if (ret) -+ pr_err("%s : set ddr freq fail\n", __func__); ++ return dev_err_probe(dev, ret, "failed to register resets\n"); + + return 0; +} -+EXPORT_SYMBOL_GPL(spacemit_set_ddr_freq_level); + -+CLK_OF_DECLARE(k1_clock, "spacemit,k1-clock", spacemit_k1_ccu_probe); ++static const struct of_device_id of_k3_ccu_match[] = { ++ { ++ .compatible = "spacemit,k3-pll", ++ .data = &k3_ccu_pll_data, ++ }, ++ { ++ .compatible = "spacemit,k3-syscon-mpmu", ++ .data = &k3_ccu_mpmu_data, ++ }, ++ { ++ .compatible = "spacemit,k3-syscon-apbc", ++ .data = &k3_ccu_apbc_data, ++ }, ++ { ++ .compatible = "spacemit,k3-syscon-apmu", ++ .data = &k3_ccu_apmu_data, ++ }, ++ { ++ .compatible = "spacemit,k3-syscon-dciu", ++ .data = &k3_ccu_dciu_data, ++ }, ++ { ++ .compatible = "spacemit,k3-syscon-rcpu-sysctrl", ++ .data = &k3_ccu_rcpu_sysctrl_data, ++ }, ++ { ++ .compatible = "spacemit,k3-syscon-rcpu-uartctrl", ++ .data = &k3_ccu_rcpu_uartctrl_data, ++ }, ++ { ++ .compatible = "spacemit,k3-syscon-rcpu-i2sctrl", ++ .data = &k3_ccu_rcpu_i2sctrl_data, ++ }, ++ { ++ .compatible = "spacemit,k3-syscon-rcpu-spictrl", ++ .data = &k3_ccu_rcpu_spictrl_data, ++ }, ++ { ++ .compatible = "spacemit,k3-syscon-rcpu-i2cctrl", ++ .data = &k3_ccu_rcpu_i2cctrl_data, ++ }, ++ { ++ .compatible = "spacemit,k3-syscon-rpmu", ++ .data = &k3_ccu_rpmu_data, ++ }, ++ { ++ .compatible = "spacemit,k3-syscon-rcpu-pwmctrl", ++ .data = &k3_ccu_rcpu_pwmctrl_data, ++ }, ++ { ++ .compatible = "spacemit,k3-syscon-apbc2", ++ .data = &k3_ccu_apbc2_data, ++ }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, of_k3_ccu_match); + -diff --git a/drivers/clk/spacemit/ccu-spacemit-k1.h b/drivers/clk/spacemit/ccu-spacemit-k1.h ++static struct platform_driver k3_ccu_driver = { ++ .driver = { ++ .name = "spacemit,k3-ccu", ++ .of_match_table = of_k3_ccu_match, ++ }, ++ .probe = k3_ccu_probe, ++}; ++module_platform_driver(k3_ccu_driver); ++ ++MODULE_DESCRIPTION("SpacemiT K3 CCU driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/clk/spacemit/ccu_common.h b/drivers/clk/spacemit/ccu_common.h new file mode 100644 -index 000000000000..f7da85ea3c31 +index 000000000000..db8d43286ee7 --- /dev/null -+++ b/drivers/clk/spacemit/ccu-spacemit-k1.h -@@ -0,0 +1,81 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* Copyright (c) 2023, spacemit Corporation. */ -+ -+#ifndef _CCU_SPACEMIT_K1_H_ -+#define _CCU_SPACEMIT_K1_H_ ++++ b/drivers/clk/spacemit/ccu_common.h +@@ -0,0 +1,52 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (c) 2024 SpacemiT Technology Co. Ltd ++ * Copyright (c) 2024-2025 Haylen Chu ++ */ + -+#include -+#include ++#ifndef _CCU_COMMON_H_ ++#define _CCU_COMMON_H_ + -+enum ccu_base_type { -+ BASE_TYPE_MPMU = 0, -+ BASE_TYPE_APMU = 1, -+ BASE_TYPE_APBC = 2, -+ BASE_TYPE_APBS = 3, -+ BASE_TYPE_CIU = 4, -+ BASE_TYPE_DCIU = 5, -+ BASE_TYPE_DDRC = 6, -+ BASE_TYPE_AUDC = 7, -+ BASE_TYPE_APBC2 = 8, -+ BASE_TYPE_RCPU = 9, -+ BASE_TYPE_RCPU2 = 10, -+}; ++#include + -+enum { -+ CLK_DIV_TYPE_1REG_NOFC_V1 = 0, -+ CLK_DIV_TYPE_1REG_FC_V2, -+ CLK_DIV_TYPE_2REG_NOFC_V3, -+ CLK_DIV_TYPE_2REG_FC_V4, -+ CLK_DIV_TYPE_1REG_FC_DIV_V5, -+ CLK_DIV_TYPE_1REG_FC_MUX_V6, -+}; ++/* invert en-bit value of gate clock, 1: disable, 0: enable */ ++#define CCU_GATE_INVERT_FLAG BIT(31) + +struct ccu_common { -+ void __iomem *base; -+ enum ccu_base_type base_type; -+ u32 reg_type; -+ u32 reg_ctrl; -+ u32 reg_sel; -+ u32 reg_xtc; -+ u32 fc; -+ bool is_pll; -+ const char *name; -+ const struct clk_ops *ops; -+ const char * const *parent_names; -+ u8 num_parents; -+ unsigned long flags; -+ spinlock_t *lock; -+ struct clk_hw hw; -+}; -+ -+struct spacemit_k1_clk { -+ void __iomem *mpmu_base; -+ void __iomem *apmu_base; -+ void __iomem *apbc_base; -+ void __iomem *apbs_base; -+ void __iomem *ciu_base; -+ void __iomem *dciu_base; -+ void __iomem *ddrc_base; -+ void __iomem *audio_ctrl_base; -+ void __iomem *apbc2_base; -+ void __iomem *rcpu_base; -+ void __iomem *rcpu2_base; -+}; -+ -+struct clk_hw_table { -+ char *name; -+ u32 clk_hw_id; -+}; -+ -+extern spinlock_t g_cru_lock; ++ struct regmap *regmap; ++ struct regmap *lock_regmap; ++ ++ union { ++ /* For DDN and MIX */ ++ struct { ++ u32 reg_ctrl; ++ u32 reg_fc; ++ u32 mask_fc; ++ }; ++ ++ /* For PLL */ ++ struct { ++ u32 reg_swcr1; ++ u32 reg_swcr2; ++ u32 reg_swcr3; ++ }; ++ }; ++ ++ struct clk_hw hw; ++}; + +static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw) +{ + return container_of(hw, struct ccu_common, hw); +} + -+int spacemit_ccu_probe(struct device_node *node, -+ struct spacemit_k1_clk *clk_info, -+ struct clk_hw_onecell_data *desc); -+ -+#endif /* _CCU_SPACEMIT_K1_H_ */ ++#define ccu_read(c, reg) \ ++ ({ \ ++ u32 tmp; \ ++ regmap_read((c)->regmap, (c)->reg_##reg, &tmp); \ ++ tmp; \ ++ }) ++#define ccu_update(c, reg, mask, val) \ ++ regmap_update_bits((c)->regmap, (c)->reg_##reg, mask, val) ++ ++#endif /* _CCU_COMMON_H_ */ diff --git a/drivers/clk/spacemit/ccu_ddn.c b/drivers/clk/spacemit/ccu_ddn.c new file mode 100644 -index 000000000000..a23d9dad8e32 +index 000000000000..06d86748182b --- /dev/null +++ b/drivers/clk/spacemit/ccu_ddn.c -@@ -0,0 +1,161 @@ +@@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* -+ * Spacemit clock type ddn ++ * Copyright (c) 2024 SpacemiT Technology Co. Ltd ++ * Copyright (c) 2024-2025 Haylen Chu + * -+ * Copyright (c) 2023, spacemit Corporation. ++ * DDN stands for "Divider Denominator Numerator", it's M/N clock with a ++ * constant x2 factor. This clock hardware follows the equation below, + * -+ */ -+ -+#include -+#include -+#include "ccu_ddn.h" -+ -+/* -+ * It is M/N clock ++ * numerator Fin ++ * 2 * ------------- = ------- ++ * denominator Fout ++ * ++ * Thus, Fout could be calculated with, + * -+ * Fout from synthesizer can be given from two equations: -+ * numerator/denominator = Fin / (Fout * factor) ++ * Fin denominator ++ * Fout = ----- * ------------- ++ * 2 numerator + */ + -+static void ccu_ddn_disable(struct clk_hw *hw) -+{ -+ struct ccu_ddn *ddn = hw_to_ccu_ddn(hw); -+ struct ccu_common *common = &ddn->common; -+ unsigned long flags; -+ u32 reg; -+ -+ if (!ddn->gate) -+ return; ++#include ++#include + -+ spin_lock_irqsave(common->lock, flags); -+ reg = readl(common->base + common->reg_sel); -+ writel(reg & ~ddn->gate, common->base + common->reg_sel); -+ spin_unlock_irqrestore(common->lock, flags); -+} ++#include "ccu_ddn.h" + -+static int ccu_ddn_enable(struct clk_hw *hw) ++static unsigned long ccu_ddn_calc_rate(unsigned long prate, unsigned long num, ++ unsigned long den, unsigned int pre_div) +{ -+ struct ccu_ddn *ddn = hw_to_ccu_ddn(hw); -+ struct ccu_common *common = &ddn->common; -+ unsigned long flags; -+ u32 reg; -+ -+ if (!ddn->gate) -+ return 0; -+ -+ spin_lock_irqsave(common->lock, flags); -+ reg = readl(common->base + common->reg_sel); -+ writel(reg | ddn->gate, common->base + common->reg_sel); -+ spin_unlock_irqrestore(common->lock, flags); -+ -+ return 0; ++ return prate * den / pre_div / num; +} + -+static int ccu_ddn_is_enabled(struct clk_hw *hw) ++static unsigned long ccu_ddn_calc_best_rate(struct ccu_ddn *ddn, ++ unsigned long rate, unsigned long prate, ++ unsigned long *num, unsigned long *den) +{ -+ struct ccu_ddn *ddn = hw_to_ccu_ddn(hw); -+ struct ccu_common *common = &ddn->common; -+ -+ if (!ddn->gate) -+ return 1; -+ -+ return readl(common->base + common->reg_sel) & ddn->gate; ++ rational_best_approximation(rate, prate / ddn->pre_div, ++ ddn->den_mask >> ddn->den_shift, ++ ddn->num_mask >> ddn->num_shift, ++ den, num); ++ return ccu_ddn_calc_rate(prate, *num, *den, ddn->pre_div); +} + -+static long clk_ddn_round_rate(struct clk_hw *hw, unsigned long drate, ++static long ccu_ddn_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct ccu_ddn *ddn = hw_to_ccu_ddn(hw); -+ struct ccu_ddn_config *params = &ddn->ddn; -+ unsigned long rate = 0, prev_rate; -+ unsigned long result; -+ int i; -+ -+ for (i = 0; i < params->tbl_size; i++) { -+ prev_rate = rate; -+ rate = (((*prate / 10000) * params->tbl[i].den) / -+ (params->tbl[i].num * params->info->factor)) * 10000; -+ if (rate > drate) -+ break; -+ } ++ unsigned long num, den; + -+ if (i == 0 || i == params->tbl_size) { -+ result = rate; -+ } else { -+ if ((drate - prev_rate) > (rate - drate)) -+ result = rate; -+ else -+ result = prev_rate; -+ } -+ return result; ++ return ccu_ddn_calc_best_rate(ddn, rate, *prate, &num, &den); +} + -+static unsigned long clk_ddn_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) ++static unsigned long ccu_ddn_recalc_rate(struct clk_hw *hw, unsigned long prate) +{ + struct ccu_ddn *ddn = hw_to_ccu_ddn(hw); -+ struct ccu_ddn_config *params = &ddn->ddn; + unsigned int val, num, den; -+ unsigned long rate; + -+ val = readl(ddn->common.base + ddn->common.reg_ctrl); -+ num = (val >> params->info->num_shift) & params->info->num_mask; -+ den = (val >> params->info->den_shift) & params->info->den_mask; -+ if (!den) -+ return 0; ++ val = ccu_read(&ddn->common, ctrl); + -+ rate = (((parent_rate / 10000) * den) / -+ (num * params->info->factor)) * 10000; ++ num = (val & ddn->num_mask) >> ddn->num_shift; ++ den = (val & ddn->den_mask) >> ddn->den_shift; + -+ return rate; ++ return ccu_ddn_calc_rate(prate, num, den, ddn->pre_div); +} + -+/* Configures new clock rate*/ -+static int clk_ddn_set_rate(struct clk_hw *hw, unsigned long drate, ++static int ccu_ddn_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + struct ccu_ddn *ddn = hw_to_ccu_ddn(hw); -+ struct ccu_ddn_config *params = &ddn->ddn; -+ int i; -+ unsigned long val; -+ unsigned long prev_rate, rate = 0; -+ unsigned long flags = 0; -+ -+ for (i = 0; i < params->tbl_size; i++) { -+ prev_rate = rate; -+ rate = (((prate / 10000) * params->tbl[i].den) / -+ (params->tbl[i].num * params->info->factor)) * 10000; -+ if (rate > drate) -+ break; -+ } -+ -+ if (i > 0) -+ i--; ++ unsigned long num, den; + -+ if (ddn->common.lock) -+ spin_lock_irqsave(ddn->common.lock, flags); ++ ccu_ddn_calc_best_rate(ddn, rate, prate, &num, &den); + -+ val = readl(ddn->common.base + ddn->common.reg_ctrl); -+ val &= ~(params->info->num_mask << params->info->num_shift); -+ val |= (params->tbl[i].num & params->info->num_mask) -+ << params->info->num_shift; -+ val &= ~(params->info->den_mask << params->info->den_shift); -+ val |= (params->tbl[i].den & params->info->den_mask) -+ << params->info->den_shift; -+ writel(val, ddn->common.base + ddn->common.reg_ctrl); -+ -+ if (ddn->common.lock) -+ spin_unlock_irqrestore(ddn->common.lock, flags); ++ ccu_update(&ddn->common, ctrl, ++ ddn->num_mask | ddn->den_mask, ++ (num << ddn->num_shift) | (den << ddn->den_shift)); + + return 0; +} + -+const struct clk_ops ccu_ddn_ops = { -+ .disable = ccu_ddn_disable, -+ .enable = ccu_ddn_enable, -+ .is_enabled = ccu_ddn_is_enabled, -+ .recalc_rate = clk_ddn_recalc_rate, -+ .round_rate = clk_ddn_round_rate, -+ .set_rate = clk_ddn_set_rate, ++const struct clk_ops spacemit_ccu_ddn_ops = { ++ .recalc_rate = ccu_ddn_recalc_rate, ++ .round_rate = ccu_ddn_round_rate, ++ .set_rate = ccu_ddn_set_rate, +}; -+ diff --git a/drivers/clk/spacemit/ccu_ddn.h b/drivers/clk/spacemit/ccu_ddn.h new file mode 100644 -index 000000000000..92a4e3e46262 +index 000000000000..4838414a8e8d --- /dev/null +++ b/drivers/clk/spacemit/ccu_ddn.h -@@ -0,0 +1,86 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* Copyright (c) 2023, spacemit Corporation. */ +@@ -0,0 +1,50 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (c) 2024 SpacemiT Technology Co. Ltd ++ * Copyright (c) 2024-2025 Haylen Chu ++ */ + +#ifndef _CCU_DDN_H_ +#define _CCU_DDN_H_ + -+#include ++#include +#include + -+#include "ccu-spacemit-k1.h" ++#include "ccu_common.h" + -+struct ccu_ddn_tbl { -+ unsigned int num; -+ unsigned int den; -+}; -+ -+struct ccu_ddn_info { -+ unsigned int factor; ++struct ccu_ddn { ++ struct ccu_common common; + unsigned int num_mask; -+ unsigned int den_mask; + unsigned int num_shift; ++ unsigned int den_mask; + unsigned int den_shift; ++ unsigned int pre_div; +}; + -+struct ccu_ddn_config { -+ struct ccu_ddn_info *info; -+ struct ccu_ddn_tbl *tbl; -+ u32 tbl_size; -+}; -+ -+#define PLL_DDN_TBL(_num, _den) \ -+ { \ -+ .num = (_num), \ -+ .den = (_den), \ -+ } ++#define CCU_DDN_INIT(_name, _parent, _flags) \ ++ CLK_HW_INIT_HW(#_name, &_parent.common.hw, &spacemit_ccu_ddn_ops, _flags) + -+struct ccu_ddn { -+ u32 gate; -+ struct ccu_ddn_config ddn; -+ struct ccu_common common; -+}; -+ -+#define _SPACEMIT_CCU_DDN_CONFIG(_info, _table, _size) \ -+ { \ -+ .info = (struct ccu_ddn_info *)_info, \ -+ .tbl = (struct ccu_ddn_tbl *)_table, \ -+ .tbl_size = _size, \ -+ } -+ -+#define SPACEMIT_CCU_DDN(_struct, _name, _parent, _info, _table, \ -+ _size, _base_type, _reg_ctrl, _flags) \ -+ struct ccu_ddn _struct = { \ -+ .ddn = _SPACEMIT_CCU_DDN_CONFIG(_info, _table, _size), \ -+ .common = { \ -+ .reg_ctrl = _reg_ctrl, \ -+ .base_type = _base_type, \ -+ .hw.init = CLK_HW_INIT(_name, \ -+ _parent, &ccu_ddn_ops, _flags), \ -+ } \ -+ } -+ -+#define SPACEMIT_CCU_DDN_GATE(_struct, _name, _parent, _info, \ -+ _table, _size, _base_type, _reg_ddn, \ -+ __reg_gate, _gate_mask, _flags) \ -+ struct ccu_ddn _struct = { \ -+ .gate = _gate_mask, \ -+ .ddn = _SPACEMIT_CCU_DDN_CONFIG(_info, _table, _size), \ -+ .common = { \ -+ .reg_ctrl = _reg_ddn, \ -+ .reg_sel = __reg_gate, \ -+ .base_type = _base_type, \ -+ .hw.init = CLK_HW_INIT(_name, \ -+ _parent, &ccu_ddn_ops, _flags), \ -+ } \ -+ } ++#define CCU_DDN_DEFINE(_name, _parent, _reg_ctrl, _num_shift, _num_width, \ ++ _den_shift, _den_width, _pre_div, _flags) \ ++static struct ccu_ddn _name = { \ ++ .common = { \ ++ .reg_ctrl = _reg_ctrl, \ ++ .hw.init = CCU_DDN_INIT(_name, _parent, _flags), \ ++ }, \ ++ .num_mask = GENMASK(_num_shift + _num_width - 1, _num_shift), \ ++ .num_shift = _num_shift, \ ++ .den_mask = GENMASK(_den_shift + _den_width - 1, _den_shift), \ ++ .den_shift = _den_shift, \ ++ .pre_div = _pre_div, \ ++} + +static inline struct ccu_ddn *hw_to_ccu_ddn(struct clk_hw *hw) +{ @@ -55938,853 +57871,153 @@ index 000000000000..92a4e3e46262 + return container_of(common, struct ccu_ddn, common); +} + -+extern const struct clk_ops ccu_ddn_ops; -+ -+#endif -diff --git a/drivers/clk/spacemit/ccu_ddr.c b/drivers/clk/spacemit/ccu_ddr.c -new file mode 100644 -index 000000000000..ffd8650a6e79 ---- /dev/null -+++ b/drivers/clk/spacemit/ccu_ddr.c -@@ -0,0 +1,272 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Spacemit clock type ddr -+ * -+ * Copyright (c) 2023, spacemit Corporation. -+ * -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include "ccu_ddr.h" -+ -+#define PMU_AP_IMR (0x098) -+#define AP_DCLK_FC_DONE_INT_MSK BIT(15) -+#define DCLK_FC_DONE_INT_MSK BIT(4) -+ -+#define PMU_AP_ISR (0x0a0) -+#define AP_DCLK_FC_DONE_INT_STS BIT(15) -+#define DCLK_FC_DONE_INT_STS BIT(4) -+#define AP_FC_STS BIT(1) -+ -+#define DFC_AP (0x180) -+#define DFC_FREQ_LV 0x1 -+#define DFC_REQ BIT(0) -+ -+#define DFC_STATUS (0x188) -+#define DFC_CAUSE_SHIFT 0x7 -+#define DFC_STS BIT(0) -+ -+/* enable/disable ddr frequency change done interrupt */ -+static void ccu_ddr_enable_dfc_int(struct ccu_common *common, bool enable) -+{ -+ u32 val; -+ unsigned long flags; -+ -+ spin_lock_irqsave(common->lock, flags); -+ val = readl(common->base + PMU_AP_IMR); -+ if (enable) -+ val |= AP_DCLK_FC_DONE_INT_MSK; -+ else -+ val &= ~AP_DCLK_FC_DONE_INT_MSK; -+ -+ writel(val, common->base + PMU_AP_IMR); -+ spin_unlock_irqrestore(common->lock, flags); -+} -+ -+/* clear ddr frequency change done interrupt status*/ -+static void ccu_ddr_clear_dfc_int_status(struct ccu_common *common) -+{ -+ u32 val; -+ unsigned long flags; -+ -+ spin_lock_irqsave(common->lock, flags); -+ val = readl(common->base + PMU_AP_ISR); -+ val &= ~(AP_DCLK_FC_DONE_INT_STS | AP_FC_STS); -+ writel(val, common->base + PMU_AP_ISR); -+ spin_unlock_irqrestore(common->lock, flags); -+} -+ -+static int ccu_ddr_wait_freq_change_done(struct ccu_common *common) -+{ -+ int timeout = 100; -+ u32 val; -+ -+ while (--timeout) { -+ udelay(10); -+ val = readl(common->base + PMU_AP_ISR); -+ if (val & AP_DCLK_FC_DONE_INT_STS) -+ break; -+ } -+ if (!timeout) { -+ pr_err("%s: wait dfc done timeout!\n", __func__); -+ return -EBUSY; -+ } -+ return 0; -+} -+ -+static int ccu_ddr_freq_chg(struct ccu_common *common, -+ struct ccu_mux_config *mux, u8 level) -+{ -+ u32 reg; -+ u32 timeout; -+ unsigned long flags; -+ -+ if (level > MAX_FREQ_LV) { -+ pr_err("%s: invalid %d freq level\n", __func__, level); -+ return -EINVAL; -+ } -+ -+ /* check if dfc in progress */ -+ timeout = 1000; -+ while (--timeout) { -+ if (!(readl(common->base + DFC_STATUS) & DFC_STS)) -+ break; -+ udelay(10); -+ } -+ -+ if (!timeout) { -+ pr_err("%s: another dfc is in pregress. status:0x%x\n", -+ __func__, readl(common->base + DFC_STATUS)); -+ return -EBUSY; -+ } -+ -+ spin_lock_irqsave(common->lock, flags); -+ reg = readl(common->base + common->reg_sel); -+ reg &= ~GENMASK(mux->width + mux->shift - 1, mux->shift); -+ writel(reg | (level << mux->shift) | common->fc, -+ common->base + common->reg_sel); -+ spin_unlock_irqrestore(common->lock, flags); -+ -+ timeout = 1000; -+ while (--timeout) { -+ udelay(10); -+ if (!(readl(common->base + DFC_STATUS) & DFC_STS)) -+ break; -+ } -+ -+ if (!timeout) { -+ pr_err("dfc error! status:0x%x\n", -+ readl(common->base + DFC_STATUS)); -+ return -EBUSY; -+ } -+ -+ return 0; -+} -+ -+static unsigned long ccu_ddr_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ return parent_rate; -+} -+ -+static long ccu_ddr_round_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long *prate) -+{ -+ return rate; -+} -+ -+unsigned long ccu_ddr_calc_best_rate(struct clk_hw *hw, unsigned long rate, -+ u32 *mux_val) -+{ -+ struct ccu_ddr *ddr = hw_to_ccu_ddr(hw); -+ struct ccu_common *common = &ddr->common; -+ struct clk_hw *parent; -+ unsigned long parent_rate = 0, best_rate = 0; -+ u32 i; -+ -+ for (i = 0; i < common->num_parents; i++) { -+ parent = clk_hw_get_parent_by_index(hw, i); -+ if (!parent) -+ continue; -+ parent_rate = clk_get_rate(clk_hw_get_clk(parent, -+ common->name)); -+ if (abs(parent_rate - rate) < abs(best_rate - rate)) { -+ best_rate = parent_rate; -+ *mux_val = i; -+ } -+ } -+ return best_rate; -+} -+ -+static int ccu_ddr_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct ccu_ddr *ddr = hw_to_ccu_ddr(hw); -+ struct ccu_common *common = &ddr->common; -+ struct ccu_mux_config *mux = ddr->mux ? ddr->mux : NULL; -+ unsigned long best_rate = 0; -+ u32 cur_mux, mux_val = 0; -+ u32 reg = 0; -+ -+ if (!mux) -+ return 0; -+ -+ best_rate = ccu_ddr_calc_best_rate(hw, rate, &mux_val); -+ -+ reg = readl(common->base + common->reg_sel); -+ if (mux) { -+ cur_mux = reg >> mux->shift; -+ cur_mux &= (1 << mux->width) - 1; -+ if (cur_mux != mux_val) -+ clk_hw_set_parent(hw, clk_hw_get_parent_by_index(hw, mux_val)); -+ } -+ return 0; -+} -+ -+static u8 ccu_ddr_get_parent(struct clk_hw *hw) -+{ -+ struct ccu_ddr *ddr = hw_to_ccu_ddr(hw); -+ struct ccu_common *common = &ddr->common; -+ struct ccu_mux_config *mux = ddr->mux; -+ u32 reg; -+ u8 parent; -+ -+ if (!mux) -+ return 0; -+ -+ reg = readl(common->base + common->reg_sel); -+ -+ parent = reg >> mux->shift; -+ parent &= (1 << mux->width) - 1; -+ -+ if (mux->table) { -+ int num_parents = clk_hw_get_num_parents(&common->hw); -+ int i; -+ -+ for (i = 0; i < num_parents; i++) -+ if (mux->table[i] == parent) -+ return i; -+ } -+ return parent; -+} -+ -+static int ccu_ddr_set_parent(struct clk_hw *hw, u8 index) -+{ -+ struct ccu_ddr *ddr = hw_to_ccu_ddr(hw); -+ struct ccu_common *common = &ddr->common; -+ struct ccu_mux_config *mux = ddr->mux; -+ int ret = 0; -+ -+ if (!mux) -+ return 0; -+ -+ if (mux->table) -+ index = mux->table[index]; -+ -+ /* request change begin */ -+ ccu_ddr_enable_dfc_int(common, true); -+ -+ /* change parent*/ -+ ret = ccu_ddr_freq_chg(common, mux, index); -+ if (ret < 0) { -+ pr_err("%s: ddr_freq_chg fail. ret = %d\n", __func__, ret); -+ return ret; -+ } -+ -+ /* wait for frequency change done */ -+ ret = ccu_ddr_wait_freq_change_done(common); -+ if (ret < 0) { -+ pr_err("%s: wait_freq_change_done timeout. ret = %d\n", -+ __func__, ret); -+ return ret; -+ } -+ ccu_ddr_clear_dfc_int_status(common); -+ ccu_ddr_enable_dfc_int(common, false); -+ -+ return 0; -+} -+ -+static int ccu_ddr_determine_rate(struct clk_hw *hw, -+ struct clk_rate_request *req) -+{ -+ unsigned long best_rate = req->rate; -+ u32 mux_val = 0; -+ -+ best_rate = ccu_ddr_calc_best_rate(hw, req->rate, &mux_val); -+ req->rate = best_rate; -+ return 0; -+} -+ -+const struct clk_ops ccu_ddr_ops = { -+ .get_parent = ccu_ddr_get_parent, -+ .set_parent = ccu_ddr_set_parent, -+ .determine_rate = ccu_ddr_determine_rate, -+ .round_rate = ccu_ddr_round_rate, -+ .recalc_rate = ccu_ddr_recalc_rate, -+ .set_rate = ccu_ddr_set_rate, -+}; -+ -diff --git a/drivers/clk/spacemit/ccu_ddr.h b/drivers/clk/spacemit/ccu_ddr.h -new file mode 100644 -index 000000000000..c8f648366e3c ---- /dev/null -+++ b/drivers/clk/spacemit/ccu_ddr.h -@@ -0,0 +1,44 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* Copyright (c) 2023, spacemit Corporation. */ -+ -+#ifndef _CCU_DDR_H_ -+#define _CCU_DDR_H_ -+ -+#include -+#include "ccu-spacemit-k1.h" -+#include "ccu_mix.h" -+ -+struct ccu_ddr { -+ struct ccu_mux_config *mux; -+ struct ccu_common common; -+}; -+ -+#define MAX_FREQ_LV 7 -+ -+#define SPACEMIT_CCU_DDR_FC(_struct, _name, _parents, _base_type, \ -+ _reg, _fc, _shift, _width, _flags) \ -+ struct ccu_ddr _struct = { \ -+ .mux = CCU_MUX_INIT(_shift, _width, NULL, 0), \ -+ .common = { \ -+ .reg_sel = _reg, \ -+ .fc = _fc, \ -+ .base_type = _base_type, \ -+ .name = _name, \ -+ .parent_names = _parents, \ -+ .num_parents = ARRAY_SIZE(_parents), \ -+ .hw.init = CLK_HW_INIT_PARENTS(_name, \ -+ _parents, &ccu_ddr_ops, \ -+ (_flags) | CLK_GET_RATE_NOCACHE), \ -+ } \ -+ } -+ -+static inline struct ccu_ddr *hw_to_ccu_ddr(struct clk_hw *hw) -+{ -+ struct ccu_common *common = hw_to_ccu_common(hw); -+ -+ return container_of(common, struct ccu_ddr, common); -+} -+ -+extern const struct clk_ops ccu_ddr_ops; -+ -+#endif /* _CCU_DDR_H_ */ -diff --git a/drivers/clk/spacemit/ccu_dpll.c b/drivers/clk/spacemit/ccu_dpll.c -new file mode 100644 -index 000000000000..ff8b699e1ba2 ---- /dev/null -+++ b/drivers/clk/spacemit/ccu_dpll.c -@@ -0,0 +1,124 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Spacemit clock type pll -+ * -+ * Copyright (c) 2023, spacemit Corporation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "ccu_dpll.h" -+ -+#define DPLL_MIN_FREQ 1700000000 -+#define DPLL_MAX_FREQ 3400000000 -+ -+#define pll_readl(reg) readl(reg) -+#define pll_readl_pll_swcr1(p) pll_readl(p.base + p.reg_ctrl) -+#define pll_readl_pll_swcr2(p) pll_readl(p.base + p.reg_sel) -+ -+#define pll_writel(val, reg) writel(val, reg) -+#define pll_writel_pll_swcr1(val, p) pll_writel(val, p.base + p.reg_ctrl) -+#define pll_writel_pll_swcr2(val, p) pll_writel(val, p.base + p.reg_sel) -+ -+/* unified dpllx_swcr1 for dpll1~2 */ -+union dpllx_swcr1 { -+ struct { -+ unsigned int reg0:8; -+ unsigned int reg1:8; -+ unsigned int reg2:8; -+ unsigned int reg3:8; -+ } b; -+ unsigned int v; -+}; -+ -+/* unified dpllx_swcr2 for dpll1~2 */ -+union dpllx_swcr2 { -+ struct { -+ unsigned int reg4:8; -+ unsigned int reg5:8; -+ unsigned int reg6:8; -+ unsigned int reg7:8; -+ } b; -+ unsigned int v; -+}; -+ -+/* frequency unit Mhz, return pll vco freq */ -+static unsigned long __get_vco_freq(struct clk_hw *hw) -+{ -+ unsigned int reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, size, i; -+ struct ccu_dpll_rate_tbl *freq_pll_regs_table, *pll_reg; -+ struct ccu_dpll *p = hw_to_ccu_dpll(hw); -+ union dpllx_swcr1 swcr1; -+ union dpllx_swcr2 swcr2; -+ -+ swcr1.v = pll_readl_pll_swcr1(p->common); -+ swcr2.v = pll_readl_pll_swcr2(p->common); -+ -+ reg0 = swcr1.b.reg0; -+ reg1 = swcr1.b.reg1; -+ reg2 = swcr1.b.reg2; -+ reg3 = swcr1.b.reg3; -+ reg4 = swcr2.b.reg4; -+ reg5 = swcr2.b.reg5; -+ reg6 = swcr2.b.reg6; -+ reg7 = swcr2.b.reg7; -+ -+ freq_pll_regs_table = p->dpll.rate_tbl; -+ size = p->dpll.tbl_size; -+ -+ for (i = 0; i < size; i++) { -+ pll_reg = &freq_pll_regs_table[i]; -+ if (pll_reg->reg0 == reg0 && pll_reg->reg1 == reg1 && -+ pll_reg->reg2 == reg2 && pll_reg->reg3 == reg3 && -+ pll_reg->reg4 == reg4 && pll_reg->reg5 == reg5 && -+ pll_reg->reg6 == reg6 && pll_reg->reg7 == reg7) -+ return pll_reg->rate; -+ } -+ -+ pr_err("Unknown rate for clock %s\n", __clk_get_name(hw->clk)); -+ return 0; -+} -+ -+static unsigned long ccu_dpll_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ return __get_vco_freq(hw); -+} -+ -+static long ccu_dpll_round_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long *prate) -+{ -+ struct ccu_dpll *p = hw_to_ccu_dpll(hw); -+ unsigned long max_rate = 0; -+ unsigned int i; -+ struct ccu_dpll_config *params = &p->dpll; -+ -+ if (rate > DPLL_MAX_FREQ || rate < DPLL_MIN_FREQ) { -+ pr_err("%lu rate out of range!\n", rate); -+ return -EINVAL; -+ } -+ -+ if (params->rate_tbl) { -+ for (i = 0; i < params->tbl_size; i++) { -+ if (params->rate_tbl[i].rate <= rate) { -+ if (max_rate < params->rate_tbl[i].rate) -+ max_rate = params->rate_tbl[i].rate; -+ } -+ } -+ } else { -+ pr_err("don't find freq table for pll\n"); -+ } -+ -+ return max_rate; -+} -+ -+const struct clk_ops ccu_dpll_ops = { -+ .recalc_rate = ccu_dpll_recalc_rate, -+ .round_rate = ccu_dpll_round_rate, -+}; -+ -diff --git a/drivers/clk/spacemit/ccu_dpll.h b/drivers/clk/spacemit/ccu_dpll.h -new file mode 100644 -index 000000000000..6bbf62bb7e19 ---- /dev/null -+++ b/drivers/clk/spacemit/ccu_dpll.h -@@ -0,0 +1,76 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* Copyright (c) 2023, spacemit Corporation. */ -+ -+#ifndef _CCU_DPLL_H_ -+#define _CCU_DPLL_H_ -+ -+#include -+#include -+#include "ccu-spacemit-k1.h" -+ -+struct ccu_dpll_rate_tbl { -+ unsigned long long rate; -+ u32 reg0; -+ u32 reg1; -+ u32 reg2; -+ u32 reg3; -+ u32 reg4; -+ u32 reg5; -+ u32 reg6; -+ u32 reg7; -+}; -+ -+struct ccu_dpll_config { -+ struct ccu_dpll_rate_tbl *rate_tbl; -+ u32 tbl_size; -+}; -+ -+#define DPLL_RATE(_rate, _reg0, _reg1, _reg2, _reg3, _reg4, \ -+ _reg5, _reg6, _reg7) \ -+ { \ -+ .rate = (_rate), \ -+ .reg0 = (_reg0), \ -+ .reg1 = (_reg1), \ -+ .reg2 = (_reg2), \ -+ .reg3 = (_reg3), \ -+ .reg4 = (_reg4), \ -+ .reg5 = (_reg5), \ -+ .reg6 = (_reg6), \ -+ .reg7 = (_reg7), \ -+ } -+ -+struct ccu_dpll { -+ struct ccu_dpll_config dpll; -+ struct ccu_common common; -+}; -+ -+#define _SPACEMIT_CCU_DPLL_CONFIG(_table, _size) \ -+ { \ -+ .rate_tbl = (struct ccu_dpll_rate_tbl *)_table, \ -+ .tbl_size = _size, \ -+ } -+ -+#define SPACEMIT_CCU_DPLL(_struct, _name, _table, _size, _base_type, \ -+ _reg_ctrl, _reg_sel, _is_pll, _flags) \ -+ struct ccu_dpll _struct = { \ -+ .dpll = _SPACEMIT_CCU_DPLL_CONFIG(_table, _size), \ -+ .common = { \ -+ .reg_ctrl = _reg_ctrl, \ -+ .reg_sel = _reg_sel, \ -+ .base_type = _base_type, \ -+ .is_pll = 0, \ -+ .hw.init = CLK_HW_INIT_NO_PARENT(_name, \ -+ &ccu_dpll_ops, _flags), \ -+ } \ -+ } -+ -+static inline struct ccu_dpll *hw_to_ccu_dpll(struct clk_hw *hw) -+{ -+ struct ccu_common *common = hw_to_ccu_common(hw); -+ -+ return container_of(common, struct ccu_dpll, common); -+} -+ -+extern const struct clk_ops ccu_dpll_ops; ++extern const struct clk_ops spacemit_ccu_ddn_ops; + +#endif diff --git a/drivers/clk/spacemit/ccu_mix.c b/drivers/clk/spacemit/ccu_mix.c new file mode 100644 -index 000000000000..baa341090f53 +index 000000000000..30f7b664c464 --- /dev/null +++ b/drivers/clk/spacemit/ccu_mix.c -@@ -0,0 +1,502 @@ +@@ -0,0 +1,278 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* -+ * Spacemit clock type mix(div/mux/gate/factor) -+ * -+ * Copyright (c) 2023, spacemit Corporation. ++ * Copyright (c) 2024 SpacemiT Technology Co. Ltd ++ * Copyright (c) 2024-2025 Haylen Chu + * ++ * MIX clock type is the combination of mux, factor or divider, and gate + */ ++ +#include -+#include -+#include -+#include -+#include -+#include ++ +#include "ccu_mix.h" + -+#define TIMEOUT_LIMIT (20000) -+static int twsi8_reg_val = 0x04; -+const char *tswi8_clk_name = "twsi8_clk"; ++#define MIX_FC_TIMEOUT_US 10000 ++#define MIX_FC_DELAY_US 5 + -+static void ccu_mix_disable(struct clk_hw *hw) ++static void ccu_gate_disable(struct clk_hw *hw) +{ + struct ccu_mix *mix = hw_to_ccu_mix(hw); -+ struct ccu_common *common = &mix->common; -+ struct ccu_gate_config *gate = mix->gate; -+ unsigned long flags = 0; -+ unsigned long rate; -+ u32 tmp; ++ struct ccu_gate_config *gate = &mix->gate; + -+ if (!gate) -+ return; -+ -+ if (!strcmp(common->name, tswi8_clk_name)) { -+ twsi8_reg_val &= ~gate->gate_mask; -+ twsi8_reg_val |= gate->val_disable; -+ tmp = twsi8_reg_val; -+ if (common->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 || -+ common->reg_type == CLK_DIV_TYPE_2REG_FC_V4) -+ writel(tmp, common->base + common->reg_sel); -+ else -+ writel(tmp, common->base + common->reg_ctrl); -+ return; -+ } -+ -+ if (common->lock) -+ spin_lock_irqsave(common->lock, flags); -+ -+ if (common->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 || -+ common->reg_type == CLK_DIV_TYPE_2REG_FC_V4) -+ tmp = readl(common->base + common->reg_sel); -+ else -+ tmp = readl(common->base + common->reg_ctrl); -+ -+ tmp &= ~gate->gate_mask; -+ tmp |= gate->val_disable; -+ -+ if (common->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 || -+ common->reg_type == CLK_DIV_TYPE_2REG_FC_V4) -+ writel(tmp, common->base + common->reg_sel); ++ if (gate->flags & CCU_GATE_INVERT_FLAG) ++ ccu_update(&mix->common, ctrl, gate->mask, gate->mask); + else -+ writel(tmp, common->base + common->reg_ctrl); -+ -+ if (common->lock) -+ spin_unlock_irqrestore(common->lock, flags); -+ -+ if (gate->flags & SPACEMIT_CLK_GATE_NEED_DELAY) { -+ rate = clk_hw_get_rate(&common->hw); -+ -+ if (rate == 0) -+ pr_err("clock rate of %s is 0.\n", -+ clk_hw_get_name(&common->hw)); -+ else -+ udelay(DIV_ROUND_UP(2000000, rate)); -+ } ++ ccu_update(&mix->common, ctrl, mix->gate.mask, 0); +} + -+static int ccu_mix_enable(struct clk_hw *hw) ++static int ccu_gate_enable(struct clk_hw *hw) +{ + struct ccu_mix *mix = hw_to_ccu_mix(hw); -+ struct ccu_common *common = &mix->common; -+ struct ccu_gate_config *gate = mix->gate; -+ unsigned long flags = 0; -+ unsigned long rate; -+ u32 tmp; -+ u32 val = 0; -+ int timeout_power = 1; -+ -+ if (!gate) -+ return 0; -+ -+ if (!strcmp(common->name, tswi8_clk_name)) { -+ twsi8_reg_val &= ~gate->gate_mask; -+ twsi8_reg_val |= gate->val_enable; -+ tmp = twsi8_reg_val; -+ if (common->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 || -+ common->reg_type == CLK_DIV_TYPE_2REG_FC_V4) -+ writel(tmp, common->base + common->reg_sel); -+ else -+ writel(tmp, common->base + common->reg_ctrl); -+ return 0; -+ } ++ struct ccu_gate_config *gate = &mix->gate; + -+ if (common->lock) -+ spin_lock_irqsave(common->lock, flags); -+ -+ if (common->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 || -+ common->reg_type == CLK_DIV_TYPE_2REG_FC_V4) -+ tmp = readl(common->base + common->reg_sel); -+ else -+ tmp = readl(common->base + common->reg_ctrl); -+ -+ tmp &= ~gate->gate_mask; -+ tmp |= gate->val_enable; -+ -+ if (common->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 || -+ common->reg_type == CLK_DIV_TYPE_2REG_FC_V4) -+ writel(tmp, common->base + common->reg_sel); -+ else -+ writel(tmp, common->base + common->reg_ctrl); -+ -+ if (common->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 || -+ common->reg_type == CLK_DIV_TYPE_2REG_FC_V4) -+ val = readl(common->base + common->reg_sel); ++ if (gate->flags & CCU_GATE_INVERT_FLAG) ++ ccu_update(&mix->common, ctrl, gate->mask, 0); + else -+ val = readl(common->base + common->reg_ctrl); -+ -+ if (common->lock) -+ spin_unlock_irqrestore(common->lock, flags); -+ -+ while ((val & gate->gate_mask) != gate->val_enable && -+ (timeout_power < TIMEOUT_LIMIT)) { -+ udelay(timeout_power); -+ if (common->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 || -+ common->reg_type == CLK_DIV_TYPE_2REG_FC_V4) -+ val = readl(common->base + common->reg_sel); -+ else -+ val = readl(common->base + common->reg_ctrl); -+ timeout_power *= 10; -+ } -+ -+ if (timeout_power > 1) { -+ if (val == tmp) -+ pr_err("write clk_gate %s timeout occur, read pass after %d us delay\n", -+ clk_hw_get_name(&common->hw), timeout_power); -+ else -+ pr_err("write clk_gate %s timeout after %d us!\n", -+ clk_hw_get_name(&common->hw), timeout_power); -+ } -+ -+ if (gate->flags & SPACEMIT_CLK_GATE_NEED_DELAY) { -+ rate = clk_hw_get_rate(&common->hw); -+ -+ if (rate == 0) -+ pr_err("clock rate of %s is 0.\n", -+ clk_hw_get_name(&common->hw)); -+ else -+ udelay(DIV_ROUND_UP(2000000, rate)); -+ } ++ ccu_update(&mix->common, ctrl, gate->mask, gate->mask); + + return 0; +} + -+static int ccu_mix_is_enabled(struct clk_hw *hw) ++static int ccu_gate_is_enabled(struct clk_hw *hw) +{ + struct ccu_mix *mix = hw_to_ccu_mix(hw); -+ struct ccu_common *common = &mix->common; -+ struct ccu_gate_config *gate = mix->gate; -+ unsigned long flags = 0; -+ u32 tmp; ++ struct ccu_gate_config *gate = &mix->gate; + -+ if (!gate) -+ return 1; -+ -+ if (!strcmp(common->name, tswi8_clk_name)) -+ return (twsi8_reg_val & gate->gate_mask) == gate->val_enable; -+ -+ if (common->lock) -+ spin_lock_irqsave(common->lock, flags); -+ -+ if (common->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 || -+ common->reg_type == CLK_DIV_TYPE_2REG_FC_V4) -+ tmp = readl(common->base + common->reg_sel); ++ if (gate->flags & CCU_GATE_INVERT_FLAG) ++ return (ccu_read(&mix->common, ctrl) & gate->mask) == 0; + else -+ tmp = readl(common->base + common->reg_ctrl); ++ return (ccu_read(&mix->common, ctrl) & gate->mask) == gate->mask; ++} + -+ if (common->lock) -+ spin_unlock_irqrestore(common->lock, flags); ++static unsigned long ccu_factor_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct ccu_mix *mix = hw_to_ccu_mix(hw); + -+ return (tmp & gate->gate_mask) == gate->val_enable; ++ return parent_rate * mix->factor.mul / mix->factor.div; +} + -+static unsigned long ccu_mix_recalc_rate(struct clk_hw *hw, ++static unsigned long ccu_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_mix *mix = hw_to_ccu_mix(hw); -+ struct ccu_common *common = &mix->common; -+ struct ccu_div_config *div = mix->div; ++ struct ccu_div_config *div = &mix->div; + unsigned long val; -+ u32 reg; + -+ if (!div) { -+ if (mix->factor) -+ parent_rate = parent_rate * mix->factor->mul / mix->factor->div; -+ return parent_rate; -+ } -+ -+ if (common->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 || -+ common->reg_type == CLK_DIV_TYPE_2REG_FC_V4) -+ reg = readl(common->base + common->reg_sel); -+ else -+ reg = readl(common->base + common->reg_ctrl); -+ -+ val = reg >> div->shift; ++ val = ccu_read(&mix->common, ctrl) >> div->shift; + val &= (1 << div->width) - 1; + -+ val = divider_recalc_rate(hw, parent_rate, val, div->table, -+ div->flags, div->width); -+ -+ return val; ++ return divider_recalc_rate(hw, parent_rate, val, NULL, 0, div->width); +} + ++/* ++ * Some clocks require a "FC" (frequency change) bit to be set after changing ++ * their rates or reparenting. This bit will be automatically cleared by ++ * hardware in MIX_FC_TIMEOUT_US, which indicates the operation is completed. ++ */ +static int ccu_mix_trigger_fc(struct clk_hw *hw) +{ -+ struct ccu_mix *mix = hw_to_ccu_mix(hw); -+ struct ccu_common *common = &mix->common; -+ unsigned long val = 0; -+ -+ int ret = 0, timeout = 50; ++ struct ccu_common *common = hw_to_ccu_common(hw); ++ unsigned int val; + -+ if (common->reg_type == CLK_DIV_TYPE_1REG_FC_V2 || -+ common->reg_type == CLK_DIV_TYPE_2REG_FC_V4 || -+ common->reg_type == CLK_DIV_TYPE_1REG_FC_DIV_V5 || -+ common->reg_type == CLK_DIV_TYPE_1REG_FC_MUX_V6) { -+ timeout = 50; -+ val = readl(common->base + common->reg_ctrl); -+ val |= common->fc; -+ writel(val, common->base + common->reg_ctrl); ++ if (common->reg_fc) ++ return 0; + -+ do { -+ val = readl(common->base + common->reg_ctrl); -+ timeout--; -+ if (!(val & common->fc)) -+ break; -+ } while (timeout); ++ ccu_update(common, fc, common->mask_fc, common->mask_fc); + -+ if (timeout == 0) { -+ timeout = 5000; -+ do { -+ val = readl(common->base + common->reg_ctrl); -+ timeout--; -+ if (!(val & common->fc)) -+ break; -+ } while (timeout); -+ if (timeout != 0) -+ ret = 0; -+ else -+ ret = -1; -+ } -+ } ++ return regmap_read_poll_timeout_atomic(common->regmap, common->reg_fc, ++ val, !(val & common->mask_fc), ++ MIX_FC_DELAY_US, ++ MIX_FC_TIMEOUT_US); ++} + -+ return ret; ++static long ccu_factor_round_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long *prate) ++{ ++ return ccu_factor_recalc_rate(hw, *prate); +} + -+static long ccu_mix_round_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long *prate) ++static int ccu_factor_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) +{ -+ return rate; ++ return 0; +} + -+unsigned long ccu_mix_calc_best_rate(struct clk_hw *hw, -+ unsigned long rate, u32 *mux_val, -+ u32 *div_val) ++static unsigned long ++ccu_mix_calc_best_rate(struct clk_hw *hw, unsigned long rate, ++ struct clk_hw **best_parent, ++ unsigned long *best_parent_rate, ++ u32 *div_val) +{ + struct ccu_mix *mix = hw_to_ccu_mix(hw); -+ struct ccu_common *common = &mix->common; -+ struct ccu_div_config *div = mix->div ? mix->div : NULL; -+ struct clk *clk; -+ struct clk_hw *parent; -+ unsigned long parent_rate = 0, best_rate = 0; -+ u32 i, j, div_max; ++ unsigned int parent_num = clk_hw_get_num_parents(hw); ++ struct ccu_div_config *div = &mix->div; ++ u32 div_max = 1 << div->width; ++ unsigned long best_rate = 0; ++ ++ for (int i = 0; i < parent_num; i++) { ++ struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i); ++ unsigned long parent_rate; + -+ for (i = 0; i < common->num_parents; i++) { -+ parent = clk_hw_get_parent_by_index(hw, i); + if (!parent) + continue; -+ clk = clk_hw_get_clk(parent, common->name); -+ parent_rate = clk_get_rate(clk); + -+ if (div) -+ div_max = 1 << div->width; -+ else -+ div_max = 1; ++ parent_rate = clk_hw_get_rate(parent); ++ ++ for (int j = 1; j <= div_max; j++) { ++ unsigned long tmp = DIV_ROUND_CLOSEST_ULL(parent_rate, j); ++ ++ if (abs(tmp - rate) < abs(best_rate - rate)) { ++ best_rate = tmp; ++ ++ if (div_val) ++ *div_val = j - 1; + -+ for (j = 1; j <= div_max; j++) { -+ if (abs(parent_rate / j - rate) -+ < abs(best_rate - rate)) { -+ best_rate = DIV_ROUND_UP_ULL(parent_rate, j); -+ *mux_val = i; -+ *div_val = j - 1; ++ if (best_parent) { ++ *best_parent = parent; ++ *best_parent_rate = parent_rate; ++ } + } + } + } @@ -56795,6 +58028,10 @@ index 000000000000..baa341090f53 +static int ccu_mix_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ ++ req->rate = ccu_mix_calc_best_rate(hw, req->rate, ++ &req->best_parent_hw, ++ &req->best_parent_rate, ++ NULL); + return 0; +} + @@ -56803,213 +58040,151 @@ index 000000000000..baa341090f53 +{ + struct ccu_mix *mix = hw_to_ccu_mix(hw); + struct ccu_common *common = &mix->common; -+ struct ccu_div_config *div = mix->div ? mix->div : NULL; -+ struct ccu_mux_config *mux = mix->mux ? mix->mux : NULL; -+ struct clk_hw *parent; -+ unsigned long best_rate = 0; -+ unsigned long flags; -+ u32 cur_mux, cur_div, mux_val = 0, div_val = 0; -+ u32 reg = 0; -+ int ret = 0; ++ struct ccu_div_config *div = &mix->div; ++ u32 current_div, target_div, mask; + -+ if (!div && !mux) -+ return 0; ++ ccu_mix_calc_best_rate(hw, rate, NULL, NULL, &target_div); + -+ best_rate = ccu_mix_calc_best_rate(hw, rate, &mux_val, &div_val); -+ if (!strcmp(common->name, tswi8_clk_name)) { -+ if (mux) { -+ cur_mux = twsi8_reg_val >> mux->shift; -+ cur_mux &= (1 << mux->width) - 1; -+ parent = clk_hw_get_parent_by_index(hw, mux_val); -+ if (cur_mux != mux_val) -+ clk_hw_set_parent(hw, parent); -+ } -+ return 0; -+ } -+ if (common->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 || -+ common->reg_type == CLK_DIV_TYPE_2REG_FC_V4) -+ reg = readl(common->base + common->reg_sel); -+ else -+ reg = readl(common->base + common->reg_ctrl); ++ current_div = ccu_read(common, ctrl) >> div->shift; ++ current_div &= (1 << div->width) - 1; + -+ if (mux) { -+ cur_mux = reg >> mux->shift; -+ cur_mux &= (1 << mux->width) - 1; -+ parent = clk_hw_get_parent_by_index(hw, mux_val); -+ if (cur_mux != mux_val) -+ clk_hw_set_parent(hw, parent); -+ } -+ -+ if (div) { -+ cur_div = reg >> div->shift; -+ cur_div &= (1 << div->width) - 1; -+ if (cur_div == div_val) -+ return 0; -+ } else { ++ if (current_div == target_div) + return 0; -+ } + -+ spin_lock_irqsave(common->lock, flags); -+ if (common->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 || -+ common->reg_type == CLK_DIV_TYPE_2REG_FC_V4) -+ reg = readl(common->base + common->reg_sel); -+ else -+ reg = readl(common->base + common->reg_ctrl); ++ mask = GENMASK(div->width + div->shift - 1, div->shift); + -+ reg &= ~GENMASK(div->width + div->shift - 1, div->shift); ++ ccu_update(common, ctrl, mask, target_div << div->shift); + -+ if (common->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 || -+ common->reg_type == CLK_DIV_TYPE_2REG_FC_V4) -+ writel(reg | (div_val << div->shift), -+ common->base + common->reg_sel); -+ else -+ writel(reg | (div_val << div->shift), -+ common->base + common->reg_ctrl); -+ -+ if (common->reg_type == CLK_DIV_TYPE_1REG_FC_V2 || -+ common->reg_type == CLK_DIV_TYPE_2REG_FC_V4 || -+ common->reg_type == CLK_DIV_TYPE_1REG_FC_DIV_V5) { -+ ret = ccu_mix_trigger_fc(hw); -+ } -+ spin_unlock_irqrestore(common->lock, flags); -+ -+ if (ret) -+ pr_err("%s of %s timeout\n", __func__, -+ clk_hw_get_name(&common->hw)); -+ -+ return ret; ++ return ccu_mix_trigger_fc(hw); +} + -+static u8 ccu_mix_get_parent(struct clk_hw *hw) ++static u8 ccu_mux_get_parent(struct clk_hw *hw) +{ + struct ccu_mix *mix = hw_to_ccu_mix(hw); -+ struct ccu_common *common = &mix->common; -+ struct ccu_mux_config *mux = mix->mux; -+ u32 reg; ++ struct ccu_mux_config *mux = &mix->mux; + u8 parent; + -+ if (!mux) -+ return 0; -+ -+ if (!strcmp(common->name, tswi8_clk_name)) { -+ parent = twsi8_reg_val >> mux->shift; -+ parent &= (1 << mux->width) - 1; -+ return parent; -+ } -+ -+ if (common->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 || -+ common->reg_type == CLK_DIV_TYPE_2REG_FC_V4) -+ reg = readl(common->base + common->reg_sel); -+ else -+ reg = readl(common->base + common->reg_ctrl); -+ -+ parent = reg >> mux->shift; ++ parent = ccu_read(&mix->common, ctrl) >> mux->shift; + parent &= (1 << mux->width) - 1; + -+ if (mux->table) { -+ int num_parents = clk_hw_get_num_parents(&common->hw); -+ int i; -+ -+ for (i = 0; i < num_parents; i++) -+ if (mux->table[i] == parent) -+ return i; -+ } + return parent; +} + -+static int ccu_mix_set_parent(struct clk_hw *hw, u8 index) ++static int ccu_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct ccu_mix *mix = hw_to_ccu_mix(hw); -+ struct ccu_common *common = &mix->common; -+ struct ccu_mux_config *mux = mix->mux; -+ unsigned long flags; -+ u32 reg = 0; -+ int ret = 0; ++ struct ccu_mux_config *mux = &mix->mux; ++ u32 mask; + -+ if (!mux) -+ return 0; ++ mask = GENMASK(mux->width + mux->shift - 1, mux->shift); + -+ if (mux->table) -+ index = mux->table[index]; -+ -+ if (!strcmp(common->name, tswi8_clk_name)) { -+ twsi8_reg_val &= ~GENMASK(mux->width -+ + mux->shift - 1, mux->shift); -+ twsi8_reg_val |= (index << mux->shift); -+ reg = twsi8_reg_val; -+ if (common->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 || -+ common->reg_type == CLK_DIV_TYPE_2REG_FC_V4) -+ writel(reg, common->base + common->reg_sel); -+ else -+ writel(reg, common->base + common->reg_ctrl); -+ return 0; -+ } ++ ccu_update(&mix->common, ctrl, mask, index << mux->shift); + -+ spin_lock_irqsave(common->lock, flags); ++ return ccu_mix_trigger_fc(hw); ++} + -+ if (common->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 || -+ common->reg_type == CLK_DIV_TYPE_2REG_FC_V4) -+ reg = readl(common->base + common->reg_sel); -+ else -+ reg = readl(common->base + common->reg_ctrl); ++const struct clk_ops spacemit_ccu_gate_ops = { ++ .disable = ccu_gate_disable, ++ .enable = ccu_gate_enable, ++ .is_enabled = ccu_gate_is_enabled, ++}; + -+ reg &= ~GENMASK(mux->width + mux->shift - 1, mux->shift); ++const struct clk_ops spacemit_ccu_factor_ops = { ++ .round_rate = ccu_factor_round_rate, ++ .recalc_rate = ccu_factor_recalc_rate, ++ .set_rate = ccu_factor_set_rate, ++}; + -+ if (common->reg_type == CLK_DIV_TYPE_2REG_NOFC_V3 || -+ common->reg_type == CLK_DIV_TYPE_2REG_FC_V4) -+ writel(reg | (index << mux->shift), -+ common->base + common->reg_sel); -+ else -+ writel(reg | (index << mux->shift), -+ common->base + common->reg_ctrl); ++const struct clk_ops spacemit_ccu_mux_ops = { ++ .determine_rate = ccu_mix_determine_rate, ++ .get_parent = ccu_mux_get_parent, ++ .set_parent = ccu_mux_set_parent, ++}; + -+ if (common->reg_type == CLK_DIV_TYPE_1REG_FC_V2 || -+ common->reg_type == CLK_DIV_TYPE_2REG_FC_V4 || -+ common->reg_type == CLK_DIV_TYPE_1REG_FC_MUX_V6) { -+ ret = ccu_mix_trigger_fc(hw); -+ } -+ spin_unlock_irqrestore(common->lock, flags); ++const struct clk_ops spacemit_ccu_div_ops = { ++ .determine_rate = ccu_mix_determine_rate, ++ .recalc_rate = ccu_div_recalc_rate, ++ .set_rate = ccu_mix_set_rate, ++}; + -+ if (ret) -+ pr_err("%s of %s timeout\n", __func__, -+ clk_hw_get_name(&common->hw)); ++const struct clk_ops spacemit_ccu_factor_gate_ops = { ++ .disable = ccu_gate_disable, ++ .enable = ccu_gate_enable, ++ .is_enabled = ccu_gate_is_enabled, + -+ return 0; -+} ++ .round_rate = ccu_factor_round_rate, ++ .recalc_rate = ccu_factor_recalc_rate, ++ .set_rate = ccu_factor_set_rate, ++}; ++ ++const struct clk_ops spacemit_ccu_mux_gate_ops = { ++ .disable = ccu_gate_disable, ++ .enable = ccu_gate_enable, ++ .is_enabled = ccu_gate_is_enabled, ++ ++ .determine_rate = ccu_mix_determine_rate, ++ .get_parent = ccu_mux_get_parent, ++ .set_parent = ccu_mux_set_parent, ++}; ++ ++const struct clk_ops spacemit_ccu_div_gate_ops = { ++ .disable = ccu_gate_disable, ++ .enable = ccu_gate_enable, ++ .is_enabled = ccu_gate_is_enabled, + -+const struct clk_ops ccu_mix_ops = { -+ .disable = ccu_mix_disable, -+ .enable = ccu_mix_enable, -+ .is_enabled = ccu_mix_is_enabled, -+ .get_parent = ccu_mix_get_parent, -+ .set_parent = ccu_mix_set_parent, + .determine_rate = ccu_mix_determine_rate, -+ .round_rate = ccu_mix_round_rate, -+ .recalc_rate = ccu_mix_recalc_rate, -+ .set_rate = ccu_mix_set_rate, ++ .recalc_rate = ccu_div_recalc_rate, ++ .set_rate = ccu_mix_set_rate, +}; + ++const struct clk_ops spacemit_ccu_mux_div_gate_ops = { ++ .disable = ccu_gate_disable, ++ .enable = ccu_gate_enable, ++ .is_enabled = ccu_gate_is_enabled, ++ ++ .get_parent = ccu_mux_get_parent, ++ .set_parent = ccu_mux_set_parent, ++ ++ .determine_rate = ccu_mix_determine_rate, ++ .recalc_rate = ccu_div_recalc_rate, ++ .set_rate = ccu_mix_set_rate, ++}; ++ ++const struct clk_ops spacemit_ccu_mux_div_ops = { ++ .get_parent = ccu_mux_get_parent, ++ .set_parent = ccu_mux_set_parent, ++ ++ .determine_rate = ccu_mix_determine_rate, ++ .recalc_rate = ccu_div_recalc_rate, ++ .set_rate = ccu_mix_set_rate, ++}; diff --git a/drivers/clk/spacemit/ccu_mix.h b/drivers/clk/spacemit/ccu_mix.h new file mode 100644 -index 000000000000..cd087972d62b +index 000000000000..191a8dc8f941 --- /dev/null +++ b/drivers/clk/spacemit/ccu_mix.h -@@ -0,0 +1,380 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* Copyright (c) 2023, spacemit Corporation. */ +@@ -0,0 +1,246 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (c) 2024 SpacemiT Technology Co. Ltd ++ * Copyright (c) 2024-2025 Haylen Chu ++ */ + +#ifndef _CCU_MIX_H_ +#define _CCU_MIX_H_ + +#include -+#include "ccu-spacemit-k1.h" + -+#define SPACEMIT_CLK_GATE_NEED_DELAY BIT(0) ++#include "ccu_common.h" + ++/** ++ * struct ccu_gate_config - Gate configuration ++ * ++ * @mask: Mask to enable the gate. Some clocks may have more than one bit ++ * set in this field. ++ */ +struct ccu_gate_config { -+ u32 gate_mask; -+ u32 val_enable; -+ u32 val_disable; ++ u32 mask; + u32 flags; +}; + @@ -57021,349 +58196,202 @@ index 000000000000..cd087972d62b +struct ccu_mux_config { + u8 shift; + u8 width; -+ const u8 *table; -+ u32 flags; +}; + +struct ccu_div_config { + u8 shift; + u8 width; -+ u32 max; -+ u32 offset; -+ u32 flags; -+ struct clk_div_table *table; +}; + +struct ccu_mix { -+ struct ccu_gate_config *gate; -+ struct ccu_factor_config *factor; -+ struct ccu_div_config *div; -+ struct ccu_mux_config *mux; ++ struct ccu_factor_config factor; ++ struct ccu_gate_config gate; ++ struct ccu_div_config div; ++ struct ccu_mux_config mux; + struct ccu_common common; +}; + -+#define CCU_GATE_INIT(_gate_mask, _val_enable, _val_disable, _flags) \ -+ (&(struct ccu_gate_config) { \ -+ .gate_mask = _gate_mask, \ -+ .val_enable = _val_enable, \ -+ .val_disable = _val_disable, \ -+ .flags = _flags, \ -+ }) -+ -+#define CCU_FACTOR_INIT(_div, _mul) \ -+ (&(struct ccu_factor_config) { \ -+ .div = _div, \ -+ .mul = _mul, \ -+ }) ++#define CCU_GATE_INIT(_mask) { .mask = _mask } ++#define CCU_FACTOR_INIT(_div, _mul) { .div = _div, .mul = _mul } ++#define CCU_MUX_INIT(_shift, _width) { .shift = _shift, .width = _width } ++#define CCU_DIV_INIT(_shift, _width) { .shift = _shift, .width = _width } ++#define CCU_GATE_FLAGS_INIT(_mask, _flags) { .mask = _mask, .flags = _flags } + -+#define CCU_MUX_INIT(_shift, _width, _table, _flags) \ -+ (&(struct ccu_mux_config) { \ -+ .shift = _shift, \ -+ .width = _width, \ -+ .table = _table, \ -+ .flags = _flags, \ -+ }) -+ -+#define CCU_DIV_INIT(_shift, _width, _table, _flags) \ -+ (&(struct ccu_div_config) { \ -+ .shift = _shift, \ -+ .width = _width, \ -+ .flags = _flags, \ -+ .table = _table, \ -+ }) ++#define CCU_PARENT_HW(_parent) { .hw = &_parent.common.hw } ++#define CCU_PARENT_NAME(_name) { .fw_name = #_name } + -+#define SPACEMIT_CCU_GATE(_struct, _name, _parent, _base_type, _reg, \ -+ _gate_mask, _val_enable, _val_disable, _flags) \ -+ struct ccu_mix _struct = { \ -+ .gate = CCU_GATE_INIT(_gate_mask, _val_enable, \ -+ _val_disable, 0), \ -+ .common = { \ -+ .reg_ctrl = _reg, \ -+ .base_type = _base_type, \ -+ .name = _name, \ -+ .num_parents = 1, \ -+ .hw.init = CLK_HW_INIT(_name, _parent, \ -+ &ccu_mix_ops, _flags), \ -+ } \ -+ } -+ -+#define SPACEMIT_CCU_GATE_NO_PARENT(_struct, _name, _parent, \ -+ _base_type, _reg, _gate_mask, _val_enable, \ -+ _val_disable, _flags) \ -+ struct ccu_mix _struct = { \ -+ .gate = CCU_GATE_INIT(_gate_mask, _val_enable, \ -+ _val_disable, 0), \ -+ .common = { \ -+ .reg_ctrl = _reg, \ -+ .base_type = _base_type, \ -+ .name = _name, \ -+ .num_parents = 0, \ -+ .hw.init = CLK_HW_INIT_NO_PARENT(_name, \ -+ &ccu_mix_ops, _flags), \ -+ } \ ++#define CCU_MIX_INITHW(_name, _parent, _ops, _flags) \ ++ .hw.init = &(struct clk_init_data) { \ ++ .flags = _flags, \ ++ .name = #_name, \ ++ .parent_data = (const struct clk_parent_data[]) \ ++ { _parent }, \ ++ .num_parents = 1, \ ++ .ops = &_ops, \ + } + -+#define SPACEMIT_CCU_FACTOR(_struct, _name, _parent, _div, _mul) \ -+ struct ccu_mix _struct = { \ -+ .factor = CCU_FACTOR_INIT(_div, _mul), \ -+ .common = { \ -+ .name = _name, \ -+ .num_parents = 1, \ -+ .hw.init = CLK_HW_INIT(_name, \ -+ _parent, &ccu_mix_ops, 0), \ -+ } \ -+ } ++#define CCU_MIX_INITHW_PARENTS(_name, _parents, _ops, _flags) \ ++ .hw.init = CLK_HW_INIT_PARENTS_DATA(#_name, _parents, &_ops, _flags) + -+#define SPACEMIT_CCU_MUX(_struct, _name, _parents, _base_type, \ -+ _reg, _shift, _width, _flags) \ -+ struct ccu_mix _struct = { \ -+ .mux = CCU_MUX_INIT(_shift, _width, NULL, 0), \ -+ .common = { \ -+ .reg_ctrl = _reg, \ -+ .base_type = _base_type, \ -+ .name = _name, \ -+ .parent_names = _parents, \ -+ .num_parents = ARRAY_SIZE(_parents), \ -+ .hw.init = CLK_HW_INIT_PARENTS(_name, \ -+ _parents, &ccu_mix_ops, \ -+ (_flags) | CLK_GET_RATE_NOCACHE), \ -+ } \ -+ } -+ -+#define SPACEMIT_CCU_DIV(_struct, _name, _parent, _base_type, \ -+ _reg, _shift, _width, _flags) \ -+ struct ccu_mix _struct = { \ -+ .div = CCU_DIV_INIT(_shift, _width, NULL, 0), \ -+ .common = { \ -+ .reg_ctrl = _reg, \ -+ .base_type = _base_type, \ -+ .name = _name, \ -+ .num_parents = 1, \ -+ .hw.init = CLK_HW_INIT(_name, _parent, \ -+ &ccu_mix_ops, \ -+ (_flags) | CLK_GET_RATE_NOCACHE), \ -+ } \ -+ } -+ -+#define SPACEMIT_CCU_GATE_FACTOR(_struct, _name, _parent, _base_type, \ -+ _reg, _gate_mask, _val_enable, _val_disable, \ -+ _div, _mul, _flags) \ -+ struct ccu_mix _struct = { \ -+ .gate = CCU_GATE_INIT(_gate_mask, _val_enable, \ -+ _val_disable, 0), \ -+ .factor = CCU_FACTOR_INIT(_div, _mul), \ -+ .common = { \ -+ .reg_ctrl = _reg, \ -+ .base_type = _base_type, \ -+ .name = _name, \ -+ .num_parents = 1, \ -+ .hw.init = CLK_HW_INIT(_name, _parent, \ -+ &ccu_mix_ops, _flags), \ -+ } \ -+ } -+ -+#define SPACEMIT_CCU_MUX_GATE(_struct, _name, _parents, _base_type, \ -+ _reg, _shift, _width, _gate_mask, _val_enable, \ -+ _val_disable, _flags) \ -+ struct ccu_mix _struct = { \ -+ .gate = CCU_GATE_INIT(_gate_mask, _val_enable, \ -+ _val_disable, 0), \ -+ .mux = CCU_MUX_INIT(_shift, _width, NULL, 0), \ -+ .common = { \ -+ .reg_ctrl = _reg, \ -+ .base_type = _base_type, \ -+ .name = _name, \ -+ .parent_names = _parents, \ -+ .num_parents = ARRAY_SIZE(_parents), \ -+ .hw.init = CLK_HW_INIT_PARENTS(_name, \ -+ _parents, &ccu_mix_ops, \ -+ (_flags) | CLK_GET_RATE_NOCACHE), \ -+ } \ -+ } -+ -+#define SPACEMIT_CCU_DIV_GATE(_struct, _name, _parent, _base_type, \ -+ _reg, _shift, _width, _gate_mask, _val_enable, \ -+ _val_disable, _flags) \ -+ struct ccu_mix _struct = { \ -+ .gate = CCU_GATE_INIT(_gate_mask, _val_enable, \ -+ _val_disable, 0), \ -+ .div = CCU_DIV_INIT(_shift, _width, NULL, 0), \ -+ .common = { \ -+ .reg_ctrl = _reg, \ -+ .base_type = _base_type, \ -+ .name = _name, \ -+ .num_parents = 1, \ -+ .hw.init = CLK_HW_INIT(_name, _parent, \ -+ &ccu_mix_ops, \ -+ (_flags) | CLK_GET_RATE_NOCACHE), \ -+ } \ -+ } ++#define CCU_GATE_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _flags) \ ++static struct ccu_mix _name = { \ ++ .gate = CCU_GATE_INIT(_mask_gate), \ ++ .common = { \ ++ .reg_ctrl = _reg_ctrl, \ ++ CCU_MIX_INITHW(_name, _parent, spacemit_ccu_gate_ops, _flags), \ ++ } \ ++} + -+#define SPACEMIT_CCU_DIV_MUX_GATE(_struct, _name, _parents, _base_type, \ -+ _reg_ctrl, _mshift, _mwidth, _muxshift, \ -+ _muxwidth, _gate_mask, _val_enable, \ -+ _val_disable, _flags) \ -+ struct ccu_mix _struct = { \ -+ .gate = CCU_GATE_INIT(_gate_mask, _val_enable, \ -+ _val_disable, 0), \ -+ .div = CCU_DIV_INIT(_mshift, _mwidth, NULL, 0), \ -+ .mux = CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0), \ -+ .common = { \ -+ .reg_ctrl = _reg_ctrl, \ -+ .base_type = _base_type, \ -+ .name = _name, \ -+ .parent_names = _parents, \ -+ .num_parents = ARRAY_SIZE(_parents), \ -+ .hw.init = CLK_HW_INIT_PARENTS(_name, \ -+ _parents, &ccu_mix_ops, \ -+ (_flags) | CLK_GET_RATE_NOCACHE), \ -+ }, \ -+ } ++#define CCU_FACTOR_DEFINE(_name, _parent, _div, _mul) \ ++static struct ccu_mix _name = { \ ++ .factor = CCU_FACTOR_INIT(_div, _mul), \ ++ .common = { \ ++ CCU_MIX_INITHW(_name, _parent, spacemit_ccu_factor_ops, 0), \ ++ } \ ++} + -+#define SPACEMIT_CCU_DIV2_FC_MUX_GATE(_struct, _name, _parents, \ -+ _base_type, _reg_ctrl, _reg_sel, _mshift, \ -+ _mwidth, _fc, _muxshift, _muxwidth, _gate_mask, \ -+ _val_enable, _val_disable, _flags) \ -+ struct ccu_mix _struct = { \ -+ .gate = CCU_GATE_INIT(_gate_mask, _val_enable, \ -+ _val_disable, 0), \ -+ .div = CCU_DIV_INIT(_mshift, _mwidth, NULL, 0), \ -+ .mux = CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0), \ -+ .common = { \ -+ .reg_type = CLK_DIV_TYPE_2REG_FC_V4, \ -+ .reg_ctrl = _reg_ctrl, \ -+ .reg_sel = _reg_sel, \ -+ .fc = _fc, \ -+ .base_type = _base_type, \ -+ .name = _name, \ -+ .parent_names = _parents, \ -+ .num_parents = ARRAY_SIZE(_parents), \ -+ .hw.init = CLK_HW_INIT_PARENTS(_name, \ -+ _parents, &ccu_mix_ops, \ -+ (_flags) | CLK_GET_RATE_NOCACHE), \ -+ }, \ -+ } ++#define CCU_MUX_DEFINE(_name, _parents, _reg_ctrl, _shift, _width, _flags) \ ++static struct ccu_mix _name = { \ ++ .mux = CCU_MUX_INIT(_shift, _width), \ ++ .common = { \ ++ .reg_ctrl = _reg_ctrl, \ ++ CCU_MIX_INITHW_PARENTS(_name, _parents, spacemit_ccu_mux_ops, \ ++ _flags), \ ++ } \ ++} + -+#define SPACEMIT_CCU_DIV_FC_MUX_GATE(_struct, _name, _parents, \ -+ _base_type, _reg_ctrl, _mshift, _mwidth, _fc, \ -+ _muxshift, _muxwidth, _gate_mask, _val_enable, \ -+ _val_disable, _flags) \ -+ struct ccu_mix _struct = { \ -+ .gate = CCU_GATE_INIT(_gate_mask, _val_enable, \ -+ _val_disable, 0), \ -+ .div = CCU_DIV_INIT(_mshift, _mwidth, NULL, 0), \ -+ .mux = CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0), \ -+ .common = { \ -+ .reg_type = CLK_DIV_TYPE_1REG_FC_V2, \ -+ .reg_ctrl = _reg_ctrl, \ -+ .fc = _fc, \ -+ .base_type = _base_type, \ -+ .name = _name, \ -+ .parent_names = _parents, \ -+ .num_parents = ARRAY_SIZE(_parents), \ -+ .hw.init = CLK_HW_INIT_PARENTS(_name, \ -+ _parents, &ccu_mix_ops, \ -+ (_flags) | CLK_GET_RATE_NOCACHE), \ -+ }, \ -+ } ++#define CCU_DIV_DEFINE(_name, _parent, _reg_ctrl, _shift, _width, _flags) \ ++static struct ccu_mix _name = { \ ++ .div = CCU_DIV_INIT(_shift, _width), \ ++ .common = { \ ++ .reg_ctrl = _reg_ctrl, \ ++ CCU_MIX_INITHW(_name, _parent, spacemit_ccu_div_ops, _flags) \ ++ } \ ++} + -+#define SPACEMIT_CCU_DIV_MFC_MUX_GATE(_struct, _name, _parents, _base_type, \ -+ _reg_ctrl, _mshift, _mwidth, _fc, _muxshift, \ -+ _muxwidth, _gate_mask, _val_enable, \ -+ _val_disable, _flags) \ -+ struct ccu_mix _struct = { \ -+ .gate = CCU_GATE_INIT(_gate_mask, \ -+ _val_enable, _val_disable, 0), \ -+ .div = CCU_DIV_INIT(_mshift, _mwidth, NULL, 0), \ -+ .mux = CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0), \ -+ .common = { \ -+ .reg_type = CLK_DIV_TYPE_1REG_FC_MUX_V6, \ -+ .reg_ctrl = _reg_ctrl, \ -+ .fc = _fc, \ -+ .base_type = _base_type, \ -+ .name = _name, \ -+ .parent_names = _parents, \ -+ .num_parents = ARRAY_SIZE(_parents), \ -+ .hw.init = CLK_HW_INIT_PARENTS(_name, \ -+ _parents, &ccu_mix_ops, \ -+ (_flags) | CLK_GET_RATE_NOCACHE), \ -+ }, \ -+ } ++#define CCU_GATE_FLAGS_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _flags) \ ++static struct ccu_mix _name = { \ ++ .gate = CCU_GATE_FLAGS_INIT(_mask_gate, _flags), \ ++ .common = { \ ++ .reg_ctrl = _reg_ctrl, \ ++ CCU_MIX_INITHW(_name, _parent, spacemit_ccu_gate_ops, _flags), \ ++ } \ ++} + -+#define SPACEMIT_CCU_DIV_FC_WITH_GATE(_struct, _name, _parent, _base_type, \ -+ _reg_ctrl, _mshift, _mwidth, _fc, _gate_mask, \ -+ _val_enable, _val_disable, _flags) \ -+ struct ccu_mix _struct = { \ -+ .gate = CCU_GATE_INIT(_gate_mask, _val_enable, \ -+ _val_disable, 0), \ -+ .div = CCU_DIV_INIT(_mshift, _mwidth, NULL, 0), \ -+ .common = { \ -+ .reg_type = CLK_DIV_TYPE_1REG_FC_V2, \ -+ .reg_ctrl = _reg_ctrl, \ -+ .fc = _fc, \ -+ .base_type = _base_type, \ -+ .name = _name, \ -+ .num_parents = 1, \ -+ .hw.init = CLK_HW_INIT(_name, \ -+ _parent, &ccu_mix_ops, \ -+ (_flags) | CLK_GET_RATE_NOCACHE), \ -+ }, \ -+ } ++#define CCU_FACTOR_GATE_FLAGS_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _div, \ ++ _mul, _flags) \ ++static struct ccu_mix _name = { \ ++ .gate = CCU_GATE_INIT(_mask_gate), \ ++ .factor = CCU_FACTOR_INIT(_div, _mul), \ ++ .common = { \ ++ .reg_ctrl = _reg_ctrl, \ ++ CCU_MIX_INITHW(_name, _parent, spacemit_ccu_factor_gate_ops, _flags) \ ++ } \ ++} + -+#define SPACEMIT_CCU_DIV_MUX(_struct, _name, _parents, _base_type, \ -+ _reg_ctrl, _mshift, _mwidth, _muxshift, _muxwidth, _flags) \ -+ struct ccu_mix _struct = { \ -+ .div = CCU_DIV_INIT(_mshift, _mwidth, NULL, 0), \ -+ .mux = CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0), \ -+ .common = { \ -+ .reg_ctrl = _reg_ctrl, \ -+ .base_type = _base_type, \ -+ .name = _name, \ -+ .parent_names = _parents, \ -+ .num_parents = ARRAY_SIZE(_parents), \ -+ .hw.init = CLK_HW_INIT_PARENTS(_name, \ -+ _parents, &ccu_mix_ops, \ -+ (_flags) | CLK_GET_RATE_NOCACHE), \ -+ }, \ -+ } ++#define CCU_FACTOR_GATE_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _div, \ ++ _mul) \ ++ CCU_FACTOR_GATE_FLAGS_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _div, \ ++ _mul, 0) ++ ++#define CCU_MUX_GATE_DEFINE(_name, _parents, _reg_ctrl, _shift, _width, \ ++ _mask_gate, _flags) \ ++static struct ccu_mix _name = { \ ++ .gate = CCU_GATE_INIT(_mask_gate), \ ++ .mux = CCU_MUX_INIT(_shift, _width), \ ++ .common = { \ ++ .reg_ctrl = _reg_ctrl, \ ++ CCU_MIX_INITHW_PARENTS(_name, _parents, \ ++ spacemit_ccu_mux_gate_ops, _flags), \ ++ } \ ++} + -+#define SPACEMIT_CCU_DIV_FC_MUX(_struct, _name, _parents, _base_type, \ -+ _reg_ctrl, _mshift, _mwidth, _fc, _muxshift, \ -+ _muxwidth, _flags) \ -+ struct ccu_mix _struct = { \ -+ .div = CCU_DIV_INIT(_mshift, _mwidth, NULL, 0), \ -+ .mux = CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0), \ -+ .common = { \ -+ .reg_type = CLK_DIV_TYPE_1REG_FC_V2, \ -+ .reg_ctrl = _reg_ctrl, \ -+ .fc = _fc, \ -+ .base_type = _base_type, \ -+ .name = _name, \ -+ .parent_names = _parents, \ -+ .num_parents = ARRAY_SIZE(_parents), \ -+ .hw.init = CLK_HW_INIT_PARENTS(_name, \ -+ _parents, &ccu_mix_ops, \ -+ (_flags) | CLK_GET_RATE_NOCACHE), \ -+ }, \ -+ } ++#define CCU_DIV_GATE_DEFINE(_name, _parent, _reg_ctrl, _shift, _width, \ ++ _mask_gate, _flags) \ ++static struct ccu_mix _name = { \ ++ .gate = CCU_GATE_INIT(_mask_gate), \ ++ .div = CCU_DIV_INIT(_shift, _width), \ ++ .common = { \ ++ .reg_ctrl = _reg_ctrl, \ ++ CCU_MIX_INITHW(_name, _parent, spacemit_ccu_div_gate_ops, \ ++ _flags), \ ++ } \ ++} + -+#define SPACEMIT_CCU_MUX_FC(_struct, _name, _parents, _base_type, \ -+ _reg_ctrl, _fc, _muxshift, _muxwidth, _flags) \ -+ struct ccu_mix _struct = { \ -+ .mux = CCU_MUX_INIT(_muxshift, _muxwidth, NULL, 0), \ -+ .common = { \ -+ .reg_type = CLK_DIV_TYPE_1REG_FC_V2, \ -+ .reg_ctrl = _reg_ctrl, \ -+ .fc = _fc, \ -+ .base_type = _base_type, \ -+ .name = _name, \ -+ .parent_names = _parents, \ -+ .num_parents = ARRAY_SIZE(_parents), \ -+ .hw.init = CLK_HW_INIT_PARENTS(_name, \ -+ _parents, &ccu_mix_ops, \ -+ (_flags) | CLK_GET_RATE_NOCACHE), \ -+ }, \ -+ } ++#define CCU_MUX_DIV_GATE_DEFINE(_name, _parents, _reg_ctrl, _mshift, _mwidth, \ ++ _muxshift, _muxwidth, _mask_gate, _flags) \ ++static struct ccu_mix _name = { \ ++ .gate = CCU_GATE_INIT(_mask_gate), \ ++ .div = CCU_DIV_INIT(_mshift, _mwidth), \ ++ .mux = CCU_MUX_INIT(_muxshift, _muxwidth), \ ++ .common = { \ ++ .reg_ctrl = _reg_ctrl, \ ++ CCU_MIX_INITHW_PARENTS(_name, _parents, \ ++ spacemit_ccu_mux_div_gate_ops, _flags), \ ++ }, \ ++} ++ ++#define CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(_name, _parents, _reg_ctrl, _reg_fc, \ ++ _mshift, _mwidth, _mask_fc, _muxshift, \ ++ _muxwidth, _mask_gate, _flags) \ ++static struct ccu_mix _name = { \ ++ .gate = CCU_GATE_INIT(_mask_gate), \ ++ .div = CCU_DIV_INIT(_mshift, _mwidth), \ ++ .mux = CCU_MUX_INIT(_muxshift, _muxwidth), \ ++ .common = { \ ++ .reg_ctrl = _reg_ctrl, \ ++ .reg_fc = _reg_fc, \ ++ .mask_fc = _mask_fc, \ ++ CCU_MIX_INITHW_PARENTS(_name, _parents, \ ++ spacemit_ccu_mux_div_gate_ops, _flags), \ ++ }, \ ++} ++ ++#define CCU_MUX_DIV_GATE_FC_DEFINE(_name, _parents, _reg_ctrl, _mshift, _mwidth,\ ++ _mask_fc, _muxshift, _muxwidth, _mask_gate, \ ++ _flags) \ ++CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(_name, _parents, _reg_ctrl, _reg_ctrl, _mshift,\ ++ _mwidth, _mask_fc, _muxshift, _muxwidth, \ ++ _mask_gate, _flags) ++ ++#define CCU_MUX_DIV_FC_DEFINE(_name, _parents, _reg_ctrl, _mshift, _mwidth, \ ++ _mask_fc, _muxshift, _muxwidth, _flags) \ ++static struct ccu_mix _name = { \ ++ .div = CCU_DIV_INIT(_mshift, _mwidth), \ ++ .mux = CCU_MUX_INIT(_muxshift, _muxwidth), \ ++ .common = { \ ++ .reg_ctrl = _reg_ctrl, \ ++ .reg_fc = _reg_ctrl, \ ++ .mask_fc = _mask_fc, \ ++ CCU_MIX_INITHW_PARENTS(_name, _parents, \ ++ spacemit_ccu_mux_div_ops, _flags), \ ++ }, \ ++} ++ ++#define CCU_MUX_FC_DEFINE(_name, _parents, _reg_ctrl, _mask_fc, _muxshift, \ ++ _muxwidth, _flags) \ ++static struct ccu_mix _name = { \ ++ .mux = CCU_MUX_INIT(_muxshift, _muxwidth), \ ++ .common = { \ ++ .reg_ctrl = _reg_ctrl, \ ++ .reg_fc = _reg_ctrl, \ ++ .mask_fc = _mask_fc, \ ++ CCU_MIX_INITHW_PARENTS(_name, _parents, spacemit_ccu_mux_ops, \ ++ _flags) \ ++ }, \ ++} ++ ++#define CCU_DIV_FC_DEFINE(_name, _parent, _reg_ctrl, _mask_fc, _mshift, \ ++ _mwidth, _flags) \ ++static struct ccu_mix _name = { \ ++ .div = CCU_DIV_INIT(_mshift, _mwidth), \ ++ .common = { \ ++ .reg_ctrl = _reg_ctrl, \ ++ .reg_fc = _reg_ctrl, \ ++ .mask_fc = _mask_fc, \ ++ CCU_MIX_INITHW(_name, _parent, spacemit_ccu_div_ops, _flags) \ ++ }, \ ++} + +static inline struct ccu_mix *hw_to_ccu_mix(struct clk_hw *hw) +{ @@ -57372,376 +58400,421 @@ index 000000000000..cd087972d62b + return container_of(common, struct ccu_mix, common); +} + -+extern const struct clk_ops ccu_mix_ops; -+ ++extern const struct clk_ops spacemit_ccu_gate_ops; ++extern const struct clk_ops spacemit_ccu_factor_ops; ++extern const struct clk_ops spacemit_ccu_mux_ops; ++extern const struct clk_ops spacemit_ccu_div_ops; ++extern const struct clk_ops spacemit_ccu_factor_gate_ops; ++extern const struct clk_ops spacemit_ccu_div_gate_ops; ++extern const struct clk_ops spacemit_ccu_mux_gate_ops; ++extern const struct clk_ops spacemit_ccu_mux_div_ops; ++extern const struct clk_ops spacemit_ccu_mux_div_gate_ops; +#endif /* _CCU_DIV_H_ */ diff --git a/drivers/clk/spacemit/ccu_pll.c b/drivers/clk/spacemit/ccu_pll.c new file mode 100644 -index 000000000000..9bc4d1de8b33 +index 000000000000..fd07b6759d58 --- /dev/null +++ b/drivers/clk/spacemit/ccu_pll.c -@@ -0,0 +1,286 @@ +@@ -0,0 +1,278 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* -+ * Spacemit clock type pll -+ * -+ * Copyright (c) 2023, spacemit Corporation. -+ * ++ * Copyright (c) 2024 SpacemiT Technology Co. Ltd ++ * Copyright (c) 2024-2025 Haylen Chu + */ + -+#include -+#include +#include -+#include -+#include ++#include ++#include + ++#include "ccu_common.h" +#include "ccu_pll.h" + -+#define PLL_MIN_FREQ 600000000 -+#define PLL_MAX_FREQ 3400000000 -+#define PLL_DELAYTIME 590 ++#define PLL_TIMEOUT_US 3000 ++#define PLL_DELAY_US 5 + -+#define pll_readl(reg) readl(reg) -+#define pll_readl_pll_swcr1(p) pll_readl(p.base + p.reg_ctrl) -+#define pll_readl_pll_swcr2(p) pll_readl(p.base + p.reg_sel) -+#define pll_readl_pll_swcr3(p) pll_readl(p.base + p.reg_xtc) ++#define PLL_SWCR3_EN ((u32)BIT(31)) ++#define PLL_SWCR3_MASK GENMASK(30, 0) + -+#define pll_writel(val, reg) writel(val, reg) -+#define pll_writel_pll_swcr1(val, p) pll_writel(val, p.base + p.reg_ctrl) -+#define pll_writel_pll_swcr2(val, p) pll_writel(val, p.base + p.reg_sel) -+#define pll_writel_pll_swcr3(val, p) pll_writel(val, p.base + p.reg_xtc) ++#define PLLA_SWCR2_EN ((u32)BIT(16)) ++#define PLLA_SWCR2_MASK GENMASK(15, 8) + -+/* unified pllx_swcr1 for pll1~3 */ -+union pllx_swcr1 { -+ struct { -+ unsigned int reg5:8; -+ unsigned int reg6:8; -+ unsigned int reg7:8; -+ unsigned int reg8:8; -+ } b; -+ unsigned int v; -+}; ++static const struct ccu_pll_rate_tbl *ccu_pll_lookup_best_rate(struct ccu_pll *pll, ++ unsigned long rate) ++{ ++ struct ccu_pll_config *config = &pll->config; ++ const struct ccu_pll_rate_tbl *best_entry; ++ unsigned long best_delta = ULONG_MAX; ++ int i; + -+/* unified pllx_swcr2 for pll1~3 */ -+union pllx_swcr2 { -+ struct { -+ unsigned int div1_en:1; -+ unsigned int div2_en:1; -+ unsigned int div3_en:1; -+ unsigned int div4_en:1; -+ unsigned int div5_en:1; -+ unsigned int div6_en:1; -+ unsigned int div7_en:1; -+ unsigned int div8_en:1; -+ unsigned int reserved1:4; -+ unsigned int atest_en:1; -+ unsigned int cktest_en:1; -+ unsigned int dtest_en:1; -+ unsigned int rdo:2; -+ unsigned int mon_cfg:4; -+ unsigned int reserved2:11; -+ } b; -+ unsigned int v; -+}; -+ -+union pllx_swcr3 { -+ struct { -+ unsigned int div_frc:24; -+ unsigned int div_int:7; -+ unsigned int pll_en:1; -+ } b; ++ for (i = 0; i < config->tbl_num; i++) { ++ const struct ccu_pll_rate_tbl *entry = &config->rate_tbl[i]; ++ unsigned long delta = abs_diff(entry->rate, rate); + -+ unsigned int v; -+}; ++ if (delta < best_delta) { ++ best_delta = delta; ++ best_entry = entry; ++ } ++ } + -+static int ccu_pll_is_enabled(struct clk_hw *hw) ++ return best_entry; ++} ++ ++static const struct ccu_pll_rate_tbl *ccu_pll_lookup_matched_entry(struct ccu_pll *pll) +{ -+ struct ccu_pll *p = hw_to_ccu_pll(hw); -+ union pllx_swcr3 swcr3; -+ unsigned int enabled; ++ struct ccu_pll_config *config = &pll->config; ++ u32 swcr1, swcr3; ++ int i; + -+ swcr3.v = pll_readl_pll_swcr3(p->common); -+ enabled = swcr3.b.pll_en; ++ swcr1 = ccu_read(&pll->common, swcr1); ++ swcr3 = ccu_read(&pll->common, swcr3); ++ swcr3 &= PLL_SWCR3_MASK; + -+ return enabled; ++ for (i = 0; i < config->tbl_num; i++) { ++ const struct ccu_pll_rate_tbl *entry = &config->rate_tbl[i]; ++ ++ if (swcr1 == entry->swcr1 && swcr3 == entry->swcr3) ++ return entry; ++ } ++ ++ return NULL; +} + -+static unsigned long __get_vco_freq(struct clk_hw *hw) ++static void ccu_pll_update_param(struct ccu_pll *pll, const struct ccu_pll_rate_tbl *entry) +{ -+ unsigned int reg5, reg6, reg7, reg8, size, i; -+ unsigned int div_int, div_frc; -+ struct ccu_pll_rate_tbl *freq_pll_regs_table, *pll_regs; -+ struct ccu_pll *p = hw_to_ccu_pll(hw); -+ union pllx_swcr1 swcr1; -+ union pllx_swcr3 swcr3; ++ struct ccu_common *common = &pll->common; + -+ swcr1.v = pll_readl_pll_swcr1(p->common); -+ swcr3.v = pll_readl_pll_swcr3(p->common); ++ regmap_write(common->regmap, common->reg_swcr1, entry->swcr1); ++ ccu_update(common, swcr3, PLL_SWCR3_MASK, entry->swcr3); ++} + -+ reg5 = swcr1.b.reg5; -+ reg6 = swcr1.b.reg6; -+ reg7 = swcr1.b.reg7; -+ reg8 = swcr1.b.reg8; ++static int ccu_pll_is_enabled(struct clk_hw *hw) ++{ ++ struct ccu_common *common = hw_to_ccu_common(hw); + -+ div_int = swcr3.b.div_int; -+ div_frc = swcr3.b.div_frc; ++ return ccu_read(common, swcr3) & PLL_SWCR3_EN; ++} + -+ freq_pll_regs_table = p->pll.rate_tbl; -+ size = p->pll.tbl_size; ++static int ccu_pll_enable(struct clk_hw *hw) ++{ ++ struct ccu_pll *pll = hw_to_ccu_pll(hw); ++ struct ccu_common *common = &pll->common; ++ unsigned int tmp; + -+ for (i = 0; i < size; i++) { -+ pll_regs = &freq_pll_regs_table[i]; -+ if (pll_regs->reg5 == reg5 && pll_regs->reg6 == reg6 && -+ pll_regs->reg7 == reg7 && pll_regs->reg8 == reg8 && -+ pll_regs->div_int == div_int && -+ pll_regs->div_frac == div_frc) -+ return pll_regs->rate; -+ } ++ ccu_update(common, swcr3, PLL_SWCR3_EN, PLL_SWCR3_EN); + -+ pr_err("Unknown rate for clock %s\n", __clk_get_name(hw->clk)); ++ /* check lock status */ ++ return regmap_read_poll_timeout_atomic(common->lock_regmap, ++ pll->config.reg_lock, ++ tmp, ++ tmp & pll->config.mask_lock, ++ PLL_DELAY_US, PLL_TIMEOUT_US); ++} ++ ++static void ccu_pll_disable(struct clk_hw *hw) ++{ ++ struct ccu_common *common = hw_to_ccu_common(hw); ++ ++ ccu_update(common, swcr3, PLL_SWCR3_EN, 0); ++} ++ ++/* ++ * PLLs must be gated before changing rate, which is ensured by ++ * flag CLK_SET_RATE_GATE. ++ */ ++static int ccu_pll_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct ccu_pll *pll = hw_to_ccu_pll(hw); ++ const struct ccu_pll_rate_tbl *entry; ++ ++ entry = ccu_pll_lookup_best_rate(pll, rate); ++ ccu_pll_update_param(pll, entry); + + return 0; +} + -+static int ccu_pll_enable(struct clk_hw *hw) ++static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) +{ -+ unsigned int delaytime = PLL_DELAYTIME; -+ unsigned long flags; -+ struct ccu_pll *p = hw_to_ccu_pll(hw); -+ union pllx_swcr3 swcr3; ++ struct ccu_pll *pll = hw_to_ccu_pll(hw); ++ const struct ccu_pll_rate_tbl *entry; + -+ if (ccu_pll_is_enabled(hw)) -+ return 0; ++ entry = ccu_pll_lookup_matched_entry(pll); + -+ spin_lock_irqsave(p->common.lock, flags); -+ swcr3.v = pll_readl_pll_swcr3(p->common); -+ swcr3.b.pll_en = 1; -+ pll_writel_pll_swcr3(swcr3.v, p->common); -+ spin_unlock_irqrestore(p->common.lock, flags); ++ WARN_ON_ONCE(!entry); + -+ /* check lock status */ -+ udelay(50); ++ return entry ? entry->rate : -EINVAL; ++} + -+ while ((!(readl(p->pll.lock_base + p->pll.reg_lock) -+ & p->pll.lock_enable_bit)) && delaytime) { -+ udelay(5); -+ delaytime--; -+ } ++static long ccu_pll_round_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long *prate) ++{ ++ struct ccu_pll *pll = hw_to_ccu_pll(hw); + -+ if (unlikely(!delaytime)) { -+ pr_err("%s enabling didn't get stable within 3000us!!!\n", -+ __clk_get_name(hw->clk)); -+ return -EINVAL; -+ } ++ return ccu_pll_lookup_best_rate(pll, rate)->rate; ++} ++ ++static int ccu_pll_init(struct clk_hw *hw) ++{ ++ struct ccu_pll *pll = hw_to_ccu_pll(hw); ++ ++ if (ccu_pll_lookup_matched_entry(pll)) ++ return 0; ++ ++ ccu_pll_disable(hw); ++ ccu_pll_update_param(pll, &pll->config.rate_tbl[0]); + + return 0; +} + -+static void ccu_pll_disable(struct clk_hw *hw) ++static const struct ccu_pll_rate_tbl *ccu_plla_lookup_matched_entry(struct ccu_pll *pll) +{ -+ unsigned long flags; -+ struct ccu_pll *p = hw_to_ccu_pll(hw); -+ union pllx_swcr3 swcr3; ++ struct ccu_pll_config *config = &pll->config; ++ u32 swcr1, swcr2, swcr3; ++ int i; ++ ++ swcr1 = ccu_read(&pll->common, swcr1); ++ swcr2 = ccu_read(&pll->common, swcr2); ++ swcr3 = ccu_read(&pll->common, swcr3); ++ swcr2 &= PLLA_SWCR2_MASK; ++ ++ for (i = 0; i < config->tbl_num; i++) { ++ const struct ccu_pll_rate_tbl *entry = &config->rate_tbl[i]; + -+ spin_lock_irqsave(p->common.lock, flags); -+ swcr3.v = pll_readl_pll_swcr3(p->common); -+ swcr3.b.pll_en = 0; -+ pll_writel_pll_swcr3(swcr3.v, p->common); -+ spin_unlock_irqrestore(p->common.lock, flags); ++ if (swcr1 == entry->swcr1 && swcr2 == entry->swcr2 && swcr3 == entry->swcr3) ++ return entry; ++ } ++ ++ return NULL; +} + -+/* -+ * pll rate change requires sequence: -+ * clock off -> change rate setting -> clock on -+ * This function doesn't really change rate, but cache the config -+ */ -+static int ccu_pll_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) ++static void ccu_plla_update_param(struct ccu_pll *pll, const struct ccu_pll_rate_tbl *entry) +{ -+ unsigned int i, reg5 = 0, reg6 = 0, reg7 = 0, reg8 = 0; -+ unsigned int div_int, div_frc; -+ unsigned long flags; -+ unsigned long new_rate = rate, old_rate; -+ struct ccu_pll *p = hw_to_ccu_pll(hw); -+ struct ccu_pll_config *params = &p->pll; -+ union pllx_swcr1 swcr1; -+ union pllx_swcr3 swcr3; -+ bool found = false; -+ bool pll_enabled = false; ++ struct ccu_common *common = &pll->common; + -+ if (ccu_pll_is_enabled(hw)) { -+ pll_enabled = true; -+ ccu_pll_disable(hw); -+ } ++ regmap_write(common->regmap, common->reg_swcr1, entry->swcr1); ++ regmap_write(common->regmap, common->reg_swcr3, entry->swcr3); ++ ccu_update(common, swcr2, PLLA_SWCR2_MASK, entry->swcr2); ++} + -+ old_rate = __get_vco_freq(hw); ++static int ccu_plla_is_enabled(struct clk_hw *hw) ++{ ++ struct ccu_common *common = hw_to_ccu_common(hw); + -+ /* setp 1: calculate fbd frcd kvco and band */ -+ if (params->rate_tbl) { -+ for (i = 0; i < params->tbl_size; i++) { -+ if (rate == params->rate_tbl[i].rate) { -+ found = true; ++ return ccu_read(common, swcr2) & PLLA_SWCR2_EN; ++} + -+ reg5 = params->rate_tbl[i].reg5; -+ reg6 = params->rate_tbl[i].reg6; -+ reg7 = params->rate_tbl[i].reg7; -+ reg8 = params->rate_tbl[i].reg8; -+ div_int = params->rate_tbl[i].div_int; -+ div_frc = params->rate_tbl[i].div_frac; -+ break; -+ } -+ } ++static int ccu_plla_enable(struct clk_hw *hw) ++{ ++ struct ccu_pll *pll = hw_to_ccu_pll(hw); ++ struct ccu_common *common = &pll->common; ++#ifndef CONFIG_SOC_SPACEMIT_K3_FPGA ++ unsigned int tmp; ++#endif + -+ WARN_ON_ONCE(!found); -+ } else { -+ pr_err("don't find freq table for pll\n"); -+ if (pll_enabled) -+ ccu_pll_enable(hw); -+ return -EINVAL; -+ } ++ ccu_update(common, swcr2, PLLA_SWCR2_EN, PLLA_SWCR2_EN); + -+ spin_lock_irqsave(p->common.lock, flags); ++#ifdef CONFIG_SOC_SPACEMIT_K3_FPGA ++ return 0; ++#else ++ /* check lock status */ ++ return regmap_read_poll_timeout_atomic(common->lock_regmap, ++ pll->config.reg_lock, ++ tmp, ++ tmp & pll->config.mask_lock, ++ PLL_DELAY_US, PLL_TIMEOUT_US); ++#endif ++} + -+ /* setp 2: set pll kvco/band and fbd/frcd setting */ -+ swcr1.v = pll_readl_pll_swcr1(p->common); -+ swcr1.b.reg5 = reg5; -+ swcr1.b.reg6 = reg6; -+ swcr1.b.reg7 = reg7; -+ swcr1.b.reg8 = reg8; -+ pll_writel_pll_swcr1(swcr1.v, p->common); ++static void ccu_plla_disable(struct clk_hw *hw) ++{ ++ struct ccu_common *common = hw_to_ccu_common(hw); + -+ swcr3.v = pll_readl_pll_swcr3(p->common); -+ swcr3.b.div_int = div_int; -+ swcr3.b.div_frc = div_frc; -+ pll_writel_pll_swcr3(swcr3.v, p->common); ++ ccu_update(common, swcr2, PLLA_SWCR2_EN, 0); ++} + -+ spin_unlock_irqrestore(p->common.lock, flags); ++/* ++ * PLLAs must be gated before changing rate, which is ensured by ++ * flag CLK_SET_RATE_GATE. ++ */ ++static int ccu_plla_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct ccu_pll *pll = hw_to_ccu_pll(hw); ++ const struct ccu_pll_rate_tbl *entry; + -+ if (pll_enabled) -+ ccu_pll_enable(hw); ++ entry = ccu_pll_lookup_best_rate(pll, rate); ++ ccu_plla_update_param(pll, entry); + -+ pr_debug("%s %s rate %lu->%lu!\n", __func__, -+ __clk_get_name(hw->clk), old_rate, new_rate); + return 0; +} + -+static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) ++static unsigned long ccu_plla_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) +{ -+ return __get_vco_freq(hw); ++ struct ccu_pll *pll = hw_to_ccu_pll(hw); ++ const struct ccu_pll_rate_tbl *entry; ++ ++ entry = ccu_plla_lookup_matched_entry(pll); ++ ++ WARN_ON_ONCE(!entry); ++ ++ return entry ? entry->rate : -EINVAL; +} + -+static long ccu_pll_round_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long *prate) ++static int ccu_plla_init(struct clk_hw *hw) +{ -+ struct ccu_pll *p = hw_to_ccu_pll(hw); -+ unsigned long max_rate = 0; -+ unsigned int i; -+ struct ccu_pll_config *params = &p->pll; ++ struct ccu_pll *pll = hw_to_ccu_pll(hw); + -+ if (rate > PLL_MAX_FREQ || rate < PLL_MIN_FREQ) { -+ pr_err("%lu rate out of range!\n", rate); -+ return -EINVAL; -+ } ++ if (ccu_plla_lookup_matched_entry(pll)) ++ return 0; + -+ if (params->rate_tbl) { -+ for (i = 0; i < params->tbl_size; i++) { -+ if (params->rate_tbl[i].rate <= rate) { -+ if (max_rate < params->rate_tbl[i].rate) -+ max_rate = params->rate_tbl[i].rate; -+ } -+ } -+ } else { -+ pr_err("don't find freq table for pll\n"); -+ } ++ ccu_plla_disable(hw); ++ ccu_plla_update_param(pll, &pll->config.rate_tbl[0]); + -+ return max_rate; ++ return 0; +} + -+const struct clk_ops ccu_pll_ops = { -+ .enable = ccu_pll_enable, -+ .disable = ccu_pll_disable, -+ .set_rate = ccu_pll_set_rate, -+ .recalc_rate = ccu_pll_recalc_rate, -+ .round_rate = ccu_pll_round_rate, -+ .is_enabled = ccu_pll_is_enabled, ++const struct clk_ops spacemit_ccu_pll_ops = { ++ .init = ccu_pll_init, ++ .enable = ccu_pll_enable, ++ .disable = ccu_pll_disable, ++ .set_rate = ccu_pll_set_rate, ++ .recalc_rate = ccu_pll_recalc_rate, ++ .round_rate = ccu_pll_round_rate, ++ .is_enabled = ccu_pll_is_enabled, +}; + ++const struct clk_ops spacemit_ccu_plla_ops = { ++ .init = ccu_plla_init, ++ .enable = ccu_plla_enable, ++ .disable = ccu_plla_disable, ++ .set_rate = ccu_plla_set_rate, ++ .recalc_rate = ccu_plla_recalc_rate, ++ .round_rate = ccu_pll_round_rate, ++ .is_enabled = ccu_plla_is_enabled, ++}; diff --git a/drivers/clk/spacemit/ccu_pll.h b/drivers/clk/spacemit/ccu_pll.h new file mode 100644 -index 000000000000..4b3796787d22 +index 000000000000..8727379f6ce6 --- /dev/null +++ b/drivers/clk/spacemit/ccu_pll.h -@@ -0,0 +1,79 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* Copyright (c) 2023, spacemit Corporation. */ +@@ -0,0 +1,126 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (c) 2024 SpacemiT Technology Co. Ltd ++ * Copyright (c) 2024-2025 Haylen Chu ++ */ + +#ifndef _CCU_PLL_H_ +#define _CCU_PLL_H_ + -+#include +#include -+#include "ccu-spacemit-k1.h" + ++#include "ccu_common.h" ++ ++/** ++ * struct ccu_pll_rate_tbl - Structure mapping between PLL rate and register ++ * configuration. ++ * ++ * Usual PLL type ++ * @rate: PLL rate ++ * @swcr1: Register value of PLLX_SW1_CTRL (PLLx_SWCR1). ++ * @swcr2: Not use. ++ * @swcr3: Register value of the PLLx_SW3_CTRL's lowest 31 bits of ++ * PLLx_SW3_CTRL (PLLx_SWCR3). This highest bit is for enabling ++ * the PLL and not contained in this field. ++ * ++ * Special PLL type A ++ * @rate: PLLA rate ++ * @swcr1: Register value of PLLAX_SW1_CTRL (PLLAx_SWCR1). ++ * @swcr2: Register value of PLLAX_SW2_CTRL[15:8] (PLLAx_SWCR2). PLLAX_SW2_CTRL[16] ++ * is for enabling the PLLA and not contained in this field. ++ * @swcr3: Register value of PLLAX_SW3_CTRL (PLLAx_SWCR3). ++ */ +struct ccu_pll_rate_tbl { -+ unsigned long long rate; -+ u32 reg5; -+ u32 reg6; -+ u32 reg7; -+ u32 reg8; -+ unsigned int div_int; -+ unsigned int div_frac; ++ unsigned long rate; ++ u32 swcr1; ++ u32 swcr2; ++ u32 swcr3; +}; + +struct ccu_pll_config { -+ struct ccu_pll_rate_tbl *rate_tbl; -+ u32 tbl_size; -+ void __iomem *lock_base; ++ const struct ccu_pll_rate_tbl *rate_tbl; ++ u32 tbl_num; + u32 reg_lock; -+ u32 lock_enable_bit; ++ u32 mask_lock; +}; + -+#define PLL_RATE(_rate, _reg5, _reg6, _reg7, _reg8, _div_int, _div_frac) \ -+ { \ -+ .rate = (_rate), \ -+ .reg5 = (_reg5), \ -+ .reg6 = (_reg6), \ -+ .reg7 = (_reg7), \ -+ .reg8 = (_reg8), \ -+ .div_int = (_div_int), \ -+ .div_frac = (_div_frac), \ ++#define CCU_PLL_RATE(_rate, _swcr1, _swcr3) \ ++ { \ ++ .rate = _rate, \ ++ .swcr1 = _swcr1, \ ++ .swcr3 = _swcr3, \ ++ } ++ ++#define CCU_PLLA_RATE(_rate, _swcr1, _swcr2, _swcr3) \ ++ { \ ++ .rate = _rate, \ ++ .swcr1 = _swcr1, \ ++ .swcr2 = _swcr2, \ ++ .swcr3 = _swcr3, \ + } + +struct ccu_pll { -+ struct ccu_pll_config pll; + struct ccu_common common; ++ struct ccu_pll_config config; +}; + -+#define _SPACEMIT_CCU_PLL_CONFIG(_table, _size, _reg_lock, _lock_enable_bit) \ -+ { \ -+ .rate_tbl = (struct ccu_pll_rate_tbl *)_table, \ -+ .tbl_size = _size, \ -+ .reg_lock = _reg_lock, \ -+ .lock_enable_bit = _lock_enable_bit, \ -+ } -+ -+#define SPACEMIT_CCU_PLL(_struct, _name, _table, _size, _base_type, \ -+ _reg_ctrl, _reg_sel, _reg_xtc, _reg_lock, \ -+ _lock_enable_bit, _is_pll, _flags) \ -+ struct ccu_pll _struct = { \ -+ .pll = _SPACEMIT_CCU_PLL_CONFIG(_table, _size, \ -+ _reg_lock, _lock_enable_bit), \ -+ .common = { \ -+ .reg_ctrl = _reg_ctrl, \ -+ .reg_sel = _reg_sel, \ -+ .reg_xtc = _reg_xtc, \ -+ .base_type = _base_type, \ -+ .is_pll = _is_pll, \ -+ .hw.init = CLK_HW_INIT_NO_PARENT(_name, \ -+ &ccu_pll_ops, _flags), \ -+ } \ ++#define CCU_PLL_CONFIG(_table, _reg_lock, _mask_lock) \ ++ { \ ++ .rate_tbl = _table, \ ++ .tbl_num = ARRAY_SIZE(_table), \ ++ .reg_lock = (_reg_lock), \ ++ .mask_lock = (_mask_lock), \ + } + ++#define CCU_PLL_HWINIT(_name, _flags) \ ++ (&(struct clk_init_data) { \ ++ .name = #_name, \ ++ .ops = &spacemit_ccu_pll_ops, \ ++ .parent_data = &(struct clk_parent_data) { .index = 0 }, \ ++ .num_parents = 1, \ ++ .flags = _flags, \ ++ }) ++ ++#define CCU_PLLA_HWINIT(_name, _flags) \ ++ (&(struct clk_init_data) { \ ++ .name = #_name, \ ++ .ops = &spacemit_ccu_plla_ops, \ ++ .parent_data = &(struct clk_parent_data) { .index = 0 }, \ ++ .num_parents = 1, \ ++ .flags = _flags, \ ++ }) ++ ++#define CCU_PLL_DEFINE(_name, _table, _reg_swcr1, _reg_swcr3, _reg_lock, \ ++ _mask_lock, _flags) \ ++static struct ccu_pll _name = { \ ++ .config = CCU_PLL_CONFIG(_table, _reg_lock, _mask_lock), \ ++ .common = { \ ++ .reg_swcr1 = _reg_swcr1, \ ++ .reg_swcr3 = _reg_swcr3, \ ++ .hw.init = CCU_PLL_HWINIT(_name, _flags) \ ++ } \ ++} ++ ++#define CCU_PLLA_DEFINE(_name, _table, _reg_swcr1, _reg_swcr2, _reg_swcr3, \ ++ _reg_lock, _mask_lock, _flags) \ ++static struct ccu_pll _name = { \ ++ .config = CCU_PLL_CONFIG(_table, _reg_lock, _mask_lock), \ ++ .common = { \ ++ .reg_swcr1 = _reg_swcr1, \ ++ .reg_swcr2 = _reg_swcr2, \ ++ .reg_swcr3 = _reg_swcr3, \ ++ .hw.init = CCU_PLLA_HWINIT(_name, _flags) \ ++ } \ ++} ++ +static inline struct ccu_pll *hw_to_ccu_pll(struct clk_hw *hw) +{ + struct ccu_common *common = hw_to_ccu_common(hw); @@ -57749,7 +58822,8 @@ index 000000000000..4b3796787d22 + return container_of(common, struct ccu_pll, common); +} + -+extern const struct clk_ops ccu_pll_ops; ++extern const struct clk_ops spacemit_ccu_pll_ops; ++extern const struct clk_ops spacemit_ccu_plla_ops; + +#endif diff --git a/drivers/clk/xuantie/Kconfig b/drivers/clk/xuantie/Kconfig @@ -509324,7 +510398,7 @@ index 0c363ca566ff..748eeb966c06 100644 iommu_set_fault_handler(domain, rproc_iommu_fault, rproc); diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig -index ccd59ddd7610..8eff8840516c 100644 +index ccd59ddd7610..6573a96e294d 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -253,6 +253,16 @@ config RESET_SUNXI @@ -509344,24 +510418,27 @@ index ccd59ddd7610..8eff8840516c 100644 config RESET_TI_SCI tristate "TI System Control Interface (TI-SCI) reset driver" depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n) -@@ -318,6 +328,12 @@ config RESET_ZYNQ +@@ -318,6 +328,7 @@ config RESET_ZYNQ help This enables the reset controller driver for Xilinx Zynq SoCs. -+config RESET_K1_SPACEMIT -+ tristate "Reset controller driver for Spacemit K1 SoC" -+ depends on SOC_SPACEMIT_K1 -+ help -+ Support for reset controllers on Spacemit K1 SoC. -+ ++source "drivers/reset/spacemit/Kconfig" source "drivers/reset/starfive/Kconfig" source "drivers/reset/sti/Kconfig" source "drivers/reset/hisilicon/Kconfig" diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile -index 8270da8a4baa..36dd9534c11c 100644 +index 8270da8a4baa..82ad5421def3 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile -@@ -33,6 +33,8 @@ obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o +@@ -1,6 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0 + obj-y += core.o + obj-y += hisilicon/ ++obj-y += spacemit/ + obj-y += starfive/ + obj-$(CONFIG_ARCH_STI) += sti/ + obj-$(CONFIG_ARCH_TEGRA) += tegra/ +@@ -33,6 +34,8 @@ obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o @@ -509370,11 +510447,6 @@ index 8270da8a4baa..36dd9534c11c 100644 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o obj-$(CONFIG_RESET_TI_TPS380X) += reset-tps380x.o -@@ -41,3 +43,4 @@ obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o - obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o - obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o - obj-$(CONFIG_ARCH_ZYNQMP) += reset-zynqmp.o -+obj-$(CONFIG_RESET_K1_SPACEMIT) += reset-spacemit-k1.o diff --git a/drivers/reset/reset-sophgo.c b/drivers/reset/reset-sophgo.c new file mode 100644 index 000000000000..3c46a43e24ba @@ -509544,681 +510616,6 @@ index 000000000000..3c46a43e24ba +MODULE_AUTHOR("Wei Huang"); +MODULE_DESCRIPTION("Bitmain SoC Reset Controoler Driver"); +MODULE_LICENSE("GPL"); -diff --git a/drivers/reset/reset-spacemit-k1.c b/drivers/reset/reset-spacemit-k1.c -new file mode 100644 -index 000000000000..ac25f3249d00 ---- /dev/null -+++ b/drivers/reset/reset-spacemit-k1.c -@@ -0,0 +1,669 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Spacemit k1x reset controller driver -+ * -+ * Copyright (c) 2023, spacemit Corporation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* APBC register offset */ -+#define APBC_UART1_CLK_RST 0x0 -+#define APBC_UART2_CLK_RST 0x4 -+#define APBC_GPIO_CLK_RST 0x8 -+#define APBC_PWM0_CLK_RST 0xc -+#define APBC_PWM1_CLK_RST 0x10 -+#define APBC_PWM2_CLK_RST 0x14 -+#define APBC_PWM3_CLK_RST 0x18 -+#define APBC_TWSI8_CLK_RST 0x20 -+#define APBC_UART3_CLK_RST 0x24 -+#define APBC_RTC_CLK_RST 0x28 -+#define APBC_TWSI0_CLK_RST 0x2c -+#define APBC_TWSI1_CLK_RST 0x30 -+#define APBC_TIMERS1_CLK_RST 0x34 -+#define APBC_TWSI2_CLK_RST 0x38 -+#define APBC_AIB_CLK_RST 0x3c -+#define APBC_TWSI4_CLK_RST 0x40 -+#define APBC_TIMERS2_CLK_RST 0x44 -+#define APBC_ONEWIRE_CLK_RST 0x48 -+#define APBC_TWSI5_CLK_RST 0x4c -+#define APBC_DRO_CLK_RST 0x58 -+#define APBC_IR_CLK_RST 0x5c -+#define APBC_TWSI6_CLK_RST 0x60 -+#define APBC_TWSI7_CLK_RST 0x68 -+#define APBC_TSEN_CLK_RST 0x6c -+#define APBC_UART4_CLK_RST 0x70 -+#define APBC_UART5_CLK_RST 0x74 -+#define APBC_UART6_CLK_RST 0x78 -+#define APBC_SSP3_CLK_RST 0x7c -+#define APBC_SSPA0_CLK_RST 0x80 -+#define APBC_SSPA1_CLK_RST 0x84 -+#define APBC_IPC_AP2AUD_CLK_RST 0x90 -+#define APBC_UART7_CLK_RST 0x94 -+#define APBC_UART8_CLK_RST 0x98 -+#define APBC_UART9_CLK_RST 0x9c -+#define APBC_CAN0_CLK_RST 0xa0 -+#define APBC_PWM4_CLK_RST 0xa8 -+#define APBC_PWM5_CLK_RST 0xac -+#define APBC_PWM6_CLK_RST 0xb0 -+#define APBC_PWM7_CLK_RST 0xb4 -+#define APBC_PWM8_CLK_RST 0xb8 -+#define APBC_PWM9_CLK_RST 0xbc -+#define APBC_PWM10_CLK_RST 0xc0 -+#define APBC_PWM11_CLK_RST 0xc4 -+#define APBC_PWM12_CLK_RST 0xc8 -+#define APBC_PWM13_CLK_RST 0xcc -+#define APBC_PWM14_CLK_RST 0xd0 -+#define APBC_PWM15_CLK_RST 0xd4 -+#define APBC_PWM16_CLK_RST 0xd8 -+#define APBC_PWM17_CLK_RST 0xdc -+#define APBC_PWM18_CLK_RST 0xe0 -+#define APBC_PWM19_CLK_RST 0xe4 -+ -+/* MPMU register offset */ -+#define MPMU_WDTPCR 0x200 -+ -+/* APMU register offset */ -+#define APMU_JPG_CLK_RES_CTRL 0x20 -+#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x24 -+#define APMU_ISP_CLK_RES_CTRL 0x38 -+#define APMU_LCD_CLK_RES_CTRL1 0x44 -+#define APMU_LCD_SPI_CLK_RES_CTRL 0x48 -+#define APMU_LCD_CLK_RES_CTRL2 0x4c -+#define APMU_CCIC_CLK_RES_CTRL 0x50 -+#define APMU_SDH0_CLK_RES_CTRL 0x54 -+#define APMU_SDH1_CLK_RES_CTRL 0x58 -+#define APMU_USB_CLK_RES_CTRL 0x5c -+#define APMU_QSPI_CLK_RES_CTRL 0x60 -+#define APMU_USB_CLK_RES_CTRL 0x5c -+#define APMU_DMA_CLK_RES_CTRL 0x64 -+#define APMU_AES_CLK_RES_CTRL 0x68 -+#define APMU_VPU_CLK_RES_CTRL 0xa4 -+#define APMU_GPU_CLK_RES_CTRL 0xcc -+#define APMU_SDH2_CLK_RES_CTRL 0xe0 -+#define APMU_PMUA_MC_CTRL 0xe8 -+#define APMU_PMU_CC2_AP 0x100 -+#define APMU_PMUA_EM_CLK_RES_CTRL 0x104 -+#define APMU_AUDIO_CLK_RES_CTRL 0x14c -+#define APMU_HDMI_CLK_RES_CTRL 0x1B8 -+#define APMU_PCIE_CLK_RES_CTRL_0 0x3cc -+#define APMU_PCIE_CLK_RES_CTRL_1 0x3d4 -+#define APMU_PCIE_CLK_RES_CTRL_2 0x3dc -+#define APMU_EMAC0_CLK_RES_CTRL 0x3e4 -+#define APMU_EMAC1_CLK_RES_CTRL 0x3ec -+ -+/* APBC2 register offset */ -+#define APBC2_UART1_CLK_RST 0x00 -+#define APBC2_SSP2_CLK_RST 0x04 -+#define APBC2_TWSI3_CLK_RST 0x08 -+#define APBC2_RTC_CLK_RST 0x0c -+#define APBC2_TIMERS0_CLK_RST 0x10 -+#define APBC2_KPC_CLK_RST 0x14 -+#define APBC2_GPIO_CLK_RST 0x1c -+/* end of APBC2 register offset */ -+ -+/* RCPU register offset */ -+#define RCPU_HDMI_CLK_RST 0x2044 -+#define RCPU_CAN_CLK_RST 0x4c -+#define RCPU_I2C0_CLK_RST 0x30 -+#define RCPU_SSP0_CLK_RST 0x28 -+#define RCPU_IR_CLK_RST 0x48 -+#define RCPU_UART0_CLK_RST 0xd8 -+#define RCPU_UART1_CLK_RST 0x3c -+ -+/* RCPU2 register offset */ -+#define RCPU2_PWM0_CLK_RST 0x00 -+#define RCPU2_PWM1_CLK_RST 0x04 -+#define RCPU2_PWM2_CLK_RST 0x08 -+#define RCPU2_PWM3_CLK_RST 0x0c -+#define RCPU2_PWM4_CLK_RST 0x10 -+#define RCPU2_PWM5_CLK_RST 0x14 -+#define RCPU2_PWM6_CLK_RST 0x18 -+#define RCPU2_PWM7_CLK_RST 0x1c -+#define RCPU2_PWM8_CLK_RST 0x20 -+#define RCPU2_PWM9_CLK_RST 0x24 -+ -+enum spacemit_reset_base_type { -+ RST_BASE_TYPE_MPMU = 0, -+ RST_BASE_TYPE_APMU = 1, -+ RST_BASE_TYPE_APBC = 2, -+ RST_BASE_TYPE_APBS = 3, -+ RST_BASE_TYPE_CIU = 4, -+ RST_BASE_TYPE_DCIU = 5, -+ RST_BASE_TYPE_DDRC = 6, -+ RST_BASE_TYPE_AUDC = 7, -+ RST_BASE_TYPE_APBC2 = 8, -+ RST_BASE_TYPE_RCPU = 9, -+ RST_BASE_TYPE_RCPU2 = 10, -+}; -+ -+struct spacemit_reset_signal { -+ u32 offset; -+ u32 mask; -+ u32 deassert_val; -+ u32 assert_val; -+ enum spacemit_reset_base_type type; -+}; -+ -+struct spacemit_reset_variant { -+ const struct spacemit_reset_signal *signals; -+ u32 signals_num; -+ const struct reset_control_ops ops; -+}; -+ -+struct spacemit_reset { -+ spinlock_t *lock; -+ struct reset_controller_dev rcdev; -+ void __iomem *mpmu_base; -+ void __iomem *apmu_base; -+ void __iomem *apbc_base; -+ void __iomem *apbs_base; -+ void __iomem *ciu_base; -+ void __iomem *dciu_base; -+ void __iomem *ddrc_base; -+ void __iomem *audio_ctrl_base; -+ void __iomem *apbc2_base; -+ void __iomem *rcpu_base; -+ void __iomem *rcpu2_base; -+ const struct spacemit_reset_signal *signals; -+}; -+ -+/* for register access protection */ -+extern spinlock_t g_cru_lock; -+struct spacemit_reset k1_reset_controller; -+ -+static const struct spacemit_reset_signal -+ k1_reset_signals[RESET_NUMBER] = { -+ [RESET_UART1] = { APBC_UART1_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_UART2] = { APBC_UART2_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_GPIO] = { APBC_GPIO_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_PWM0] = { APBC_PWM0_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_PWM1] = { APBC_PWM1_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_PWM2] = { APBC_PWM2_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_PWM3] = { APBC_PWM3_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_PWM4] = { APBC_PWM4_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_PWM5] = { APBC_PWM5_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_PWM6] = { APBC_PWM6_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_PWM7] = { APBC_PWM7_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_PWM8] = { APBC_PWM8_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_PWM9] = { APBC_PWM9_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_PWM10] = { APBC_PWM10_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_PWM11] = { APBC_PWM11_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_PWM12] = { APBC_PWM12_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_PWM13] = { APBC_PWM13_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_PWM14] = { APBC_PWM14_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_PWM15] = { APBC_PWM15_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_PWM16] = { APBC_PWM16_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_PWM17] = { APBC_PWM17_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_PWM18] = { APBC_PWM18_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_PWM19] = { APBC_PWM19_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_SSP3] = { APBC_SSP3_CLK_RST, BIT(2), 0, BIT(2), -+ RST_BASE_TYPE_APBC }, -+ [RESET_UART3] = { APBC_UART3_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_RTC] = { APBC_RTC_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_TWSI0] = { APBC_TWSI0_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_TIMERS1] = { APBC_TIMERS1_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_AIB] = { APBC_AIB_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_TIMERS2] = { APBC_TIMERS2_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_ONEWIRE] = { APBC_ONEWIRE_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_SSPA0] = { APBC_SSPA0_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_SSPA1] = { APBC_SSPA1_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_DRO] = { APBC_DRO_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_IR] = { APBC_IR_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_TWSI1] = { APBC_TWSI1_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_TSEN] = { APBC_TSEN_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_TWSI2] = { APBC_TWSI2_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_TWSI4] = { APBC_TWSI4_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_TWSI5] = { APBC_TWSI5_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_TWSI6] = { APBC_TWSI6_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_TWSI7] = { APBC_TWSI7_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_TWSI8] = { APBC_TWSI8_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_IPC_AP2AUD] = { APBC_IPC_AP2AUD_CLK_RST, -+ BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_UART4] = { APBC_UART4_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_UART5] = { APBC_UART5_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_UART6] = { APBC_UART6_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_UART7] = { APBC_UART7_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_UART8] = { APBC_UART8_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_UART9] = { APBC_UART9_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_CAN0] = { APBC_CAN0_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC }, -+ [RESET_WDT] = { MPMU_WDTPCR, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_MPMU }, -+ [RESET_JPG] = { APMU_JPG_CLK_RES_CTRL, BIT(0), -+ BIT(0), 0, RST_BASE_TYPE_APMU }, -+ [RESET_CSI] = { APMU_CSI_CCIC2_CLK_RES_CTRL, -+ BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU }, -+ [RESET_CCIC2_PHY] = { APMU_CSI_CCIC2_CLK_RES_CTRL, -+ BIT(2), BIT(2), 0, RST_BASE_TYPE_APMU }, -+ [RESET_CCIC3_PHY] = { APMU_CSI_CCIC2_CLK_RES_CTRL, -+ BIT(29), BIT(29), 0, RST_BASE_TYPE_APMU }, -+ [RESET_ISP] = { APMU_ISP_CLK_RES_CTRL, BIT(0), -+ BIT(0), 0, RST_BASE_TYPE_APMU }, -+ [RESET_ISP_AHB] = { APMU_ISP_CLK_RES_CTRL, BIT(3), -+ BIT(3), 0, RST_BASE_TYPE_APMU }, -+ [RESET_ISP_CI] = { APMU_ISP_CLK_RES_CTRL, BIT(16), -+ BIT(16), 0, RST_BASE_TYPE_APMU }, -+ [RESET_ISP_CPP] = { APMU_ISP_CLK_RES_CTRL, BIT(27), -+ BIT(27), 0, RST_BASE_TYPE_APMU }, -+ [RESET_LCD] = { APMU_LCD_CLK_RES_CTRL1, BIT(4), -+ BIT(4), 0, RST_BASE_TYPE_APMU }, -+ [RESET_DSI_ESC] = { APMU_LCD_CLK_RES_CTRL1, BIT(3), -+ BIT(3), 0, RST_BASE_TYPE_APMU }, -+ [RESET_V2D] = { APMU_LCD_CLK_RES_CTRL1, BIT(27), -+ BIT(27), 0, RST_BASE_TYPE_APMU }, -+ [RESET_MIPI] = { APMU_LCD_CLK_RES_CTRL1, BIT(15), -+ BIT(15), 0, RST_BASE_TYPE_APMU }, -+ [RESET_LCD_SPI] = { APMU_LCD_SPI_CLK_RES_CTRL, -+ BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU }, -+ [RESET_LCD_SPI_BUS] = { APMU_LCD_SPI_CLK_RES_CTRL, -+ BIT(4), BIT(4), 0, RST_BASE_TYPE_APMU }, -+ [RESET_LCD_SPI_HBUS] = { APMU_LCD_SPI_CLK_RES_CTRL, -+ BIT(2), BIT(2), 0, RST_BASE_TYPE_APMU }, -+ [RESET_LCD_MCLK] = { APMU_LCD_CLK_RES_CTRL2, BIT(9), -+ BIT(9), 0, RST_BASE_TYPE_APMU }, -+ [RESET_CCIC_4X] = { APMU_CCIC_CLK_RES_CTRL, -+ BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU }, -+ [RESET_CCIC1_PHY] = { APMU_CCIC_CLK_RES_CTRL, -+ BIT(2), BIT(2), 0, RST_BASE_TYPE_APMU }, -+ [RESET_SDH_AXI] = { APMU_SDH0_CLK_RES_CTRL, BIT(0), -+ BIT(0), 0, RST_BASE_TYPE_APMU }, -+ [RESET_SDH0] = { APMU_SDH0_CLK_RES_CTRL, BIT(1), -+ BIT(1), 0, RST_BASE_TYPE_APMU }, -+ [RESET_SDH1] = { APMU_SDH1_CLK_RES_CTRL, BIT(1), -+ BIT(1), 0, RST_BASE_TYPE_APMU }, -+ [RESET_USB_AXI] = { APMU_USB_CLK_RES_CTRL, BIT(0), -+ BIT(0), 0, RST_BASE_TYPE_APMU }, -+ [RESET_USBP1_AXI] = { APMU_USB_CLK_RES_CTRL, BIT(4), -+ BIT(4), 0, RST_BASE_TYPE_APMU }, -+ [RESET_USB3_0] = { APMU_USB_CLK_RES_CTRL, -+ BIT(9) | BIT(10) | BIT(11), BIT(9) | BIT(10) | BIT(11), -+ 0, RST_BASE_TYPE_APMU }, -+ [RESET_QSPI] = { APMU_QSPI_CLK_RES_CTRL, BIT(1), -+ BIT(1), 0, RST_BASE_TYPE_APMU }, -+ [RESET_QSPI_BUS] = { APMU_QSPI_CLK_RES_CTRL, BIT(0), -+ BIT(0), 0, RST_BASE_TYPE_APMU }, -+ [RESET_DMA] = { APMU_DMA_CLK_RES_CTRL, BIT(0), -+ BIT(0), 0, RST_BASE_TYPE_APMU }, -+ [RESET_AES] = { APMU_AES_CLK_RES_CTRL, BIT(4), -+ BIT(4), 0, RST_BASE_TYPE_APMU }, -+ [RESET_VPU] = { APMU_VPU_CLK_RES_CTRL, BIT(0), -+ BIT(0), 0, RST_BASE_TYPE_APMU }, -+ [RESET_GPU] = { APMU_GPU_CLK_RES_CTRL, BIT(1), -+ BIT(1), 0, RST_BASE_TYPE_APMU }, -+ [RESET_SDH2] = { APMU_SDH2_CLK_RES_CTRL, BIT(1), -+ BIT(1), 0, RST_BASE_TYPE_APMU }, -+ [RESET_MC] = { APMU_PMUA_MC_CTRL, BIT(0), -+ BIT(0), 0, RST_BASE_TYPE_APMU }, -+ [RESET_EM_AXI] = { APMU_PMUA_EM_CLK_RES_CTRL, BIT(0), -+ BIT(0), 0, RST_BASE_TYPE_APMU }, -+ [RESET_EM] = { APMU_PMUA_EM_CLK_RES_CTRL, BIT(1), -+ BIT(1), 0, RST_BASE_TYPE_APMU }, -+ [RESET_AUDIO_SYS] = { APMU_AUDIO_CLK_RES_CTRL, -+ BIT(0) | BIT(2) | BIT(3), BIT(0) | BIT(2) | BIT(3), -+ 0, RST_BASE_TYPE_APMU }, -+ [RESET_HDMI] = { APMU_HDMI_CLK_RES_CTRL, BIT(9), -+ BIT(9), 0, RST_BASE_TYPE_APMU }, -+ [RESET_PCIE0] = { APMU_PCIE_CLK_RES_CTRL_0, -+ BIT(3) | BIT(4) | BIT(5) | BIT(8), -+ BIT(3) | BIT(4) | BIT(5), BIT(8), -+ RST_BASE_TYPE_APMU }, -+ [RESET_PCIE1] = { APMU_PCIE_CLK_RES_CTRL_1, -+ BIT(3) | BIT(4) | BIT(5) | BIT(8), -+ BIT(3) | BIT(4) | BIT(5), BIT(8), -+ RST_BASE_TYPE_APMU }, -+ [RESET_PCIE2] = { APMU_PCIE_CLK_RES_CTRL_2, -+ 0x138, 0x38, 0x100, RST_BASE_TYPE_APMU }, -+ [RESET_EMAC0] = { APMU_EMAC0_CLK_RES_CTRL, BIT(1), -+ BIT(1), 0, RST_BASE_TYPE_APMU }, -+ [RESET_EMAC1] = { APMU_EMAC1_CLK_RES_CTRL, BIT(1), -+ BIT(1), 0, RST_BASE_TYPE_APMU }, -+ [RESET_SEC_UART1] = { APBC2_UART1_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC2 }, -+ [RESET_SEC_SSP2] = { APBC2_SSP2_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC2 }, -+ [RESET_SEC_TWSI3] = { APBC2_TWSI3_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC2 }, -+ [RESET_SEC_RTC] = { APBC2_RTC_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC2 }, -+ [RESET_SEC_TIMERS0] = { APBC2_TIMERS0_CLK_RST, -+ BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 }, -+ [RESET_SEC_KPC] = { APBC2_KPC_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC2 }, -+ [RESET_SEC_GPIO] = { APBC2_GPIO_CLK_RST, BIT(2), 0, -+ BIT(2), RST_BASE_TYPE_APBC2 }, -+ [RESET_RCPU_HDMIAUDIO] = { RCPU_HDMI_CLK_RST, BIT(0), -+ BIT(0), 0, RST_BASE_TYPE_RCPU }, -+ [RESET_RCPU_CAN] = { RCPU_CAN_CLK_RST, BIT(0), -+ BIT(0), 0, RST_BASE_TYPE_RCPU }, -+ -+ [RESET_RCPU_I2C0] = { RCPU_I2C0_CLK_RST, BIT(0), -+ BIT(0), 0, RST_BASE_TYPE_RCPU }, -+ [RESET_RCPU_SSP0] = { RCPU_SSP0_CLK_RST, BIT(0), -+ BIT(0), 0, RST_BASE_TYPE_RCPU }, -+ [RESET_RCPU_IR] = { RCPU_IR_CLK_RST, BIT(0), -+ BIT(0), 0, RST_BASE_TYPE_RCPU }, -+ [RESET_RCPU_UART0] = { RCPU_UART0_CLK_RST, BIT(0), -+ BIT(0), 0, RST_BASE_TYPE_RCPU }, -+ [RESET_RCPU_UART1] = { RCPU_UART1_CLK_RST, BIT(0), -+ BIT(0), 0, RST_BASE_TYPE_RCPU }, -+ -+ [RESET_RCPU2_PWM0] = { RCPU2_PWM0_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_RCPU2 }, -+ [RESET_RCPU2_PWM1] = { RCPU2_PWM1_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_RCPU2 }, -+ [RESET_RCPU2_PWM2] = { RCPU2_PWM2_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_RCPU2 }, -+ [RESET_RCPU2_PWM3] = { RCPU2_PWM3_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_RCPU2 }, -+ [RESET_RCPU2_PWM4] = { RCPU2_PWM4_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_RCPU2 }, -+ [RESET_RCPU2_PWM5] = { RCPU2_PWM5_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_RCPU2 }, -+ [RESET_RCPU2_PWM6] = { RCPU2_PWM6_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_RCPU2 }, -+ [RESET_RCPU2_PWM7] = { RCPU2_PWM7_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_RCPU2 }, -+ [RESET_RCPU2_PWM8] = { RCPU2_PWM8_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_RCPU2 }, -+ [RESET_RCPU2_PWM9] = { RCPU2_PWM9_CLK_RST, BIT(2) | BIT(0), -+ BIT(0), BIT(2), RST_BASE_TYPE_RCPU2 }, -+}; -+ -+static struct spacemit_reset *to_spacemit_reset(struct reset_controller_dev *rcdev) -+{ -+ return container_of(rcdev, struct spacemit_reset, rcdev); -+} -+ -+static u32 spacemit_reset_read(struct spacemit_reset *reset, u32 id) -+{ -+ void __iomem *base; -+ -+ switch (reset->signals[id].type) { -+ case RST_BASE_TYPE_MPMU: -+ base = reset->mpmu_base; -+ break; -+ case RST_BASE_TYPE_APMU: -+ base = reset->apmu_base; -+ break; -+ case RST_BASE_TYPE_APBC: -+ base = reset->apbc_base; -+ break; -+ case RST_BASE_TYPE_APBS: -+ base = reset->apbs_base; -+ break; -+ case RST_BASE_TYPE_CIU: -+ base = reset->ciu_base; -+ break; -+ case RST_BASE_TYPE_DCIU: -+ base = reset->dciu_base; -+ break; -+ case RST_BASE_TYPE_DDRC: -+ base = reset->ddrc_base; -+ break; -+ case RST_BASE_TYPE_AUDC: -+ base = reset->audio_ctrl_base; -+ break; -+ case RST_BASE_TYPE_APBC2: -+ base = reset->apbc2_base; -+ break; -+ case RST_BASE_TYPE_RCPU: -+ base = reset->rcpu_base; -+ break; -+ case RST_BASE_TYPE_RCPU2: -+ base = reset->rcpu2_base; -+ break; -+ default: -+ base = reset->apbc_base; -+ break; -+ } -+ -+ return readl(base + reset->signals[id].offset); -+} -+ -+static void spacemit_reset_write(struct spacemit_reset *reset, u32 value, u32 id) -+{ -+ void __iomem *base; -+ -+ switch (reset->signals[id].type) { -+ case RST_BASE_TYPE_MPMU: -+ base = reset->mpmu_base; -+ break; -+ case RST_BASE_TYPE_APMU: -+ base = reset->apmu_base; -+ break; -+ case RST_BASE_TYPE_APBC: -+ base = reset->apbc_base; -+ break; -+ case RST_BASE_TYPE_APBS: -+ base = reset->apbs_base; -+ break; -+ case RST_BASE_TYPE_CIU: -+ base = reset->ciu_base; -+ break; -+ case RST_BASE_TYPE_DCIU: -+ base = reset->dciu_base; -+ break; -+ case RST_BASE_TYPE_DDRC: -+ base = reset->ddrc_base; -+ break; -+ case RST_BASE_TYPE_AUDC: -+ base = reset->audio_ctrl_base; -+ break; -+ case RST_BASE_TYPE_APBC2: -+ base = reset->apbc2_base; -+ break; -+ case RST_BASE_TYPE_RCPU: -+ base = reset->rcpu_base; -+ break; -+ case RST_BASE_TYPE_RCPU2: -+ base = reset->rcpu2_base; -+ break; -+ default: -+ base = reset->apbc_base; -+ break; -+ } -+ -+ writel(value, base + reset->signals[id].offset); -+} -+ -+static void spacemit_reset_set(struct reset_controller_dev *rcdev, u32 id, bool assert) -+{ -+ u32 value; -+ struct spacemit_reset *reset = to_spacemit_reset(rcdev); -+ -+ value = spacemit_reset_read(reset, id); -+ if (assert) { -+ value &= ~reset->signals[id].mask; -+ value |= reset->signals[id].assert_val; -+ } else { -+ value &= ~reset->signals[id].mask; -+ value |= reset->signals[id].deassert_val; -+ } -+ spacemit_reset_write(reset, value, id); -+} -+ -+static int spacemit_reset_update(struct reset_controller_dev *rcdev, -+ unsigned long id, bool assert) -+{ -+ unsigned long flags; -+ struct spacemit_reset *reset = to_spacemit_reset(rcdev); -+ -+ if (id < RESET_UART1 || id >= RESET_NUMBER) -+ return 0; -+ -+ if (id == RESET_TWSI8) -+ return 0; -+ -+ spin_lock_irqsave(reset->lock, flags); -+ if (assert) -+ spacemit_reset_set(rcdev, id, assert); -+ else -+ spacemit_reset_set(rcdev, id, assert); -+ spin_unlock_irqrestore(reset->lock, flags); -+ -+ return 0; -+} -+ -+static int spacemit_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) -+{ -+ return spacemit_reset_update(rcdev, id, true); -+} -+ -+static int spacemit_reset_deassert(struct reset_controller_dev *rcdev, -+ unsigned long id) -+{ -+ return spacemit_reset_update(rcdev, id, false); -+} -+ -+static const struct spacemit_reset_variant k1_reset_data = { -+ .signals = k1_reset_signals, -+ .signals_num = ARRAY_SIZE(k1_reset_signals), -+ .ops = { -+ .assert = spacemit_reset_assert, -+ .deassert = spacemit_reset_deassert, -+ }, -+}; -+ -+static void spacemit_reset_init(struct device_node *np) -+{ -+ struct spacemit_reset *reset; -+ -+ if (of_device_is_compatible(np, "spacemit,k1-reset")) { -+ reset = &k1_reset_controller; -+ reset->mpmu_base = of_iomap(np, 0); -+ if (!reset->mpmu_base) { -+ pr_err("failed to map mpmu registers\n"); -+ goto out; -+ } -+ -+ reset->apmu_base = of_iomap(np, 1); -+ if (!reset->apmu_base) { -+ pr_err("failed to map apmu registers\n"); -+ goto out; -+ } -+ -+ reset->apbc_base = of_iomap(np, 2); -+ if (!reset->apbc_base) { -+ pr_err("failed to map apbc registers\n"); -+ goto out; -+ } -+ -+ reset->apbs_base = of_iomap(np, 3); -+ if (!reset->apbs_base) { -+ pr_err("failed to map apbs registers\n"); -+ goto out; -+ } -+ -+ reset->ciu_base = of_iomap(np, 4); -+ if (!reset->ciu_base) { -+ pr_err("failed to map ciu registers\n"); -+ goto out; -+ } -+ -+ reset->dciu_base = of_iomap(np, 5); -+ if (!reset->dciu_base) { -+ pr_err("failed to map dragon ciu registers\n"); -+ goto out; -+ } -+ -+ reset->ddrc_base = of_iomap(np, 6); -+ if (!reset->ddrc_base) { -+ pr_err("failed to map ddrc registers\n"); -+ goto out; -+ } -+ -+ reset->apbc2_base = of_iomap(np, 7); -+ if (!reset->apbc2_base) { -+ pr_err("failed to map apbc2 registers\n"); -+ goto out; -+ } -+ -+ reset->rcpu_base = of_iomap(np, 8); -+ if (!reset->rcpu_base) { -+ pr_err("failed to map rcpu registers\n"); -+ goto out; -+ } -+ -+ reset->rcpu2_base = of_iomap(np, 9); -+ if (!reset->rcpu2_base) { -+ pr_err("failed to map rcpu2 registers\n"); -+ goto out; -+ } -+ } else { -+ pr_err("not spacemit,k1-reset\n"); -+ goto out; -+ } -+ -+ reset->lock = &g_cru_lock; -+ reset->signals = k1_reset_data.signals; -+ reset->rcdev.owner = THIS_MODULE; -+ reset->rcdev.nr_resets = k1_reset_data.signals_num; -+ reset->rcdev.ops = &k1_reset_data.ops; -+ reset->rcdev.of_node = np; -+ reset_controller_register(&reset->rcdev); -+out: -+ return; -+} -+ -+CLK_OF_DECLARE(k1_reset, "spacemit,k1-reset", spacemit_reset_init); -+ diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c new file mode 100644 index 000000000000..06f82be725be @@ -510395,6 +510792,816 @@ index 000000000000..06f82be725be +MODULE_AUTHOR("zenglinghui.zlh "); +MODULE_DESCRIPTION("XuanTie th1520 reset driver"); +MODULE_LICENSE("GPL v2"); +diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig +new file mode 100644 +index 000000000000..beadc00a5146 +--- /dev/null ++++ b/drivers/reset/spacemit/Kconfig +@@ -0,0 +1,23 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++config RESET_SPACEMIT ++ tristate "SpacemiT reset driver" ++ depends on SOC_SPACEMIT || COMPILE_TEST ++ select AUXILIARY_BUS ++ default SOC_SPACEMIT ++ help ++ This enables the reset controller driver for SpacemiT SoCs. ++ ++config RESET_SPACEMIT_K1 ++ tristate "SpacemiT k1 reset driver" ++ depends on RESET_SPACEMIT || COMPILE_TEST ++ default SOC_SPACEMIT_K1 ++ help ++ This enables the reset controller driver for SpacemiT k1. ++ ++config RESET_SPACEMIT_K3 ++ tristate "SpacemiT k3 reset driver" ++ depends on RESET_SPACEMIT || COMPILE_TEST ++ default SOC_SPACEMIT_K3 ++ help ++ This enables the reset controller driver for SpacemiT k3. +diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makefile +new file mode 100644 +index 000000000000..d7f94ba6f01f +--- /dev/null ++++ b/drivers/reset/spacemit/Makefile +@@ -0,0 +1,4 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o ++obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-k1.o ++obj-$(CONFIG_RESET_SPACEMIT_K3) += reset-k3.o +diff --git a/drivers/reset/spacemit/reset-k1.c b/drivers/reset/spacemit/reset-k1.c +new file mode 100644 +index 000000000000..c58e0994cd19 +--- /dev/null ++++ b/drivers/reset/spacemit/reset-k1.c +@@ -0,0 +1,192 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++/* SpacemiT reset controller driver */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "reset-spacemit.h" ++ ++static const struct ccu_reset_data k1_mpmu_resets[] = { ++ [RESET_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0), ++}; ++ ++const struct ccu_reset_controller_data k1_mpmu_reset_data = { ++ .reset_data = k1_mpmu_resets, ++ .count = ARRAY_SIZE(k1_mpmu_resets), ++}; ++ ++static const struct ccu_reset_data k1_apbc_resets[] = { ++ [RESET_UART0] = RESET_DATA(APBC_UART1_CLK_RST, BIT(2), 0), ++ [RESET_UART2] = RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0), ++ [RESET_GPIO] = RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0), ++ [RESET_PWM0] = RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), BIT(0)), ++ [RESET_PWM1] = RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), BIT(0)), ++ [RESET_PWM2] = RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), BIT(0)), ++ [RESET_PWM3] = RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), BIT(0)), ++ [RESET_PWM4] = RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), BIT(0)), ++ [RESET_PWM5] = RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), BIT(0)), ++ [RESET_PWM6] = RESET_DATA(APBC_PWM6_CLK_RST, BIT(2), BIT(0)), ++ [RESET_PWM7] = RESET_DATA(APBC_PWM7_CLK_RST, BIT(2), BIT(0)), ++ [RESET_PWM8] = RESET_DATA(APBC_PWM8_CLK_RST, BIT(2), BIT(0)), ++ [RESET_PWM9] = RESET_DATA(APBC_PWM9_CLK_RST, BIT(2), BIT(0)), ++ [RESET_PWM10] = RESET_DATA(APBC_PWM10_CLK_RST, BIT(2), BIT(0)), ++ [RESET_PWM11] = RESET_DATA(APBC_PWM11_CLK_RST, BIT(2), BIT(0)), ++ [RESET_PWM12] = RESET_DATA(APBC_PWM12_CLK_RST, BIT(2), BIT(0)), ++ [RESET_PWM13] = RESET_DATA(APBC_PWM13_CLK_RST, BIT(2), BIT(0)), ++ [RESET_PWM14] = RESET_DATA(APBC_PWM14_CLK_RST, BIT(2), BIT(0)), ++ [RESET_PWM15] = RESET_DATA(APBC_PWM15_CLK_RST, BIT(2), BIT(0)), ++ [RESET_PWM16] = RESET_DATA(APBC_PWM16_CLK_RST, BIT(2), BIT(0)), ++ [RESET_PWM17] = RESET_DATA(APBC_PWM17_CLK_RST, BIT(2), BIT(0)), ++ [RESET_PWM18] = RESET_DATA(APBC_PWM18_CLK_RST, BIT(2), BIT(0)), ++ [RESET_PWM19] = RESET_DATA(APBC_PWM19_CLK_RST, BIT(2), BIT(0)), ++ [RESET_SSP3] = RESET_DATA(APBC_SSP3_CLK_RST, BIT(2), 0), ++ [RESET_UART3] = RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0), ++ [RESET_RTC] = RESET_DATA(APBC_RTC_CLK_RST, BIT(2), 0), ++ [RESET_TWSI0] = RESET_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0), ++ [RESET_TIMERS1] = RESET_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0), ++ [RESET_AIB] = RESET_DATA(APBC_AIB_CLK_RST, BIT(2), 0), ++ [RESET_TIMERS2] = RESET_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0), ++ [RESET_ONEWIRE] = RESET_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0), ++ [RESET_SSPA0] = RESET_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0), ++ [RESET_SSPA1] = RESET_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0), ++ [RESET_DRO] = RESET_DATA(APBC_DRO_CLK_RST, BIT(2), 0), ++ [RESET_IR] = RESET_DATA(APBC_IR_CLK_RST, BIT(2), 0), ++ [RESET_TWSI1] = RESET_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0), ++ [RESET_TSEN] = RESET_DATA(APBC_TSEN_CLK_RST, BIT(2), 0), ++ [RESET_TWSI2] = RESET_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0), ++ [RESET_TWSI4] = RESET_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0), ++ [RESET_TWSI5] = RESET_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0), ++ [RESET_TWSI6] = RESET_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0), ++ [RESET_TWSI7] = RESET_DATA(APBC_TWSI7_CLK_RST, BIT(2), 0), ++ [RESET_TWSI8] = RESET_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0), ++ [RESET_IPC_AP2AUD] = RESET_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0), ++ [RESET_UART4] = RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0), ++ [RESET_UART5] = RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0), ++ [RESET_UART6] = RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0), ++ [RESET_UART7] = RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0), ++ [RESET_UART8] = RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0), ++ [RESET_UART9] = RESET_DATA(APBC_UART9_CLK_RST, BIT(2), 0), ++ [RESET_CAN0] = RESET_DATA(APBC_CAN0_CLK_RST, BIT(2), 0), ++}; ++ ++const struct ccu_reset_controller_data k1_apbc_reset_data = { ++ .reset_data = k1_apbc_resets, ++ .count = ARRAY_SIZE(k1_apbc_resets), ++}; ++ ++static const struct ccu_reset_data k1_apmu_resets[] = { ++ [RESET_CCIC_4X] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_CCIC1_PHY] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)), ++ [RESET_SDH_AXI] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_USBP1_AXI] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(4)), ++ [RESET_USB_AXI] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_USB30_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(9)), ++ [RESET_USB30_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(10)), ++ [RESET_USB30_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(11)), ++ [RESET_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_AES] = RESET_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)), ++ [RESET_VPU] = RESET_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_GPU] = RESET_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_EMMC] = RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_EMMC_X] = RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_AUDIO_SYS] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_AUDIO_MCU] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, BIT(2)), ++ [RESET_AUDIO_APMU] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, BIT(3)), ++ [RESET_HDMI] = RESET_DATA(APMU_HDMI_CLK_RES_CTRL, 0, BIT(9)), ++ [RESET_PCIE0_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, 0, BIT(3)), ++ [RESET_PCIE0_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, 0, BIT(4)), ++ [RESET_PCIE0_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, 0, BIT(5)), ++ [RESET_PCIE0_GLOBAL] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, BIT(8), 0), ++ [RESET_PCIE1_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, 0, BIT(3)), ++ [RESET_PCIE1_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, 0, BIT(4)), ++ [RESET_PCIE1_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, 0, BIT(5)), ++ [RESET_PCIE1_GLOBAL] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, BIT(8), 0), ++ [RESET_PCIE2_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, 0, BIT(3)), ++ [RESET_PCIE2_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, 0, BIT(4)), ++ [RESET_PCIE2_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, 0, BIT(5)), ++ [RESET_PCIE2_GLOBAL] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, BIT(8), 0), ++ [RESET_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_JPG] = RESET_DATA(APMU_JPG_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_CCIC2PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)), ++ [RESET_CCIC3PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)), ++ [RESET_CSI] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_ISP] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_ISP_CPP] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(27)), ++ [RESET_ISP_BUS] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(3)), ++ [RESET_ISP_CI] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)), ++ [RESET_DPU_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)), ++ [RESET_DPU_ESC] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)), ++ [RESET_DPU_HCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)), ++ [RESET_DPU_SPIBUS] = RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(4)), ++ [RESET_DPU_SPI_HBUS] = RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(2)), ++ [RESET_V2D] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)), ++ [RESET_MIPI] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(15)), ++ [RESET_MC] = RESET_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)), ++}; ++ ++const struct ccu_reset_controller_data k1_apmu_reset_data = { ++ .reset_data = k1_apmu_resets, ++ .count = ARRAY_SIZE(k1_apmu_resets), ++}; ++ ++static const struct ccu_reset_data k1_rcpu_resets[] = { ++ [RESET_RCPU_SSP0] = RESET_DATA(RCPU_SSP0_CLK_RST, 0, BIT(0)), ++ [RESET_RCPU_I2C0] = RESET_DATA(RCPU_I2C0_CLK_RST, 0, BIT(0)), ++ [RESET_RCPU_UART1] = RESET_DATA(RCPU_UART1_CLK_RST, 0, BIT(0)), ++ [RESET_RCPU_IR] = RESET_DATA(RCPU_CAN_CLK_RST, 0, BIT(0)), ++ [RESET_RCPU_CAN] = RESET_DATA(RCPU_IR_CLK_RST, 0, BIT(0)), ++ [RESET_RCPU_UART0] = RESET_DATA(RCPU_UART0_CLK_RST, 0, BIT(0)), ++ [RESET_RCPU_HDMI_AUDIO] = RESET_DATA(AUDIO_HDMI_CLK_CTRL, 0, BIT(0)), ++}; ++ ++const struct ccu_reset_controller_data k1_rcpu_reset_data = { ++ .reset_data = k1_rcpu_resets, ++ .count = ARRAY_SIZE(k1_rcpu_resets), ++}; ++ ++static const struct ccu_reset_data k1_rcpu2_resets[] = { ++ [RESET_RCPU2_PWM0] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), ++ [RESET_RCPU2_PWM1] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), ++ [RESET_RCPU2_PWM2] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), ++ [RESET_RCPU2_PWM3] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), ++ [RESET_RCPU2_PWM4] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), ++ [RESET_RCPU2_PWM5] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), ++ [RESET_RCPU2_PWM6] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), ++ [RESET_RCPU2_PWM7] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), ++ [RESET_RCPU2_PWM8] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), ++ [RESET_RCPU2_PWM9] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), ++}; ++ ++const struct ccu_reset_controller_data k1_rcpu2_reset_data = { ++ .reset_data = k1_rcpu2_resets, ++ .count = ARRAY_SIZE(k1_rcpu2_resets), ++}; ++ ++static const struct ccu_reset_data k1_apbc2_resets[] = { ++ [RESET_APBC2_UART1] = RESET_DATA(APBC2_UART1_CLK_RST, BIT(2), 0), ++ [RESET_APBC2_SSP2] = RESET_DATA(APBC2_SSP2_CLK_RST, BIT(2), 0), ++ [RESET_APBC2_TWSI3] = RESET_DATA(APBC2_TWSI3_CLK_RST, BIT(2), 0), ++ [RESET_APBC2_RTC] = RESET_DATA(APBC2_RTC_CLK_RST, BIT(2), 0), ++ [RESET_APBC2_TIMERS0] = RESET_DATA(APBC2_TIMERS0_CLK_RST, BIT(2), 0), ++ [RESET_APBC2_KPC] = RESET_DATA(APBC2_KPC_CLK_RST, BIT(2), 0), ++ [RESET_APBC2_GPIO] = RESET_DATA(APBC2_GPIO_CLK_RST, BIT(2), 0), ++}; ++ ++const struct ccu_reset_controller_data k1_apbc2_reset_data = { ++ .reset_data = k1_apbc2_resets, ++ .count = ARRAY_SIZE(k1_apbc2_resets), ++}; ++ +diff --git a/drivers/reset/spacemit/reset-k1.h b/drivers/reset/spacemit/reset-k1.h +new file mode 100644 +index 000000000000..757ef92b4bd0 +--- /dev/null ++++ b/drivers/reset/spacemit/reset-k1.h +@@ -0,0 +1,24 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* ++ * Copyright (c) 2025 SpacemiT Technology Co. Ltd ++ * Copyright (c) 2025 Alex Elder ++ */ ++#ifndef __RESET_SPACEMIT_K1_H ++#define __RESET_SPACEMIT_K1_H ++#include "reset-spacemit.h" ++ ++#define K1_AUX_DEV_ID(_unit) \ ++ { \ ++ .name = "ccu_k1." #_unit "-reset", \ ++ .driver_data = (kernel_ulong_t)&k1_ ## _unit ## _reset_data, \ ++ } ++ ++extern const struct ccu_reset_controller_data k1_mpmu_reset_data; ++extern const struct ccu_reset_controller_data k1_apbc_reset_data; ++extern const struct ccu_reset_controller_data k1_apmu_reset_data; ++extern const struct ccu_reset_controller_data k1_rcpu_reset_data; ++extern const struct ccu_reset_controller_data k1_rcpu2_reset_data; ++extern const struct ccu_reset_controller_data k1_apbc2_reset_data; ++ ++#endif /* __RESET_SPACEMIT_K1_H */ +diff --git a/drivers/reset/spacemit/reset-k3.c b/drivers/reset/spacemit/reset-k3.c +new file mode 100644 +index 000000000000..f974346c07cc +--- /dev/null ++++ b/drivers/reset/spacemit/reset-k3.c +@@ -0,0 +1,335 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++/* SpacemiT reset controller driver */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "reset-spacemit.h" ++ ++static const struct ccu_reset_data k3_mpmu_resets[] = { ++ [RESET_MPMU_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0), ++ [RESET_MPMU_RIPC] = RESET_DATA(MPMU_RIPCCR, BIT(2), 0), ++}; ++ ++const struct ccu_reset_controller_data k3_mpmu_reset_data = { ++ .reset_data = k3_mpmu_resets, ++ .count = ARRAY_SIZE(k3_mpmu_resets), ++}; ++ ++static const struct ccu_reset_data k3_apbc_resets[] = { ++ [RESET_APBC_UART0] = RESET_DATA(APBC_UART0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART2] = RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART3] = RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART4] = RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART5] = RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART6] = RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART7] = RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART8] = RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART9] = RESET_DATA(APBC_UART9_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART10] = RESET_DATA(APBC_UART10_CLK_RST, BIT(2), 0), ++ [RESET_APBC_GPIO] = RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM0] = RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM1] = RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM2] = RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM3] = RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM4] = RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM5] = RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM6] = RESET_DATA(APBC_PWM6_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM7] = RESET_DATA(APBC_PWM7_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM8] = RESET_DATA(APBC_PWM8_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM9] = RESET_DATA(APBC_PWM9_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM10] = RESET_DATA(APBC_PWM10_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM11] = RESET_DATA(APBC_PWM11_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM12] = RESET_DATA(APBC_PWM12_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM13] = RESET_DATA(APBC_PWM13_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM14] = RESET_DATA(APBC_PWM14_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM15] = RESET_DATA(APBC_PWM15_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM16] = RESET_DATA(APBC_PWM16_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM17] = RESET_DATA(APBC_PWM17_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM18] = RESET_DATA(APBC_PWM18_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM19] = RESET_DATA(APBC_PWM19_CLK_RST, BIT(2), 0), ++ [RESET_APBC_SPI0] = RESET_DATA(APBC_SSP0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_SPI1] = RESET_DATA(APBC_SSP1_CLK_RST, BIT(2), 0), ++ [RESET_APBC_SPI3] = RESET_DATA(APBC_SSP3_CLK_RST, BIT(2), 0), ++ [RESET_APBC_RTC] = RESET_DATA(APBC_RTC_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TWSI0] = RESET_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TWSI1] = RESET_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TWSI2] = RESET_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TWSI4] = RESET_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TWSI5] = RESET_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TWSI6] = RESET_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TWSI8] = RESET_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS0] = RESET_DATA(APBC_TIMERS0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS1] = RESET_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS2] = RESET_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS3] = RESET_DATA(APBC_TIMERS3_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS4] = RESET_DATA(APBC_TIMERS4_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS5] = RESET_DATA(APBC_TIMERS5_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS6] = RESET_DATA(APBC_TIMERS6_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS7] = RESET_DATA(APBC_TIMERS7_CLK_RST, BIT(2), 0), ++ [RESET_APBC_AIB] = RESET_DATA(APBC_AIB_CLK_RST, BIT(2), 0), ++ [RESET_APBC_ONEWIRE] = RESET_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0), ++ [RESET_APBC_I2S0] = RESET_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_I2S1] = RESET_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0), ++ [RESET_APBC_I2S2] = RESET_DATA(APBC_SSPA2_CLK_RST, BIT(2), 0), ++ [RESET_APBC_I2S3] = RESET_DATA(APBC_SSPA3_CLK_RST, BIT(2), 0), ++ [RESET_APBC_I2S4] = RESET_DATA(APBC_SSPA4_CLK_RST, BIT(2), 0), ++ [RESET_APBC_I2S5] = RESET_DATA(APBC_SSPA5_CLK_RST, BIT(2), 0), ++ [RESET_APBC_DRO] = RESET_DATA(APBC_DRO_CLK_RST, BIT(2), 0), ++ [RESET_APBC_IR0] = RESET_DATA(APBC_IR0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_IR1] = RESET_DATA(APBC_IR1_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TSEN] = RESET_DATA(APBC_TSEN_CLK_RST, BIT(2), 0), ++ [RESET_IPC_AP2AUD] = RESET_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0), ++ [RESET_APBC_CAN0] = RESET_DATA(APBC_CAN0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_CAN1] = RESET_DATA(APBC_CAN1_CLK_RST, BIT(2), 0), ++ [RESET_APBC_CAN2] = RESET_DATA(APBC_CAN2_CLK_RST, BIT(2), 0), ++ [RESET_APBC_CAN3] = RESET_DATA(APBC_CAN3_CLK_RST, BIT(2), 0), ++ [RESET_APBC_CAN4] = RESET_DATA(APBC_CAN4_CLK_RST, BIT(2), 0), ++}; ++ ++const struct ccu_reset_controller_data k3_apbc_reset_data = { ++ .reset_data = k3_apbc_resets, ++ .count = ARRAY_SIZE(k3_apbc_resets), ++}; ++ ++static const struct ccu_reset_data k3_apmu_resets[] = { ++ [RESET_APMU_CSI] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_CCIC2PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)), ++ [RESET_APMU_CCIC3PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)), ++ [RESET_APMU_ISP_CIBUS] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)), ++ [RESET_APMU_DSI_ESC] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)), ++ [RESET_APMU_LCD] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)), ++ [RESET_APMU_V2D] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)), ++ [RESET_APMU_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)), ++ [RESET_APMU_LCD_DSCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(15)), ++ [RESET_APMU_SC2_HCLK] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_CCIC_4X] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_CCIC1_PHY] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)), ++ [RESET_APMU_SDH_AXI] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_USB2] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, ++ BIT(1)|BIT(2)|BIT(3)), ++ [RESET_APMU_USB3_PORTA] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, ++ BIT(5)|BIT(6)|BIT(7)), ++ [RESET_APMU_USB3_PORTB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, ++ BIT(9)|BIT(10)|BIT(11)), ++ [RESET_APMU_USB3_PORTC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, ++ BIT(13)|BIT(14)|BIT(15)), ++ [RESET_APMU_USB3_PORTD] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, ++ BIT(17)|BIT(18)|BIT(19)), ++ [RESET_APMU_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_AES_WTM] = RESET_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)), ++ [RESET_APMU_MCB_DCLK] = RESET_DATA(APMU_MCB_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_MCB_ACLK] = RESET_DATA(APMU_MCB_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_VPU] = RESET_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_DTC] = RESET_DATA(APMU_DTC_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_GPU] = RESET_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_MC] = RESET_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)), ++ [RESET_APMU_CPU0_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(0), 0), ++ [RESET_APMU_CPU0_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(1), 0), ++ [RESET_APMU_CPU1_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(3), 0), ++ [RESET_APMU_CPU1_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(4), 0), ++ [RESET_APMU_CPU2_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(6), 0), ++ [RESET_APMU_CPU2_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(7), 0), ++ [RESET_APMU_CPU3_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(9), 0), ++ [RESET_APMU_CPU3_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(10), 0), ++ [RESET_APMU_C0_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(12), 0), ++ [RESET_APMU_CPU4_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(16), 0), ++ [RESET_APMU_CPU4_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(17), 0), ++ [RESET_APMU_CPU5_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(19), 0), ++ [RESET_APMU_CPU5_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(20), 0), ++ [RESET_APMU_CPU6_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(22), 0), ++ [RESET_APMU_CPU6_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(23), 0), ++ [RESET_APMU_CPU7_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(25), 0), ++ [RESET_APMU_CPU7_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(26), 0), ++ [RESET_APMU_C1_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(28), 0), ++ [RESET_APMU_MPSUB_DBG] = RESET_DATA(APMU_PMU_CC2_AP, BIT(29), 0), ++ [RESET_APMU_UCIE] = RESET_DATA(APMU_UCIE_CTRL, ++ BIT(1) | BIT(2) | BIT(3), 0), ++ [RESET_APMU_RCPU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, ++ BIT(3) | BIT(2) | BIT(0)), ++ [RESET_APMU_DSI4LN2_ESCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(3)), ++ [RESET_APMU_DSI4LN2_LCD_SW] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(4)), ++ [RESET_APMU_DSI4LN2_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(9)), ++ [RESET_APMU_DSI4LN2_LCD_DSCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(15)), ++ [RESET_APMU_DSI4LN2_DPU_ACLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL5, 0, BIT(0)), ++ [RESET_APMU_DPU_ACLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL5, 0, BIT(15)), ++ [RESET_APMU_UFS_ACLK] = RESET_DATA(APMU_UFS_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_EDP0] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(0)), ++ [RESET_APMU_EDP1] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(16)), ++ [RESET_APMU_PCIE_PORTA] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, ++ BIT(5) | BIT(4) | BIT(3)), ++ [RESET_APMU_PCIE_PORTB] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, ++ BIT(5) | BIT(4) | BIT(3)), ++ [RESET_APMU_PCIE_PORTC] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, ++ BIT(5) | BIT(4) | BIT(3)), ++ [RESET_APMU_PCIE_PORTD] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, ++ BIT(5) | BIT(4) | BIT(3)), ++ [RESET_APMU_PCIE_PORTE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, ++ BIT(5) | BIT(4) | BIT(3)), ++ [RESET_APMU_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_EMAC2] = RESET_DATA(APMU_EMAC2_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_ESPI_MCLK] = RESET_DATA(APMU_ESPI_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_ESPI_SCLK] = RESET_DATA(APMU_ESPI_CLK_RES_CTRL, 0, BIT(2)), ++}; ++ ++const struct ccu_reset_controller_data k3_apmu_reset_data = { ++ .reset_data = k3_apmu_resets, ++ .count = ARRAY_SIZE(k3_apmu_resets), ++}; ++ ++static const struct ccu_reset_data k3_dciu_resets[] = { ++ [RESET_DCIU_HDMA] = RESET_DATA(DCIU_DMASYS_RSTN, 0, BIT(0)), ++ [RESET_DCIU_DMA350] = RESET_DATA(DCIU_DMASYS_SDMA_RSTN, 0, BIT(0)), ++ [RESET_DCIU_DMA350_0] = RESET_DATA(DCIU_DMASYS_S0_RSTN, 0, BIT(0)), ++ [RESET_DCIU_DMA350_1] = RESET_DATA(DCIU_DMASYS_S1_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA0] = RESET_DATA(DCIU_DMASYS_A0_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA1] = RESET_DATA(DCIU_DMASYS_A1_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA2] = RESET_DATA(DCIU_DMASYS_A2_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA3] = RESET_DATA(DCIU_DMASYS_A3_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA4] = RESET_DATA(DCIU_DMASYS_A4_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA5] = RESET_DATA(DCIU_DMASYS_A5_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA6] = RESET_DATA(DCIU_DMASYS_A6_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA7] = RESET_DATA(DCIU_DMASYS_A7_RSTN, 0, BIT(0)), ++}; ++ ++const struct ccu_reset_controller_data k3_dciu_reset_data = { ++ .reset_data = k3_dciu_resets, ++ .count = ARRAY_SIZE(k3_dciu_resets), ++}; ++ ++static const struct ccu_reset_data k3_rsysctrl_resets[] = { ++ [RESET_RCPU_SYSCTRL_RCAN0] = RESET_DATA(RCPU_CAN_CLK_RST, 0, BIT(0)), ++ [RESET_RCPU_SYSCTRL_RCAN1] = RESET_DATA(RCPU_CAN1_CLK_RST, 0, BIT(0)), ++ [RESET_RCPU_SYSCTRL_RCAN2] = RESET_DATA(RCPU_CAN2_CLK_RST, 0, BIT(0)), ++ [RESET_RCPU_SYSCTRL_RCAN3] = RESET_DATA(RCPU_CAN3_CLK_RST, 0, BIT(0)), ++ [RESET_RCPU_SYSCTRL_RCAN4] = RESET_DATA(RCPU_CAN4_CLK_RST, 0, BIT(0)), ++ [RESET_RCPU_SYSCTRL_RIRC0] = RESET_DATA(RCPU_IRC_CLK_RST, 0, BIT(0)), ++ [RESET_RCPU_SYSCTRL_RIRC1] = RESET_DATA(RCPU_IRC1_CLK_RST, 0, BIT(0)), ++ [RESET_RCPU_SYSCTRL_RGMAC] = RESET_DATA(RCPU_GMAC_CLK_RST, 0, BIT(1)), ++ [RESET_RCPU_SYSCTRL_RESPI] = RESET_DATA(RCPU_ESPI_CLK_RST, 0, BIT(0)), ++ [RESET_RCPU_SYSCTRL_RI2S0_SYSCLK] = RESET_DATA(RCPU_AUDIO_I2S0_SYS_CLK_CTRL, ++ 0, BIT(0)), ++ [RESET_RCPU_SYSCTRL_RI2S1_SYSCLK] = RESET_DATA(RCPU_AUDIO_I2S1_SYS_CLK_CTRL, ++ 0, BIT(0)), ++}; ++ ++const struct ccu_reset_controller_data k3_rsysctrl_reset_data = { ++ .reset_data = k3_rsysctrl_resets, ++ .count = ARRAY_SIZE(k3_rsysctrl_resets), ++}; ++ ++static const struct ccu_reset_data k3_ruartctrl_resets[] = { ++ [RESET_RCPU_UARTCTRL_RUART0] = RESET_DATA(RCPU1_UART0_CLK_RST, BIT(2), 0), ++ [RESET_RCPU_UARTCTRL_RUART1] = RESET_DATA(RCPU1_UART1_CLK_RST, BIT(2), 0), ++ [RESET_RCPU_UARTCTRL_RUART2] = RESET_DATA(RCPU1_UART2_CLK_RST, BIT(2), 0), ++ [RESET_RCPU_UARTCTRL_RUART3] = RESET_DATA(RCPU1_UART3_CLK_RST, BIT(2), 0), ++ [RESET_RCPU_UARTCTRL_RUART4] = RESET_DATA(RCPU1_UART4_CLK_RST, BIT(2), 0), ++ [RESET_RCPU_UARTCTRL_RUART5] = RESET_DATA(RCPU1_UART5_CLK_RST, BIT(2), 0), ++}; ++ ++const struct ccu_reset_controller_data k3_ruartctrl_reset_data = { ++ .reset_data = k3_ruartctrl_resets, ++ .count = ARRAY_SIZE(k3_ruartctrl_resets), ++}; ++ ++static const struct ccu_reset_data k3_ri2sctrl_resets[] = { ++ [RESET_RCPU_I2SCTRL_RI2S0] = RESET_DATA(RCPU2_AUDIO_I2S0_TX_RX_CLK_CTRL, 0, BIT(0)), ++ [RESET_RCPU_I2SCTRL_RI2S1] = RESET_DATA(RCPU2_AUDIO_I2S1_TX_RX_CLK_CTRL, 0, BIT(0)), ++ [RESET_RCPU_I2SCTRL_RI2S2] = RESET_DATA(RCPU2_AUDIO_I2S2_TX_RX_CLK_CTRL, 0, BIT(0)), ++ [RESET_RCPU_I2SCTRL_RI2S3] = RESET_DATA(RCPU2_AUDIO_I2S3_TX_RX_CLK_CTRL, 0, BIT(0)), ++ [RESET_RCPU_I2SCTRL_RI2S2_SYSCLK] = RESET_DATA(RCPU2_AUDIO_I2S2_SYS_CLK_CTRL, ++ 0, BIT(0)), ++ [RESET_RCPU_I2SCTRL_RI2S3_SYSCLK] = RESET_DATA(RCPU2_AUDIO_I2S3_SYS_CLK_CTRL, ++ 0, BIT(0)), ++}; ++ ++const struct ccu_reset_controller_data k3_ri2sctrl_reset_data = { ++ .reset_data = k3_ri2sctrl_resets, ++ .count = ARRAY_SIZE(k3_ri2sctrl_resets), ++}; ++ ++static const struct ccu_reset_data k3_rspictrl_resets[] = { ++ [RESET_RCPU_SPICTRL_RSPI0] = RESET_DATA(RCPU3_SSP0_CLK_RST, BIT(2), 0), ++ [RESET_RCPU_SPICTRL_RSPI1] = RESET_DATA(RCPU3_SSP1_CLK_RST, BIT(2), 0), ++ [RESET_RCPU_SPICTRL_RSPI2] = RESET_DATA(RCPU3_PWR_SSP_CLK_RST, BIT(2), 0), ++}; ++ ++const struct ccu_reset_controller_data k3_rspictrl_reset_data = { ++ .reset_data = k3_rspictrl_resets, ++ .count = ARRAY_SIZE(k3_rspictrl_resets), ++}; ++ ++static const struct ccu_reset_data k3_ri2cctrl_resets[] = { ++ [RESET_RCPU_I2CCTRL_RI2C0] = RESET_DATA(RCPU4_I2C0_CLK_RST, BIT(2), 0), ++ [RESET_RCPU_I2CCTRL_RI2C1] = RESET_DATA(RCPU4_I2C1_CLK_RST, BIT(2), 0), ++ [RESET_RCPU_I2CCTRL_RI2C2] = RESET_DATA(RCPU4_PWR_I2C_CLK_RST, BIT(2), 0), ++}; ++ ++const struct ccu_reset_controller_data k3_ri2cctrl_reset_data = { ++ .reset_data = k3_ri2cctrl_resets, ++ .count = ARRAY_SIZE(k3_ri2cctrl_resets), ++}; ++ ++static const struct ccu_reset_data k3_rpmu_resets[] = { ++ [RESET_RPMU_RTIMER1] = RESET_DATA(RCPU5_TIMER1_CLK_RST, 0, BIT(0)), ++ [RESET_RPMU_RTIMER2] = RESET_DATA(RCPU5_TIMER2_CLK_RST, 0, BIT(0)), ++ [RESET_RPMU_RTIMER3] = RESET_DATA(RCPU5_TIMER3_CLK_RST, 0, BIT(0)), ++ [RESET_RPMU_RTIMER4] = RESET_DATA(RCPU5_TIMER4_CLK_RST, 0, BIT(0)), ++ [RESET_RPMU_IPC2AP] = RESET_DATA(RCPU5_AON_PER_CLK_RST_CTRL, 0, BIT(0)), ++ [RESET_RPMU_IPC2CP] = RESET_DATA(RCPU5_AON_PER_CLK_RST_CTRL, 0, BIT(2)), ++ [RESET_RPMU_IPC2MSA] = RESET_DATA(RCPU5_AON_PER_CLK_RST_CTRL, 0, BIT(4)), ++ [RESET_RPMU_RT24_CORE0] = RESET_DATA(RCPU5_RT24_CORE0_SW_RESET, BIT(0), 0), ++ [RESET_RPMU_RT24_CORE1] = RESET_DATA(RCPU5_RT24_CORE1_SW_RESET, BIT(0), 0), ++ [RESET_RPMU_GPIO] = RESET_DATA(RCPU5_GPIO_AND_EDGE_CLK_RST, 0, BIT(0)), ++ [RESET_RPMU_GPIO_EDGE] = RESET_DATA(RCPU5_GPIO_AND_EDGE_CLK_RST, 0, BIT(2)), ++}; ++ ++const struct ccu_reset_controller_data k3_rpmu_reset_data = { ++ .reset_data = k3_rpmu_resets, ++ .count = ARRAY_SIZE(k3_rpmu_resets), ++}; ++ ++static const struct ccu_reset_data k3_rpwmctrl_resets[] = { ++ [RESET_RCPU_PWMCTRL_PWM0] = RESET_DATA(RCPU6_PWM0_CLK_RST, BIT(2), 0), ++ [RESET_RCPU_PWMCTRL_PWM1] = RESET_DATA(RCPU6_PWM1_CLK_RST, BIT(2), 0), ++ [RESET_RCPU_PWMCTRL_PWM2] = RESET_DATA(RCPU6_PWM2_CLK_RST, BIT(2), 0), ++ [RESET_RCPU_PWMCTRL_PWM3] = RESET_DATA(RCPU6_PWM3_CLK_RST, BIT(2), 0), ++ [RESET_RCPU_PWMCTRL_PWM4] = RESET_DATA(RCPU6_PWM4_CLK_RST, BIT(2), 0), ++ [RESET_RCPU_PWMCTRL_PWM5] = RESET_DATA(RCPU6_PWM5_CLK_RST, BIT(2), 0), ++ [RESET_RCPU_PWMCTRL_PWM6] = RESET_DATA(RCPU6_PWM6_CLK_RST, BIT(2), 0), ++ [RESET_RCPU_PWMCTRL_PWM7] = RESET_DATA(RCPU6_PWM7_CLK_RST, BIT(2), 0), ++ [RESET_RCPU_PWMCTRL_PWM8] = RESET_DATA(RCPU6_PWM8_CLK_RST, BIT(2), 0), ++ [RESET_RCPU_PWMCTRL_PWM9] = RESET_DATA(RCPU6_PWM9_CLK_RST, BIT(2), 0), ++}; ++ ++const struct ccu_reset_controller_data k3_rpwmctrl_reset_data = { ++ .reset_data = k3_rpwmctrl_resets, ++ .count = ARRAY_SIZE(k3_rpwmctrl_resets), ++}; ++ ++static const struct ccu_reset_data k3_apbc2_resets[] = { ++ [RESET_APBC2_SEC_UART1] = RESET_DATA(APBC2_UART1_CLK_RST, BIT(2), 0), ++ [RESET_APBC2_SEC_SPI2] = RESET_DATA(APBC2_SSP2_CLK_RST, BIT(2), 0), ++ [RESET_APBC2_SEC_TWSI3] = RESET_DATA(APBC2_TWSI3_CLK_RST, BIT(2), 0), ++ [RESET_APBC2_SEC_RTC] = RESET_DATA(APBC2_RTC_CLK_RST, BIT(2), 0), ++ [RESET_APBC2_SEC_TIMERS] = RESET_DATA(APBC2_TIMERS_CLK_RST, BIT(2), 0), ++ [RESET_APBC2_SEC_GPIO] = RESET_DATA(APBC2_GPIO_CLK_RST, BIT(2), 0), ++}; ++ ++const struct ccu_reset_controller_data k3_apbc2_reset_data = { ++ .reset_data = k3_apbc2_resets, ++ .count = ARRAY_SIZE(k3_apbc2_resets), ++}; +diff --git a/drivers/reset/spacemit/reset-k3.h b/drivers/reset/spacemit/reset-k3.h +new file mode 100644 +index 000000000000..a990525737aa +--- /dev/null ++++ b/drivers/reset/spacemit/reset-k3.h +@@ -0,0 +1,30 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* ++ * Copyright (c) 2025 SpacemiT Technology Co. Ltd ++ * Copyright (c) 2025 Alex Elder ++ */ ++#ifndef __RESET_SPACEMIT_K3_H ++#define __RESET_SPACEMIT_K3_H ++#include "reset-spacemit.h" ++ ++#define K3_AUX_DEV_ID(_unit) \ ++ { \ ++ .name = "ccu_k3." #_unit "-reset", \ ++ .driver_data = (kernel_ulong_t)&k3_ ## _unit ## _reset_data, \ ++ } ++ ++extern const struct ccu_reset_controller_data k3_mpmu_reset_data; ++extern const struct ccu_reset_controller_data k3_apbc_reset_data; ++extern const struct ccu_reset_controller_data k3_apmu_reset_data; ++extern const struct ccu_reset_controller_data k3_dciu_reset_data; ++extern const struct ccu_reset_controller_data k3_rsysctrl_reset_data; ++extern const struct ccu_reset_controller_data k3_ruartctrl_reset_data; ++extern const struct ccu_reset_controller_data k3_ri2sctrl_reset_data; ++extern const struct ccu_reset_controller_data k3_rspictrl_reset_data; ++extern const struct ccu_reset_controller_data k3_ri2cctrl_reset_data; ++extern const struct ccu_reset_controller_data k3_rpmu_reset_data; ++extern const struct ccu_reset_controller_data k3_rpwmctrl_reset_data; ++extern const struct ccu_reset_controller_data k3_apbc2_reset_data; ++ ++#endif /* __RESET_SPACEMIT_K3_H */ +diff --git a/drivers/reset/spacemit/reset-spacemit.c b/drivers/reset/spacemit/reset-spacemit.c +new file mode 100644 +index 000000000000..b58cc0079021 +--- /dev/null ++++ b/drivers/reset/spacemit/reset-spacemit.c +@@ -0,0 +1,117 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++/* ++ * Copyright (c) 2025 SpacemiT Technology Co. Ltd ++ * Copyright (c) 2025 Alex Elder ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "reset-spacemit.h" ++#include "reset-k1.h" ++#include "reset-k3.h" ++ ++static int spacemit_reset_update(struct reset_controller_dev *rcdev, ++ unsigned long id, bool assert) ++{ ++ struct ccu_reset_controller *controller; ++ const struct ccu_reset_data *data; ++ u32 mask; ++ u32 val; ++ ++ controller = container_of(rcdev, struct ccu_reset_controller, rcdev); ++ data = &controller->data->reset_data[id]; ++ mask = data->assert_mask | data->deassert_mask; ++ val = assert ? data->assert_mask : data->deassert_mask; ++ ++ return regmap_update_bits(controller->regmap, data->offset, mask, val); ++} ++ ++static int spacemit_reset_assert(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ return spacemit_reset_update(rcdev, id, true); ++} ++ ++static int spacemit_reset_deassert(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ return spacemit_reset_update(rcdev, id, false); ++} ++ ++static const struct reset_control_ops spacemit_reset_control_ops = { ++ .assert = spacemit_reset_assert, ++ .deassert = spacemit_reset_deassert, ++}; ++ ++static int spacemit_reset_controller_register(struct device *dev, ++ struct ccu_reset_controller *controller) ++{ ++ struct reset_controller_dev *rcdev = &controller->rcdev; ++ ++ rcdev->ops = &spacemit_reset_control_ops; ++ rcdev->owner = THIS_MODULE; ++ rcdev->of_node = dev->of_node; ++ rcdev->nr_resets = controller->data->count; ++ ++ return devm_reset_controller_register(dev, &controller->rcdev); ++} ++ ++static int spacemit_reset_probe(struct auxiliary_device *adev, ++ const struct auxiliary_device_id *id) ++{ ++ struct spacemit_ccu_adev *rdev = to_spacemit_ccu_adev(adev); ++ struct ccu_reset_controller *controller; ++ struct device *dev = &adev->dev; ++ ++ controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); ++ if (!controller) ++ return -ENOMEM; ++ controller->data = (const struct ccu_reset_controller_data *)id->driver_data; ++ controller->regmap = rdev->regmap; ++ ++ return spacemit_reset_controller_register(dev, controller); ++} ++ ++static const struct auxiliary_device_id spacemit_reset_ids[] = { ++#ifdef CONFIG_RESET_SPACEMIT_K1 ++ K1_AUX_DEV_ID(mpmu), ++ K1_AUX_DEV_ID(apbc), ++ K1_AUX_DEV_ID(apmu), ++ K1_AUX_DEV_ID(rcpu), ++ K1_AUX_DEV_ID(rcpu2), ++ K1_AUX_DEV_ID(apbc2), ++#endif ++ ++#ifdef CONFIG_RESET_SPACEMIT_K3 ++ K3_AUX_DEV_ID(mpmu), ++ K3_AUX_DEV_ID(apbc), ++ K3_AUX_DEV_ID(apmu), ++ K3_AUX_DEV_ID(dciu), ++ K3_AUX_DEV_ID(rsysctrl), ++ K3_AUX_DEV_ID(ruartctrl), ++ K3_AUX_DEV_ID(ri2sctrl), ++ K3_AUX_DEV_ID(rspictrl), ++ K3_AUX_DEV_ID(ri2cctrl), ++ K3_AUX_DEV_ID(rpmu), ++ K3_AUX_DEV_ID(rpwmctrl), ++ K3_AUX_DEV_ID(apbc2), ++#endif ++ { }, ++}; ++MODULE_DEVICE_TABLE(auxiliary, spacemit_reset_ids); ++ ++static struct auxiliary_driver spacemit_k1_reset_driver = { ++ .probe = spacemit_reset_probe, ++ .id_table = spacemit_reset_ids, ++}; ++module_auxiliary_driver(spacemit_k1_reset_driver); ++ ++MODULE_AUTHOR("Alex Elder "); ++MODULE_DESCRIPTION("SpacemiT reset controller driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/reset/spacemit/reset-spacemit.h b/drivers/reset/spacemit/reset-spacemit.h +new file mode 100644 +index 000000000000..0ee1944f1727 +--- /dev/null ++++ b/drivers/reset/spacemit/reset-spacemit.h +@@ -0,0 +1,37 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* ++ * Copyright (c) 2025 SpacemiT Technology Co. Ltd ++ * Copyright (c) 2025 Alex Elder ++ */ ++#ifndef __RESET_SPACEMIT_H ++#define __RESET_SPACEMIT_H ++ ++#include ++#include ++ ++struct ccu_reset_data { ++ u32 offset; ++ u32 assert_mask; ++ u32 deassert_mask; ++}; ++ ++struct ccu_reset_controller_data { ++ const struct ccu_reset_data *reset_data; /* array */ ++ size_t count; ++}; ++ ++struct ccu_reset_controller { ++ struct reset_controller_dev rcdev; ++ const struct ccu_reset_controller_data *data; ++ struct regmap *regmap; ++}; ++ ++#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \ ++ { \ ++ .offset = (_offset), \ ++ .assert_mask = (_assert_mask), \ ++ .deassert_mask = (_deassert_mask), \ ++ } ++ ++#endif /* __RESET_SPACEMIT_H */ diff --git a/drivers/rpmsg/Kconfig b/drivers/rpmsg/Kconfig index d3795860f5c0..13c3bffdb881 100644 --- a/drivers/rpmsg/Kconfig @@ -630546,235 +631753,1158 @@ index 000000000000..5584243f9135 +#define SAFE_MODE 2 +#define BYPASS_MODE 3 +#endif -diff --git a/include/dt-bindings/clock/spacemit-k1-clock.h b/include/dt-bindings/clock/spacemit-k1-clock.h +diff --git a/include/dt-bindings/clock/spacemit,k1-syscon.h b/include/dt-bindings/clock/spacemit,k1-syscon.h new file mode 100644 -index 000000000000..679d95e85070 +index 000000000000..0f8b59d6753c --- /dev/null -+++ b/include/dt-bindings/clock/spacemit-k1-clock.h -@@ -0,0 +1,223 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ ++++ b/include/dt-bindings/clock/spacemit,k1-syscon.h +@@ -0,0 +1,394 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* -+ * Copyright (c) 2022 Spacemit, Inc -+ */ -+ -+#ifndef _DT_BINDINGS_CLK_SPACEMIT_K1_H_ -+#define _DT_BINDINGS_CLK_SPACEMIT_K1_H_ -+ -+#define CLK_PLL2 0 -+#define CLK_PLL3 1 -+#define CLK_PLL1_D2 2 -+#define CLK_PLL1_D3 3 -+#define CLK_PLL1_D4 4 -+#define CLK_PLL1_D5 5 -+#define CLK_PLL1_D6 6 -+#define CLK_PLL1_D7 7 -+#define CLK_PLL1_D8 8 -+#define CLK_PLL1_D11 9 -+#define CLK_PLL1_D13 10 -+#define CLK_PLL1_D23 11 -+#define CLK_PLL1_D64 12 -+#define CLK_PLL1_D10_AUD 13 -+#define CLK_PLL1_D100_AUD 14 -+#define CLK_PLL2_D1 15 -+#define CLK_PLL2_D2 16 -+#define CLK_PLL2_D3 17 -+#define CLK_PLL2_D4 18 -+#define CLK_PLL2_D5 19 -+#define CLK_PLL2_D6 20 -+#define CLK_PLL2_D7 21 -+#define CLK_PLL2_D8 22 -+#define CLK_PLL3_D1 23 -+#define CLK_PLL3_D2 24 -+#define CLK_PLL3_D3 25 -+#define CLK_PLL3_D4 26 -+#define CLK_PLL3_D5 27 -+#define CLK_PLL3_D6 28 -+#define CLK_PLL3_D7 29 -+#define CLK_PLL3_D8 30 -+#define CLK_PLL1_307P2 31 -+#define CLK_PLL1_76P8 32 -+#define CLK_PLL1_61P44 33 -+#define CLK_PLL1_153P6 34 -+#define CLK_PLL1_102P4 35 -+#define CLK_PLL1_51P2 36 -+#define CLK_PLL1_51P2_AP 37 -+#define CLK_PLL1_57P6 38 -+#define CLK_PLL1_25P6 39 -+#define CLK_PLL1_12P8 40 -+#define CLK_PLL1_12P8_WDT 41 -+#define CLK_PLL1_6P4 42 -+#define CLK_PLL1_3P2 43 -+#define CLK_PLL1_1P6 44 -+#define CLK_PLL1_0P8 45 -+#define CLK_PLL1_351 46 -+#define CLK_PLL1_409P6 47 -+#define CLK_PLL1_204P8 48 -+#define CLK_PLL1_491 49 -+#define CLK_PLL1_245P76 50 -+#define CLK_PLL1_614 51 -+#define CLK_PLL1_47P26 52 -+#define CLK_PLL1_31P5 53 -+#define CLK_PLL1_819 54 -+#define CLK_PLL1_1228 55 -+#define CLK_SLOW_UART1 56 -+#define CLK_SLOW_UART2 57 -+#define CLK_UART1 58 -+#define CLK_UART2 59 -+#define CLK_UART3 60 -+#define CLK_UART4 61 -+#define CLK_UART5 62 -+#define CLK_UART6 63 -+#define CLK_UART7 64 -+#define CLK_UART8 65 -+#define CLK_UART9 66 -+#define CLK_GPIO 67 -+#define CLK_PWM0 68 -+#define CLK_PWM1 69 -+#define CLK_PWM2 70 -+#define CLK_PWM3 71 -+#define CLK_PWM4 72 -+#define CLK_PWM5 73 -+#define CLK_PWM6 74 -+#define CLK_PWM7 75 -+#define CLK_PWM8 76 -+#define CLK_PWM9 77 -+#define CLK_PWM10 78 -+#define CLK_PWM11 79 -+#define CLK_PWM12 80 -+#define CLK_PWM13 81 -+#define CLK_PWM14 82 -+#define CLK_PWM15 83 -+#define CLK_PWM16 84 -+#define CLK_PWM17 85 -+#define CLK_PWM18 86 -+#define CLK_PWM19 87 -+#define CLK_SSP3 88 -+#define CLK_RTC 89 -+#define CLK_TWSI0 90 -+#define CLK_TWSI1 91 -+#define CLK_TWSI2 92 -+#define CLK_TWSI4 93 -+#define CLK_TWSI5 94 -+#define CLK_TWSI6 95 -+#define CLK_TWSI7 96 -+#define CLK_TWSI8 97 -+#define CLK_TIMERS1 98 -+#define CLK_TIMERS2 99 -+#define CLK_AIB 100 -+#define CLK_ONEWIRE 101 -+#define CLK_SSPA0 102 -+#define CLK_SSPA1 103 -+#define CLK_DRO 104 -+#define CLK_IR 105 -+#define CLK_TSEN 106 -+#define CLK_IPC_AP2AUD 107 -+#define CLK_CAN0 108 -+#define CLK_CAN0_BUS 109 -+#define CLK_WDT 110 -+#define CLK_RIPC 111 -+#define CLK_JPG 112 -+#define CLK_JPF_4KAFBC 113 -+#define CLK_JPF_2KAFBC 114 -+#define CLK_CCIC2PHY 115 -+#define CLK_CCIC3PHY 116 -+#define CLK_CSI 117 -+#define CLK_CAMM0 118 -+#define CLK_CAMM1 119 -+#define CLK_CAMM2 120 -+#define CLK_ISP_CPP 121 -+#define CLK_ISP_BUS 122 -+#define CLK_ISP 123 -+#define CLK_DPU_MCLK 124 -+#define CLK_DPU_ESC 125 -+#define CLK_DPU_BIT 126 -+#define CLK_DPU_PXCLK 127 -+#define CLK_DPU_HCLK 128 -+#define CLK_DPU_SPI 129 -+#define CLK_DPU_SPI_HBUS 130 -+#define CLK_DPU_SPIBUS 131 -+#define CLK_SPU_SPI_ACLK 132 -+#define CLK_V2D 133 -+#define CLK_CCIC_4X 134 -+#define CLK_CCIC1PHY 135 -+#define CLK_SDH_AXI 136 -+#define CLK_SDH0 137 -+#define CLK_SDH1 138 -+#define CLK_SDH2 139 -+#define CLK_USB_P1 140 -+#define CLK_USB_AXI 141 -+#define CLK_USB30 142 -+#define CLK_QSPI 143 -+#define CLK_QSPI_BUS 144 -+#define CLK_DMA 145 -+#define CLK_AES 146 -+#define CLK_VPU 147 -+#define CLK_GPU 148 -+#define CLK_EMMC 149 -+#define CLK_EMMC_X 150 -+#define CLK_AUDIO 151 -+#define CLK_HDMI 152 -+#define CLK_CCI550 153 -+#define CLK_PMUA_ACLK 154 -+#define CLK_CPU_C0_HI 155 -+#define CLK_CPU_C0_CORE 156 -+#define CLK_CPU_C0_ACE 157 -+#define CLK_CPU_C0_TCM 158 -+#define CLK_CPU_C1_HI 159 -+#define CLK_CPU_C1_CORE 160 -+#define CLK_CPU_C1_ACE 161 -+#define CLK_PCIE0 162 -+#define CLK_PCIE1 163 -+#define CLK_PCIE2 164 -+#define CLK_EMAC0_BUS 165 -+#define CLK_EMAC0_PTP 166 -+#define CLK_EMAC1_BUS 167 -+#define CLK_EMAC1_PTP 168 -+#define CLK_SEC_UART1 169 -+#define CLK_SEC_SSP2 170 -+#define CLK_SEC_TWSI3 171 -+#define CLK_SEC_RTC 172 -+#define CLK_SEC_TIMERS0 173 -+#define CLK_SEC_KPC 174 -+#define CLK_SEC_GPIO 175 -+#define CLK_APB 176 -+#define CLK_PLL3_80 177 -+#define CLK_PLL3_40 178 -+#define CLK_PLL3_20 179 -+#define CLK_SLOW_UART 180 -+#define CLK_I2S_SYSCLK 181 -+#define CLK_I2S_BCLK 182 -+#define CLK_RCPU_HDMIAUDIO 183 -+#define CLK_RCPU_CAN 184 -+#define CLK_RCPU_CAN_BUS 185 -+#define CLK_RCPU_I2C0 186 -+#define CLK_RCPU_SSP0 187 -+#define CLK_RCPU_IR 188 -+#define CLK_RCPU_UART0 189 -+#define CLK_RCPU_UART1 190 -+#define CLK_DPLL1 191 -+#define CLK_DPLL2 192 -+#define CLK_DFC_LVL0 193 -+#define CLK_DFC_LVL1 194 -+#define CLK_DFC_LVL2 195 -+#define CLK_DFC_LVL3 196 -+#define CLK_DFC_LVL4 197 -+#define CLK_DFC_LVL5 198 -+#define CLK_DFC_LVL6 199 -+#define CLK_DFC_LVL7 200 -+#define CLK_DDR 201 -+#define CLK_RCPU2_PWM0 202 -+#define CLK_RCPU2_PWM1 203 -+#define CLK_RCPU2_PWM2 204 -+#define CLK_RCPU2_PWM3 205 -+#define CLK_RCPU2_PWM4 206 -+#define CLK_RCPU2_PWM5 207 -+#define CLK_RCPU2_PWM6 208 -+#define CLK_RCPU2_PWM7 209 -+#define CLK_RCPU2_PWM8 210 -+#define CLK_RCPU2_PWM9 211 -+#define CLK_MAX_NO 212 -+ -+#endif /* _DT_BINDINGS_CLK_SPACEMIT_K1_H_ */ ++ * Copyright (C) 2024-2025 Haylen Chu ++ */ ++ ++#ifndef _DT_BINDINGS_SPACEMIT_CCU_H_ ++#define _DT_BINDINGS_SPACEMIT_CCU_H_ ++ ++/* APBS (PLL) clocks */ ++#define CLK_PLL1 0 ++#define CLK_PLL2 1 ++#define CLK_PLL3 2 ++#define CLK_PLL1_D2 3 ++#define CLK_PLL1_D3 4 ++#define CLK_PLL1_D4 5 ++#define CLK_PLL1_D5 6 ++#define CLK_PLL1_D6 7 ++#define CLK_PLL1_D7 8 ++#define CLK_PLL1_D8 9 ++#define CLK_PLL1_D11 10 ++#define CLK_PLL1_D13 11 ++#define CLK_PLL1_D23 12 ++#define CLK_PLL1_D64 13 ++#define CLK_PLL1_D10_AUD 14 ++#define CLK_PLL1_D100_AUD 15 ++#define CLK_PLL2_D1 16 ++#define CLK_PLL2_D2 17 ++#define CLK_PLL2_D3 18 ++#define CLK_PLL2_D4 19 ++#define CLK_PLL2_D5 20 ++#define CLK_PLL2_D6 21 ++#define CLK_PLL2_D7 22 ++#define CLK_PLL2_D8 23 ++#define CLK_PLL3_D1 24 ++#define CLK_PLL3_D2 25 ++#define CLK_PLL3_D3 26 ++#define CLK_PLL3_D4 27 ++#define CLK_PLL3_D5 28 ++#define CLK_PLL3_D6 29 ++#define CLK_PLL3_D7 30 ++#define CLK_PLL3_D8 31 ++#define CLK_PLL3_80 32 ++#define CLK_PLL3_40 33 ++#define CLK_PLL3_20 34 ++ ++/* MPMU clocks */ ++#define CLK_PLL1_307P2 0 ++#define CLK_PLL1_76P8 1 ++#define CLK_PLL1_61P44 2 ++#define CLK_PLL1_153P6 3 ++#define CLK_PLL1_102P4 4 ++#define CLK_PLL1_51P2 5 ++#define CLK_PLL1_51P2_AP 6 ++#define CLK_PLL1_57P6 7 ++#define CLK_PLL1_25P6 8 ++#define CLK_PLL1_12P8 9 ++#define CLK_PLL1_12P8_WDT 10 ++#define CLK_PLL1_6P4 11 ++#define CLK_PLL1_3P2 12 ++#define CLK_PLL1_1P6 13 ++#define CLK_PLL1_0P8 14 ++#define CLK_PLL1_409P6 15 ++#define CLK_PLL1_204P8 16 ++#define CLK_PLL1_491 17 ++#define CLK_PLL1_245P76 18 ++#define CLK_PLL1_614 19 ++#define CLK_PLL1_47P26 20 ++#define CLK_PLL1_31P5 21 ++#define CLK_PLL1_819 22 ++#define CLK_PLL1_1228 23 ++#define CLK_SLOW_UART 24 ++#define CLK_SLOW_UART1 25 ++#define CLK_SLOW_UART2 26 ++#define CLK_WDT 27 ++#define CLK_RIPC 28 ++#define CLK_I2S_SYSCLK 29 ++#define CLK_I2S_BCLK 30 ++#define CLK_APB 31 ++#define CLK_WDT_BUS 32 ++#define CLK_I2S_153P6 33 ++#define CLK_I2S_153P6_BASE 34 ++#define CLK_I2S_SYSCLK_SRC 35 ++#define CLK_I2S_BCLK_FACTOR 36 ++ ++/* MPMU resets */ ++#define RESET_WDT 0 ++ ++/* APBC clocks */ ++#define CLK_UART0 0 ++#define CLK_UART2 1 ++#define CLK_UART3 2 ++#define CLK_UART4 3 ++#define CLK_UART5 4 ++#define CLK_UART6 5 ++#define CLK_UART7 6 ++#define CLK_UART8 7 ++#define CLK_UART9 8 ++#define CLK_GPIO 9 ++#define CLK_PWM0 10 ++#define CLK_PWM1 11 ++#define CLK_PWM2 12 ++#define CLK_PWM3 13 ++#define CLK_PWM4 14 ++#define CLK_PWM5 15 ++#define CLK_PWM6 16 ++#define CLK_PWM7 17 ++#define CLK_PWM8 18 ++#define CLK_PWM9 19 ++#define CLK_PWM10 20 ++#define CLK_PWM11 21 ++#define CLK_PWM12 22 ++#define CLK_PWM13 23 ++#define CLK_PWM14 24 ++#define CLK_PWM15 25 ++#define CLK_PWM16 26 ++#define CLK_PWM17 27 ++#define CLK_PWM18 28 ++#define CLK_PWM19 29 ++#define CLK_SSP3 30 ++#define CLK_RTC 31 ++#define CLK_TWSI0 32 ++#define CLK_TWSI1 33 ++#define CLK_TWSI2 34 ++#define CLK_TWSI4 35 ++#define CLK_TWSI5 36 ++#define CLK_TWSI6 37 ++#define CLK_TWSI7 38 ++#define CLK_TWSI8 39 ++#define CLK_TIMERS1 40 ++#define CLK_TIMERS2 41 ++#define CLK_AIB 42 ++#define CLK_ONEWIRE 43 ++#define CLK_SSPA0 44 ++#define CLK_SSPA1 45 ++#define CLK_DRO 46 ++#define CLK_IR 47 ++#define CLK_TSEN 48 ++#define CLK_IPC_AP2AUD 49 ++#define CLK_CAN0 50 ++#define CLK_CAN0_BUS 51 ++#define CLK_UART0_BUS 52 ++#define CLK_UART2_BUS 53 ++#define CLK_UART3_BUS 54 ++#define CLK_UART4_BUS 55 ++#define CLK_UART5_BUS 56 ++#define CLK_UART6_BUS 57 ++#define CLK_UART7_BUS 58 ++#define CLK_UART8_BUS 59 ++#define CLK_UART9_BUS 60 ++#define CLK_GPIO_BUS 61 ++#define CLK_PWM0_BUS 62 ++#define CLK_PWM1_BUS 63 ++#define CLK_PWM2_BUS 64 ++#define CLK_PWM3_BUS 65 ++#define CLK_PWM4_BUS 66 ++#define CLK_PWM5_BUS 67 ++#define CLK_PWM6_BUS 68 ++#define CLK_PWM7_BUS 69 ++#define CLK_PWM8_BUS 70 ++#define CLK_PWM9_BUS 71 ++#define CLK_PWM10_BUS 72 ++#define CLK_PWM11_BUS 73 ++#define CLK_PWM12_BUS 74 ++#define CLK_PWM13_BUS 75 ++#define CLK_PWM14_BUS 76 ++#define CLK_PWM15_BUS 77 ++#define CLK_PWM16_BUS 78 ++#define CLK_PWM17_BUS 79 ++#define CLK_PWM18_BUS 80 ++#define CLK_PWM19_BUS 81 ++#define CLK_SSP3_BUS 82 ++#define CLK_RTC_BUS 83 ++#define CLK_TWSI0_BUS 84 ++#define CLK_TWSI1_BUS 85 ++#define CLK_TWSI2_BUS 86 ++#define CLK_TWSI4_BUS 87 ++#define CLK_TWSI5_BUS 88 ++#define CLK_TWSI6_BUS 89 ++#define CLK_TWSI7_BUS 90 ++#define CLK_TWSI8_BUS 91 ++#define CLK_TIMERS1_BUS 92 ++#define CLK_TIMERS2_BUS 93 ++#define CLK_AIB_BUS 94 ++#define CLK_ONEWIRE_BUS 95 ++#define CLK_SSPA0_BUS 96 ++#define CLK_SSPA1_BUS 97 ++#define CLK_TSEN_BUS 98 ++#define CLK_IPC_AP2AUD_BUS 99 ++#define CLK_SSPA0_I2S_BCLK 100 ++#define CLK_SSPA1_I2S_BCLK 101 ++ ++/* APBC resets */ ++#define RESET_UART0 0 ++#define RESET_UART2 1 ++#define RESET_UART3 2 ++#define RESET_UART4 3 ++#define RESET_UART5 4 ++#define RESET_UART6 5 ++#define RESET_UART7 6 ++#define RESET_UART8 7 ++#define RESET_UART9 8 ++#define RESET_GPIO 9 ++#define RESET_PWM0 10 ++#define RESET_PWM1 11 ++#define RESET_PWM2 12 ++#define RESET_PWM3 13 ++#define RESET_PWM4 14 ++#define RESET_PWM5 15 ++#define RESET_PWM6 16 ++#define RESET_PWM7 17 ++#define RESET_PWM8 18 ++#define RESET_PWM9 19 ++#define RESET_PWM10 20 ++#define RESET_PWM11 21 ++#define RESET_PWM12 22 ++#define RESET_PWM13 23 ++#define RESET_PWM14 24 ++#define RESET_PWM15 25 ++#define RESET_PWM16 26 ++#define RESET_PWM17 27 ++#define RESET_PWM18 28 ++#define RESET_PWM19 29 ++#define RESET_SSP3 30 ++#define RESET_RTC 31 ++#define RESET_TWSI0 32 ++#define RESET_TWSI1 33 ++#define RESET_TWSI2 34 ++#define RESET_TWSI4 35 ++#define RESET_TWSI5 36 ++#define RESET_TWSI6 37 ++#define RESET_TWSI7 38 ++#define RESET_TWSI8 39 ++#define RESET_TIMERS1 40 ++#define RESET_TIMERS2 41 ++#define RESET_AIB 42 ++#define RESET_ONEWIRE 43 ++#define RESET_SSPA0 44 ++#define RESET_SSPA1 45 ++#define RESET_DRO 46 ++#define RESET_IR 47 ++#define RESET_TSEN 48 ++#define RESET_IPC_AP2AUD 49 ++#define RESET_CAN0 50 ++ ++/* APMU clocks */ ++#define CLK_CCI550 0 ++#define CLK_CPU_C0_HI 1 ++#define CLK_CPU_C0_CORE 2 ++#define CLK_CPU_C0_ACE 3 ++#define CLK_CPU_C0_TCM 4 ++#define CLK_CPU_C1_HI 5 ++#define CLK_CPU_C1_CORE 6 ++#define CLK_CPU_C1_ACE 7 ++#define CLK_CCIC_4X 8 ++#define CLK_CCIC1PHY 9 ++#define CLK_SDH_AXI 10 ++#define CLK_SDH0 11 ++#define CLK_SDH1 12 ++#define CLK_SDH2 13 ++#define CLK_USB_P1 14 ++#define CLK_USB_AXI 15 ++#define CLK_USB30 16 ++#define CLK_QSPI 17 ++#define CLK_QSPI_BUS 18 ++#define CLK_DMA 19 ++#define CLK_AES 20 ++#define CLK_VPU 21 ++#define CLK_GPU 22 ++#define CLK_EMMC 23 ++#define CLK_EMMC_X 24 ++#define CLK_AUDIO 25 ++#define CLK_HDMI 26 ++#define CLK_PMUA_ACLK 27 ++#define CLK_PCIE0_MASTER 28 ++#define CLK_PCIE0_SLAVE 29 ++#define CLK_PCIE0_DBI 30 ++#define CLK_PCIE1_MASTER 31 ++#define CLK_PCIE1_SLAVE 32 ++#define CLK_PCIE1_DBI 33 ++#define CLK_PCIE2_MASTER 34 ++#define CLK_PCIE2_SLAVE 35 ++#define CLK_PCIE2_DBI 36 ++#define CLK_EMAC0_BUS 37 ++#define CLK_EMAC0_PTP 38 ++#define CLK_EMAC1_BUS 39 ++#define CLK_EMAC1_PTP 40 ++#define CLK_JPG 41 ++#define CLK_CCIC2PHY 42 ++#define CLK_CCIC3PHY 43 ++#define CLK_CSI 44 ++#define CLK_CAMM0 45 ++#define CLK_CAMM1 46 ++#define CLK_CAMM2 47 ++#define CLK_ISP_CPP 48 ++#define CLK_ISP_BUS 49 ++#define CLK_ISP 50 ++#define CLK_DPU_MCLK 51 ++#define CLK_DPU_ESC 52 ++#define CLK_DPU_BIT 53 ++#define CLK_DPU_PXCLK 54 ++#define CLK_DPU_HCLK 55 ++#define CLK_DPU_SPI 56 ++#define CLK_DPU_SPI_HBUS 57 ++#define CLK_DPU_SPIBUS 58 ++#define CLK_DPU_SPI_ACLK 59 ++#define CLK_V2D 60 ++#define CLK_EMMC_BUS 61 ++ ++/* APMU resets */ ++#define RESET_CCIC_4X 0 ++#define RESET_CCIC1_PHY 1 ++#define RESET_SDH_AXI 2 ++#define RESET_SDH0 3 ++#define RESET_SDH1 4 ++#define RESET_SDH2 5 ++#define RESET_USBP1_AXI 6 ++#define RESET_USB_AXI 7 ++#define RESET_USB30_AHB 8 ++#define RESET_USB30_VCC 9 ++#define RESET_USB30_PHY 10 ++#define RESET_QSPI 11 ++#define RESET_QSPI_BUS 12 ++#define RESET_DMA 13 ++#define RESET_AES 14 ++#define RESET_VPU 15 ++#define RESET_GPU 16 ++#define RESET_EMMC 17 ++#define RESET_EMMC_X 18 ++#define RESET_AUDIO_SYS 19 ++#define RESET_AUDIO_MCU 20 ++#define RESET_AUDIO_APMU 21 ++#define RESET_HDMI 22 ++#define RESET_PCIE0_MASTER 23 ++#define RESET_PCIE0_SLAVE 24 ++#define RESET_PCIE0_DBI 25 ++#define RESET_PCIE0_GLOBAL 26 ++#define RESET_PCIE1_MASTER 27 ++#define RESET_PCIE1_SLAVE 28 ++#define RESET_PCIE1_DBI 29 ++#define RESET_PCIE1_GLOBAL 30 ++#define RESET_PCIE2_MASTER 31 ++#define RESET_PCIE2_SLAVE 32 ++#define RESET_PCIE2_DBI 33 ++#define RESET_PCIE2_GLOBAL 34 ++#define RESET_EMAC0 35 ++#define RESET_EMAC1 36 ++#define RESET_JPG 37 ++#define RESET_CCIC2PHY 38 ++#define RESET_CCIC3PHY 39 ++#define RESET_CSI 40 ++#define RESET_ISP_CPP 41 ++#define RESET_ISP_BUS 42 ++#define RESET_ISP 43 ++#define RESET_ISP_CI 44 ++#define RESET_DPU_MCLK 45 ++#define RESET_DPU_ESC 46 ++#define RESET_DPU_HCLK 47 ++#define RESET_DPU_SPIBUS 48 ++#define RESET_DPU_SPI_HBUS 49 ++#define RESET_V2D 50 ++#define RESET_MIPI 51 ++#define RESET_MC 52 ++ ++/* RCPU resets */ ++#define RESET_RCPU_SSP0 0 ++#define RESET_RCPU_I2C0 1 ++#define RESET_RCPU_UART1 2 ++#define RESET_RCPU_IR 3 ++#define RESET_RCPU_CAN 4 ++#define RESET_RCPU_UART0 5 ++#define RESET_RCPU_HDMI_AUDIO 6 ++ ++/* RCPU2 resets */ ++#define RESET_RCPU2_PWM0 0 ++#define RESET_RCPU2_PWM1 1 ++#define RESET_RCPU2_PWM2 2 ++#define RESET_RCPU2_PWM3 3 ++#define RESET_RCPU2_PWM4 4 ++#define RESET_RCPU2_PWM5 5 ++#define RESET_RCPU2_PWM6 6 ++#define RESET_RCPU2_PWM7 7 ++#define RESET_RCPU2_PWM8 8 ++#define RESET_RCPU2_PWM9 9 ++ ++/* APBC2 resets */ ++#define RESET_APBC2_UART1 0 ++#define RESET_APBC2_SSP2 1 ++#define RESET_APBC2_TWSI3 2 ++#define RESET_APBC2_RTC 3 ++#define RESET_APBC2_TIMERS0 4 ++#define RESET_APBC2_KPC 5 ++#define RESET_APBC2_GPIO 6 ++ ++#endif /* _DT_BINDINGS_SPACEMIT_CCU_H_ */ +diff --git a/include/dt-bindings/clock/spacemit,k3-syscon.h b/include/dt-bindings/clock/spacemit,k3-syscon.h +new file mode 100644 +index 000000000000..36662aa802dd +--- /dev/null ++++ b/include/dt-bindings/clock/spacemit,k3-syscon.h +@@ -0,0 +1,746 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++/* ++ * Copyright (c) 2025 SpacemiT Technology Co. Ltd ++ */ ++ ++#ifndef _DT_BINDINGS_SPACEMIT_CCU_K3_H_ ++#define _DT_BINDINGS_SPACEMIT_CCU_K3_H_ ++ ++/* APBS (PLL) clocks */ ++#define CLK_PLL1 0 ++#define CLK_PLL2 1 ++#define CLK_PLL3 2 ++#define CLK_PLL4 3 ++#define CLK_PLL5 4 ++#define CLK_PLL6 5 ++#define CLK_PLL7 6 ++#define CLK_PLL8 7 ++#define CLK_PLL1_D2 8 ++#define CLK_PLL1_D3 9 ++#define CLK_PLL1_D4 10 ++#define CLK_PLL1_D5 11 ++#define CLK_PLL1_D6 12 ++#define CLK_PLL1_D7 13 ++#define CLK_PLL1_D8 14 ++#define CLK_PLL1_DX 15 ++#define CLK_PLL1_D64 16 ++#define CLK_PLL1_D10_AUD 17 ++#define CLK_PLL1_D100_AUD 18 ++#define CLK_PLL2_D1 19 ++#define CLK_PLL2_D2 20 ++#define CLK_PLL2_D3 21 ++#define CLK_PLL2_D4 22 ++#define CLK_PLL2_D5 23 ++#define CLK_PLL2_D6 24 ++#define CLK_PLL2_D7 25 ++#define CLK_PLL2_D8 26 ++#define CLK_PLL2_66 27 ++#define CLK_PLL2_33 28 ++#define CLK_PLL2_50 29 ++#define CLK_PLL2_25 30 ++#define CLK_PLL2_20 31 ++#define CLK_PLL2_D24_125 32 ++#define CLK_PLL2_D120_25 33 ++#define CLK_PLL3_D1 34 ++#define CLK_PLL3_D2 35 ++#define CLK_PLL3_D3 36 ++#define CLK_PLL3_D4 37 ++#define CLK_PLL3_D5 38 ++#define CLK_PLL3_D6 39 ++#define CLK_PLL3_D7 40 ++#define CLK_PLL3_D8 41 ++#define CLK_PLL4_D1 42 ++#define CLK_PLL4_D2 43 ++#define CLK_PLL4_D3 44 ++#define CLK_PLL4_D4 45 ++#define CLK_PLL4_D5 46 ++#define CLK_PLL4_D6 47 ++#define CLK_PLL4_D7 48 ++#define CLK_PLL4_D8 49 ++#define CLK_PLL5_D1 50 ++#define CLK_PLL5_D2 51 ++#define CLK_PLL5_D3 52 ++#define CLK_PLL5_D4 53 ++#define CLK_PLL5_D5 54 ++#define CLK_PLL5_D6 55 ++#define CLK_PLL5_D7 56 ++#define CLK_PLL5_D8 57 ++#define CLK_PLL6_D1 58 ++#define CLK_PLL6_D2 59 ++#define CLK_PLL6_D3 60 ++#define CLK_PLL6_D4 61 ++#define CLK_PLL6_D5 62 ++#define CLK_PLL6_D6 63 ++#define CLK_PLL6_D7 64 ++#define CLK_PLL6_D8 65 ++#define CLK_PLL6_80 66 ++#define CLK_PLL6_40 67 ++#define CLK_PLL6_20 68 ++#define CLK_PLL7_D1 69 ++#define CLK_PLL7_D2 70 ++#define CLK_PLL7_D3 71 ++#define CLK_PLL7_D4 72 ++#define CLK_PLL7_D5 73 ++#define CLK_PLL7_D6 74 ++#define CLK_PLL7_D7 75 ++#define CLK_PLL7_D8 76 ++#define CLK_PLL8_D1 77 ++#define CLK_PLL8_D2 78 ++#define CLK_PLL8_D3 79 ++#define CLK_PLL8_D4 80 ++#define CLK_PLL8_D5 81 ++#define CLK_PLL8_D6 82 ++#define CLK_PLL8_D7 83 ++#define CLK_PLL8_D8 84 ++ ++/* MPMU clocks */ ++#define CLK_MPMU_PLL1_307P2 0 ++#define CLK_MPMU_PLL1_76P8 1 ++#define CLK_MPMU_PLL1_61P44 2 ++#define CLK_MPMU_PLL1_153P6 3 ++#define CLK_MPMU_PLL1_102P4 4 ++#define CLK_MPMU_PLL1_51P2 5 ++#define CLK_MPMU_PLL1_51P2_AP 6 ++#define CLK_MPMU_PLL1_57P6 7 ++#define CLK_MPMU_PLL1_25P6 8 ++#define CLK_MPMU_PLL1_12P8 9 ++#define CLK_MPMU_PLL1_12P8_WDT 10 ++#define CLK_MPMU_PLL1_6P4 11 ++#define CLK_MPMU_PLL1_3P2 12 ++#define CLK_MPMU_PLL1_1P6 13 ++#define CLK_MPMU_PLL1_0P8 14 ++#define CLK_MPMU_PLL1_409P6 15 ++#define CLK_MPMU_PLL1_204P8 16 ++#define CLK_MPMU_PLL1_491 17 ++#define CLK_MPMU_PLL1_245P76 18 ++#define CLK_MPMU_PLL1_614 19 ++#define CLK_MPMU_PLL1_47P26 20 ++#define CLK_MPMU_PLL1_31P5 21 ++#define CLK_MPMU_PLL1_819 22 ++#define CLK_MPMU_PLL1_1228 23 ++#define CLK_MPMU_APB 24 ++#define CLK_MPMU_SLOW_UART 25 ++#define CLK_MPMU_SLOW_UART1 26 ++#define CLK_MPMU_SLOW_UART2 27 ++#define CLK_MPMU_WDT 28 ++#define CLK_MPMU_WDT_BUS 29 ++#define CLK_MPMU_RIPC 30 ++#define CLK_MPMU_I2S_153P6 31 ++#define CLK_MPMU_I2S_153P6_BASE 32 ++#define CLK_MPMU_I2S_SYSCLK_SRC 33 ++#define CLK_MPMU_I2S1_SYSCLK 34 ++#define CLK_MPMU_I2S_BCLK_FACTOR 35 ++#define CLK_MPMU_I2S_BCLK 36 ++#define CLK_MPMU_I2S0_SYSCLK_SEL 37 ++#define CLK_MPMU_I2S2_SYSCLK_SEL 38 ++#define CLK_MPMU_I2S3_SYSCLK_SEL 39 ++#define CLK_MPMU_I2S4_SYSCLK_SEL 40 ++#define CLK_MPMU_I2S5_SYSCLK_SEL 41 ++#define CLK_MPMU_I2S0_SYSCLK_DIV 42 ++#define CLK_MPMU_I2S2_SYSCLK_DIV 43 ++#define CLK_MPMU_I2S3_SYSCLK_DIV 44 ++#define CLK_MPMU_I2S4_SYSCLK_DIV 45 ++#define CLK_MPMU_I2S5_SYSCLK_DIV 46 ++#define CLK_MPMU_I2S0_SYSCLK 47 ++#define CLK_MPMU_I2S2_SYSCLK 48 ++#define CLK_MPMU_I2S3_SYSCLK 49 ++#define CLK_MPMU_I2S4_SYSCLK 50 ++#define CLK_MPMU_I2S5_SYSCLK 51 ++ ++/* MPMU resets */ ++#define RESET_MPMU_WDT 0 ++#define RESET_MPMU_RIPC 1 ++ ++/* APBC clocks */ ++#define CLK_APBC_UART0 0 ++#define CLK_APBC_UART2 1 ++#define CLK_APBC_UART3 2 ++#define CLK_APBC_UART4 3 ++#define CLK_APBC_UART5 4 ++#define CLK_APBC_UART6 5 ++#define CLK_APBC_UART7 6 ++#define CLK_APBC_UART8 7 ++#define CLK_APBC_UART9 8 ++#define CLK_APBC_UART10 9 ++#define CLK_APBC_UART0_BUS 10 ++#define CLK_APBC_UART2_BUS 11 ++#define CLK_APBC_UART3_BUS 12 ++#define CLK_APBC_UART4_BUS 13 ++#define CLK_APBC_UART5_BUS 14 ++#define CLK_APBC_UART6_BUS 15 ++#define CLK_APBC_UART7_BUS 16 ++#define CLK_APBC_UART8_BUS 17 ++#define CLK_APBC_UART9_BUS 18 ++#define CLK_APBC_UART10_BUS 19 ++#define CLK_APBC_GPIO 20 ++#define CLK_APBC_GPIO_BUS 21 ++#define CLK_APBC_PWM0 22 ++#define CLK_APBC_PWM1 23 ++#define CLK_APBC_PWM2 24 ++#define CLK_APBC_PWM3 25 ++#define CLK_APBC_PWM4 26 ++#define CLK_APBC_PWM5 27 ++#define CLK_APBC_PWM6 28 ++#define CLK_APBC_PWM7 29 ++#define CLK_APBC_PWM8 30 ++#define CLK_APBC_PWM9 31 ++#define CLK_APBC_PWM10 32 ++#define CLK_APBC_PWM11 33 ++#define CLK_APBC_PWM12 34 ++#define CLK_APBC_PWM13 35 ++#define CLK_APBC_PWM14 36 ++#define CLK_APBC_PWM15 37 ++#define CLK_APBC_PWM16 38 ++#define CLK_APBC_PWM17 39 ++#define CLK_APBC_PWM18 40 ++#define CLK_APBC_PWM19 41 ++#define CLK_APBC_PWM0_BUS 42 ++#define CLK_APBC_PWM1_BUS 43 ++#define CLK_APBC_PWM2_BUS 44 ++#define CLK_APBC_PWM3_BUS 45 ++#define CLK_APBC_PWM4_BUS 46 ++#define CLK_APBC_PWM5_BUS 47 ++#define CLK_APBC_PWM6_BUS 48 ++#define CLK_APBC_PWM7_BUS 49 ++#define CLK_APBC_PWM8_BUS 50 ++#define CLK_APBC_PWM9_BUS 51 ++#define CLK_APBC_PWM10_BUS 52 ++#define CLK_APBC_PWM11_BUS 53 ++#define CLK_APBC_PWM12_BUS 54 ++#define CLK_APBC_PWM13_BUS 55 ++#define CLK_APBC_PWM14_BUS 56 ++#define CLK_APBC_PWM15_BUS 57 ++#define CLK_APBC_PWM16_BUS 58 ++#define CLK_APBC_PWM17_BUS 59 ++#define CLK_APBC_PWM18_BUS 60 ++#define CLK_APBC_PWM19_BUS 61 ++#define CLK_APBC_SPI0_I2S_BCLK 62 ++#define CLK_APBC_SPI1_I2S_BCLK 63 ++#define CLK_APBC_SPI3_I2S_BCLK 64 ++#define CLK_APBC_SPI0 65 ++#define CLK_APBC_SPI1 66 ++#define CLK_APBC_SPI3 67 ++#define CLK_APBC_SPI0_BUS 68 ++#define CLK_APBC_SPI1_BUS 69 ++#define CLK_APBC_SPI3_BUS 70 ++#define CLK_APBC_RTC 71 ++#define CLK_APBC_RTC_BUS 72 ++#define CLK_APBC_TWSI0 73 ++#define CLK_APBC_TWSI1 74 ++#define CLK_APBC_TWSI2 75 ++#define CLK_APBC_TWSI4 76 ++#define CLK_APBC_TWSI5 77 ++#define CLK_APBC_TWSI6 78 ++#define CLK_APBC_TWSI8 79 ++#define CLK_APBC_TWSI0_BUS 80 ++#define CLK_APBC_TWSI1_BUS 81 ++#define CLK_APBC_TWSI2_BUS 82 ++#define CLK_APBC_TWSI4_BUS 83 ++#define CLK_APBC_TWSI5_BUS 84 ++#define CLK_APBC_TWSI6_BUS 85 ++#define CLK_APBC_TWSI8_BUS 86 ++#define CLK_APBC_TIMERS0 87 ++#define CLK_APBC_TIMERS1 88 ++#define CLK_APBC_TIMERS2 89 ++#define CLK_APBC_TIMERS3 90 ++#define CLK_APBC_TIMERS4 91 ++#define CLK_APBC_TIMERS5 92 ++#define CLK_APBC_TIMERS6 93 ++#define CLK_APBC_TIMERS7 94 ++#define CLK_APBC_TIMERS0_BUS 95 ++#define CLK_APBC_TIMERS1_BUS 96 ++#define CLK_APBC_TIMERS2_BUS 97 ++#define CLK_APBC_TIMERS3_BUS 98 ++#define CLK_APBC_TIMERS4_BUS 99 ++#define CLK_APBC_TIMERS5_BUS 100 ++#define CLK_APBC_TIMERS6_BUS 101 ++#define CLK_APBC_TIMERS7_BUS 102 ++#define CLK_APBC_AIB 103 ++#define CLK_APBC_AIB_BUS 104 ++#define CLK_APBC_ONEWIRE 105 ++#define CLK_APBC_ONEWIRE_BUS 106 ++#define CLK_APBC_I2S0_BCLK 107 ++#define CLK_APBC_I2S1_BCLK 108 ++#define CLK_APBC_I2S2_BCLK 109 ++#define CLK_APBC_I2S3_BCLK 110 ++#define CLK_APBC_I2S4_BCLK 111 ++#define CLK_APBC_I2S5_BCLK 112 ++#define CLK_APBC_I2S0 113 ++#define CLK_APBC_I2S1 114 ++#define CLK_APBC_I2S2 115 ++#define CLK_APBC_I2S3 116 ++#define CLK_APBC_I2S4 117 ++#define CLK_APBC_I2S5 118 ++#define CLK_APBC_I2S0_BUS 119 ++#define CLK_APBC_I2S1_BUS 120 ++#define CLK_APBC_I2S2_BUS 121 ++#define CLK_APBC_I2S3_BUS 122 ++#define CLK_APBC_I2S4_BUS 123 ++#define CLK_APBC_I2S5_BUS 124 ++#define CLK_APBC_DRO 125 ++#define CLK_APBC_IR0 126 ++#define CLK_APBC_IR1 127 ++#define CLK_APBC_TSEN 128 ++#define CLK_APBC_TSEN_BUS 129 ++#define CLK_APBC_IPC_AP2RCPU 130 ++#define CLK_APBC_IPC_AP2RCPU_BUS 131 ++#define CLK_APBC_CAN0 132 ++#define CLK_APBC_CAN1 133 ++#define CLK_APBC_CAN2 134 ++#define CLK_APBC_CAN3 135 ++#define CLK_APBC_CAN4 136 ++#define CLK_APBC_CAN0_BUS 137 ++#define CLK_APBC_CAN1_BUS 138 ++#define CLK_APBC_CAN2_BUS 139 ++#define CLK_APBC_CAN3_BUS 140 ++#define CLK_APBC_CAN4_BUS 141 ++ ++/* APBC resets */ ++#define RESET_APBC_UART0 0 ++#define RESET_APBC_UART2 1 ++#define RESET_APBC_UART3 2 ++#define RESET_APBC_UART4 3 ++#define RESET_APBC_UART5 4 ++#define RESET_APBC_UART6 5 ++#define RESET_APBC_UART7 6 ++#define RESET_APBC_UART8 7 ++#define RESET_APBC_UART9 8 ++#define RESET_APBC_UART10 9 ++#define RESET_APBC_GPIO 10 ++#define RESET_APBC_PWM0 11 ++#define RESET_APBC_PWM1 12 ++#define RESET_APBC_PWM2 13 ++#define RESET_APBC_PWM3 14 ++#define RESET_APBC_PWM4 15 ++#define RESET_APBC_PWM5 16 ++#define RESET_APBC_PWM6 17 ++#define RESET_APBC_PWM7 18 ++#define RESET_APBC_PWM8 19 ++#define RESET_APBC_PWM9 20 ++#define RESET_APBC_PWM10 21 ++#define RESET_APBC_PWM11 22 ++#define RESET_APBC_PWM12 23 ++#define RESET_APBC_PWM13 24 ++#define RESET_APBC_PWM14 25 ++#define RESET_APBC_PWM15 26 ++#define RESET_APBC_PWM16 27 ++#define RESET_APBC_PWM17 28 ++#define RESET_APBC_PWM18 29 ++#define RESET_APBC_PWM19 30 ++#define RESET_APBC_SPI0 31 ++#define RESET_APBC_SPI1 32 ++#define RESET_APBC_SPI3 33 ++#define RESET_APBC_RTC 34 ++#define RESET_APBC_TWSI0 35 ++#define RESET_APBC_TWSI1 36 ++#define RESET_APBC_TWSI2 37 ++#define RESET_APBC_TWSI4 38 ++#define RESET_APBC_TWSI5 39 ++#define RESET_APBC_TWSI6 40 ++#define RESET_APBC_TWSI8 41 ++#define RESET_APBC_TIMERS0 42 ++#define RESET_APBC_TIMERS1 43 ++#define RESET_APBC_TIMERS2 44 ++#define RESET_APBC_TIMERS3 45 ++#define RESET_APBC_TIMERS4 46 ++#define RESET_APBC_TIMERS5 47 ++#define RESET_APBC_TIMERS6 48 ++#define RESET_APBC_TIMERS7 49 ++#define RESET_APBC_AIB 50 ++#define RESET_APBC_ONEWIRE 51 ++#define RESET_APBC_I2S0 52 ++#define RESET_APBC_I2S1 53 ++#define RESET_APBC_I2S2 54 ++#define RESET_APBC_I2S3 55 ++#define RESET_APBC_I2S4 56 ++#define RESET_APBC_I2S5 57 ++#define RESET_APBC_DRO 58 ++#define RESET_APBC_IR0 59 ++#define RESET_APBC_IR1 59 ++#define RESET_APBC_TSEN 60 ++#define RESET_IPC_AP2AUD 61 ++#define RESET_APBC_CAN0 62 ++#define RESET_APBC_CAN1 63 ++#define RESET_APBC_CAN2 64 ++#define RESET_APBC_CAN3 65 ++#define RESET_APBC_CAN4 66 ++ ++/* APMU clocks */ ++#define CLK_APMU_AXICLK 0 ++#define CLK_APMU_CCI550 1 ++#define CLK_APMU_CPU_C0_CORE 2 ++#define CLK_APMU_CPU_C1_CORE 3 ++#define CLK_APMU_CPU_C2_CORE 4 ++#define CLK_APMU_CPU_C3_CORE 5 ++#define CLK_APMU_CCIC2PHY 6 ++#define CLK_APMU_CCIC3PHY 7 ++#define CLK_APMU_CSI 8 ++#define CLK_APMU_ISP_BUS 9 ++#define CLK_APMU_D1P_1228P8 10 ++#define CLK_APMU_D1P_819P2 11 ++#define CLK_APMU_D1P_614P4 12 ++#define CLK_APMU_D1P_491P52 13 ++#define CLK_APMU_D1P_409P6 14 ++#define CLK_APMU_D1P_307P2 15 ++#define CLK_APMU_D1P_245P76 16 ++#define CLK_APMU_V2D 17 ++#define CLK_APMU_DSI_ESC 18 ++#define CLK_APMU_LCD_HCLK 19 ++#define CLK_APMU_LCD_DSC 20 ++#define CLK_APMU_LCD_PXCLK 21 ++#define CLK_APMU_LCD_MCLK 22 ++#define CLK_APMU_CCIC_4X 23 ++#define CLK_APMU_CCIC1PHY 24 ++#define CLK_APMU_SC2_HCLK 25 ++#define CLK_APMU_SDH_AXI 26 ++#define CLK_APMU_SDH0 27 ++#define CLK_APMU_SDH1 28 ++#define CLK_APMU_SDH2 29 ++#define CLK_APMU_USB2_BUS 30 ++#define CLK_APMU_USB3_PORTA_BUS 31 ++#define CLK_APMU_USB3_PORTB_BUS 32 ++#define CLK_APMU_USB3_PORTC_BUS 33 ++#define CLK_APMU_USB3_PORTD_BUS 34 ++#define CLK_APMU_QSPI 35 ++#define CLK_APMU_QSPI_BUS 36 ++#define CLK_APMU_DMA 37 ++#define CLK_APMU_AES_WTM 38 ++#define CLK_APMU_VPU 39 ++#define CLK_APMU_DTC 40 ++#define CLK_APMU_GPU 41 ++#define CLK_APMU_MC_AHB 42 ++#define CLK_APMU_TOP_DCLK 43 ++#define CLK_APMU_UCIE 44 ++#define CLK_APMU_UCIE_SBCLK 45 ++#define CLK_APMU_RCPU 46 ++#define CLK_APMU_DSI4LN2_DSI_ESC 47 ++#define CLK_APMU_DSI4LN2_LCD_DSC 48 ++#define CLK_APMU_DSI4LN2_LCD_PXCLK 49 ++#define CLK_APMU_DSI4LN2_LCD_MCLK 50 ++#define CLK_APMU_DSI4LN2_DPU_ACLK 51 ++#define CLK_APMU_DPU_ACLK 52 ++#define CLK_APMU_UFS_ACLK 53 ++#define CLK_APMU_EDP0_PXCLK 54 ++#define CLK_APMU_EDP1_PXCLK 55 ++#define CLK_APMU_PCIE_PORTA_MSTE 56 ++#define CLK_APMU_PCIE_PORTA_SLV 57 ++#define CLK_APMU_PCIE_PORTB_MSTE 58 ++#define CLK_APMU_PCIE_PORTB_SLV 59 ++#define CLK_APMU_PCIE_PORTC_MSTE 60 ++#define CLK_APMU_PCIE_PORTC_SLV 61 ++#define CLK_APMU_PCIE_PORTD_MSTE 62 ++#define CLK_APMU_PCIE_PORTD_SLV 63 ++#define CLK_APMU_PCIE_PORTE_MSTE 64 ++#define CLK_APMU_PCIE_PORTE_SLV 65 ++#define CLK_APMU_EMAC0_BUS 66 ++#define CLK_APMU_EMAC0_REF 67 ++#define CLK_APMU_EMAC0_1588 68 ++#define CLK_APMU_EMAC0_RGMII_TX 69 ++#define CLK_APMU_EMAC1_BUS 70 ++#define CLK_APMU_EMAC1_REF 71 ++#define CLK_APMU_EMAC1_1588 72 ++#define CLK_APMU_EMAC1_RGMII_TX 73 ++#define CLK_APMU_EMAC2_BUS 74 ++#define CLK_APMU_EMAC2_REF 75 ++#define CLK_APMU_EMAC2_1588 76 ++#define CLK_APMU_EMAC2_RGMII_TX 77 ++#define CLK_APMU_ESPI_SCLK_SRC 78 ++#define CLK_APMU_ESPI_SCLK 79 ++#define CLK_APMU_ESPI_MCLK 80 ++#define CLK_APMU_CAM_SRC1 81 ++#define CLK_APMU_CAM_SRC2 82 ++#define CLK_APMU_CAM_SRC3 83 ++#define CLK_APMU_CAM_SRC4 84 ++#define CLK_APMU_ISIM_VCLK0 85 ++#define CLK_APMU_ISIM_VCLK1 86 ++#define CLK_APMU_ISIM_VCLK2 87 ++#define CLK_APMU_ISIM_VCLK3 88 ++ ++/* APMU resets */ ++#define RESET_APMU_CSI 0 ++#define RESET_APMU_CCIC2PHY 1 ++#define RESET_APMU_CCIC3PHY 2 ++#define RESET_APMU_ISP_CIBUS 3 ++#define RESET_APMU_DSI_ESC 4 ++#define RESET_APMU_LCD 5 ++#define RESET_APMU_V2D 6 ++#define RESET_APMU_LCD_MCLK 7 ++#define RESET_APMU_LCD_DSCCLK 8 ++#define RESET_APMU_SC2_HCLK 9 ++#define RESET_APMU_CCIC_4X 10 ++#define RESET_APMU_CCIC1_PHY 11 ++#define RESET_APMU_SDH_AXI 12 ++#define RESET_APMU_SDH0 13 ++#define RESET_APMU_SDH1 14 ++#define RESET_APMU_SDH2 15 ++#define RESET_APMU_USB2 16 ++#define RESET_APMU_USB3_PORTA 17 ++#define RESET_APMU_USB3_PORTB 18 ++#define RESET_APMU_USB3_PORTC 19 ++#define RESET_APMU_USB3_PORTD 20 ++#define RESET_APMU_QSPI 21 ++#define RESET_APMU_QSPI_BUS 22 ++#define RESET_APMU_DMA 23 ++#define RESET_APMU_AES_WTM 24 ++#define RESET_APMU_MCB_DCLK 25 ++#define RESET_APMU_MCB_ACLK 26 ++#define RESET_APMU_VPU 27 ++#define RESET_APMU_DTC 28 ++#define RESET_APMU_GPU 29 ++#define RESET_APMU_ALZO 30 ++#define RESET_APMU_MC 31 ++#define RESET_APMU_CPU0_POP 32 ++#define RESET_APMU_CPU0_SW 33 ++#define RESET_APMU_CPU1_POP 34 ++#define RESET_APMU_CPU1_SW 35 ++#define RESET_APMU_CPU2_POP 36 ++#define RESET_APMU_CPU2_SW 37 ++#define RESET_APMU_CPU3_POP 38 ++#define RESET_APMU_CPU3_SW 39 ++#define RESET_APMU_C0_MPSUB_SW 40 ++#define RESET_APMU_CPU4_POP 41 ++#define RESET_APMU_CPU4_SW 42 ++#define RESET_APMU_CPU5_POP 43 ++#define RESET_APMU_CPU5_SW 44 ++#define RESET_APMU_CPU6_POP 45 ++#define RESET_APMU_CPU6_SW 46 ++#define RESET_APMU_CPU7_POP 47 ++#define RESET_APMU_CPU7_SW 48 ++#define RESET_APMU_C1_MPSUB_SW 49 ++#define RESET_APMU_MPSUB_DBG 50 ++#define RESET_APMU_UCIE 51 ++#define RESET_APMU_RCPU 52 ++#define RESET_APMU_DSI4LN2_ESCCLK 53 ++#define RESET_APMU_DSI4LN2_LCD_SW 54 ++#define RESET_APMU_DSI4LN2_LCD_MCLK 55 ++#define RESET_APMU_DSI4LN2_LCD_DSCCLK 56 ++#define RESET_APMU_DSI4LN2_DPU_ACLK 57 ++#define RESET_APMU_DPU_ACLK 58 ++#define RESET_APMU_UFS_ACLK 59 ++#define RESET_APMU_EDP0 60 ++#define RESET_APMU_EDP1 61 ++#define RESET_APMU_PCIE_PORTA 62 ++#define RESET_APMU_PCIE_PORTB 63 ++#define RESET_APMU_PCIE_PORTC 64 ++#define RESET_APMU_PCIE_PORTD 65 ++#define RESET_APMU_PCIE_PORTE 66 ++#define RESET_APMU_EMAC0 67 ++#define RESET_APMU_EMAC1 68 ++#define RESET_APMU_EMAC2 69 ++#define RESET_APMU_ESPI_MCLK 70 ++#define RESET_APMU_ESPI_SCLK 71 ++ ++/* DCIU clocks */ ++#define CLK_DCIU_HDMA 0 ++#define CLK_DCIU_DMA350 1 ++#define CLK_DCIU_C2_TCM_PIPE 2 ++#define CLK_DCIU_C3_TCM_PIPE 3 ++ ++/* DCIU resets*/ ++#define RESET_DCIU_HDMA 0 ++#define RESET_DCIU_DMA350 1 ++#define RESET_DCIU_DMA350_0 2 ++#define RESET_DCIU_DMA350_1 3 ++#define RESET_DCIU_AXIDMA0 4 ++#define RESET_DCIU_AXIDMA1 5 ++#define RESET_DCIU_AXIDMA2 6 ++#define RESET_DCIU_AXIDMA3 7 ++#define RESET_DCIU_AXIDMA4 8 ++#define RESET_DCIU_AXIDMA5 9 ++#define RESET_DCIU_AXIDMA6 10 ++#define RESET_DCIU_AXIDMA7 11 ++ ++/* RCPU SYSCTRL clocks */ ++#define CLK_RCPU_SYSCTRL_RCAN0 0 ++#define CLK_RCPU_SYSCTRL_RCAN1 1 ++#define CLK_RCPU_SYSCTRL_RCAN2 2 ++#define CLK_RCPU_SYSCTRL_RCAN3 3 ++#define CLK_RCPU_SYSCTRL_RCAN4 4 ++#define CLK_RCPU_SYSCTRL_RCAN0_BUS 5 ++#define CLK_RCPU_SYSCTRL_RCAN1_BUS 6 ++#define CLK_RCPU_SYSCTRL_RCAN2_BUS 7 ++#define CLK_RCPU_SYSCTRL_RCAN3_BUS 8 ++#define CLK_RCPU_SYSCTRL_RCAN4_BUS 9 ++#define CLK_RCPU_SYSCTRL_RIRC0 10 ++#define CLK_RCPU_SYSCTRL_RIRC1 11 ++#define CLK_RCPU_SYSCTRL_RESPI_SCLK_SRC 12 ++#define CLK_RCPU_SYSCTRL_RESPI_SCLK 13 ++#define CLK_RCPU_SYSCTRL_REMAC_BUS 14 ++#define CLK_RCPU_SYSCTRL_REMAC_REF 15 ++#define CLK_RCPU_SYSCTRL_REMAC_1588 16 ++#define CLK_RCPU_SYSCTRL_REMAC_RGMII_TX 17 ++#define CLK_RCPU_SYSCTRL_RI2S0_SYSCLK 18 ++#define CLK_RCPU_SYSCTRL_RI2S1_SYSCLK 19 ++ ++/* RCPU SYSCTRL resets */ ++#define RESET_RCPU_SYSCTRL_RCAN0 0 ++#define RESET_RCPU_SYSCTRL_RCAN1 1 ++#define RESET_RCPU_SYSCTRL_RCAN2 2 ++#define RESET_RCPU_SYSCTRL_RCAN3 3 ++#define RESET_RCPU_SYSCTRL_RCAN4 4 ++#define RESET_RCPU_SYSCTRL_RIRC0 5 ++#define RESET_RCPU_SYSCTRL_RIRC1 6 ++#define RESET_RCPU_SYSCTRL_RGMAC 7 ++#define RESET_RCPU_SYSCTRL_RESPI 8 ++#define RESET_RCPU_SYSCTRL_RI2S0_SYSCLK 9 ++#define RESET_RCPU_SYSCTRL_RI2S1_SYSCLK 10 ++ ++/* RCPU UARTCTRL clocks */ ++#define CLK_RCPU_UARTCTRL_RUART0 0 ++#define CLK_RCPU_UARTCTRL_RUART1 1 ++#define CLK_RCPU_UARTCTRL_RUART2 2 ++#define CLK_RCPU_UARTCTRL_RUART3 3 ++#define CLK_RCPU_UARTCTRL_RUART4 4 ++#define CLK_RCPU_UARTCTRL_RUART5 5 ++#define CLK_RCPU_UARTCTRL_RUART0_BUS 6 ++#define CLK_RCPU_UARTCTRL_RUART1_BUS 7 ++#define CLK_RCPU_UARTCTRL_RUART2_BUS 8 ++#define CLK_RCPU_UARTCTRL_RUART3_BUS 9 ++#define CLK_RCPU_UARTCTRL_RUART4_BUS 10 ++#define CLK_RCPU_UARTCTRL_RUART5_BUS 11 ++ ++/* RCPU UARTCTRL resets */ ++#define RESET_RCPU_UARTCTRL_RUART0 0 ++#define RESET_RCPU_UARTCTRL_RUART1 1 ++#define RESET_RCPU_UARTCTRL_RUART2 2 ++#define RESET_RCPU_UARTCTRL_RUART3 3 ++#define RESET_RCPU_UARTCTRL_RUART4 4 ++#define RESET_RCPU_UARTCTRL_RUART5 5 ++ ++/* RCPU I2SCTRL clocks */ ++#define CLK_RCPU_I2SCTRL_RI2S0 0 ++#define CLK_RCPU_I2SCTRL_RI2S1 1 ++#define CLK_RCPU_I2SCTRL_RI2S2 2 ++#define CLK_RCPU_I2SCTRL_RI2S3 3 ++#define CLK_RCPU_I2SCTRL_RI2S0_BUS 4 ++#define CLK_RCPU_I2SCTRL_RI2S1_BUS 5 ++#define CLK_RCPU_I2SCTRL_RI2S2_BUS 6 ++#define CLK_RCPU_I2SCTRL_RI2S3_BUS 7 ++#define CLK_RCPU_I2SCTRL_RI2S2_SYSCLK 8 ++#define CLK_RCPU_I2SCTRL_RI2S3_SYSCLK 9 ++ ++/* RCPU I2SCTRL resets */ ++#define RESET_RCPU_I2SCTRL_RI2S0 0 ++#define RESET_RCPU_I2SCTRL_RI2S1 1 ++#define RESET_RCPU_I2SCTRL_RI2S2 2 ++#define RESET_RCPU_I2SCTRL_RI2S3 3 ++#define RESET_RCPU_I2SCTRL_RI2S2_SYSCLK 4 ++#define RESET_RCPU_I2SCTRL_RI2S3_SYSCLK 5 ++ ++/* RCPU SPICTRL clocks */ ++#define CLK_RCPU_SPICTRL_RSPI0 0 ++#define CLK_RCPU_SPICTRL_RSPI1 1 ++#define CLK_RCPU_SPICTRL_RSPI2 2 ++#define CLK_RCPU_SPICTRL_RSPI0_BUS 3 ++#define CLK_RCPU_SPICTRL_RSPI1_BUS 4 ++#define CLK_RCPU_SPICTRL_RSPI2_BUS 5 ++ ++/* RCPU SPICTRL resets */ ++#define RESET_RCPU_SPICTRL_RSPI0 0 ++#define RESET_RCPU_SPICTRL_RSPI1 1 ++#define RESET_RCPU_SPICTRL_RSPI2 2 ++ ++/* RCPU I2CCTRL clocks */ ++#define CLK_RCPU_I2CCTRL_RI2C0 0 ++#define CLK_RCPU_I2CCTRL_RI2C1 1 ++#define CLK_RCPU_I2CCTRL_RI2C2 2 ++#define CLK_RCPU_I2CCTRL_RI2C0_BUS 3 ++#define CLK_RCPU_I2CCTRL_RI2C1_BUS 4 ++#define CLK_RCPU_I2CCTRL_RI2C2_BUS 5 ++ ++/* RCPU I2CCTRL resets */ ++#define RESET_RCPU_I2CCTRL_RI2C0 0 ++#define RESET_RCPU_I2CCTRL_RI2C1 1 ++#define RESET_RCPU_I2CCTRL_RI2C2 2 ++ ++/* RMPU clocks */ ++#define CLK_RPMU_RCPU_APB 0 ++#define CLK_RPMU_RCPU_AXI 1 ++#define CLK_RPMU_RIPC2MSA 2 ++#define CLK_RPMU_RIPC2CP 3 ++#define CLK_RPMU_RIPC2AP 4 ++#define CLK_RPMU_RTIMER1 5 ++#define CLK_RPMU_RTIMER2 6 ++#define CLK_RPMU_RTIMER3 7 ++#define CLK_RPMU_RTIMER4 8 ++#define CLK_RPMU_RTIMER1_BUS 9 ++#define CLK_RPMU_RTIMER2_BUS 10 ++#define CLK_RPMU_RTIMER3_BUS 11 ++#define CLK_RPMU_RTIMER4_BUS 12 ++#define CLK_RPMU_RT24_CORE0 13 ++#define CLK_RPMU_RT24_CORE1 14 ++#define CLK_RPMU_RGPIO 15 ++#define CLK_RPMU_RGPIO_EDGE 16 ++#define CLK_RPMU_RGPIO_LP 17 ++ ++/* RMPU resets */ ++#define RESET_RPMU_RTIMER1 0 ++#define RESET_RPMU_RTIMER2 1 ++#define RESET_RPMU_RTIMER3 2 ++#define RESET_RPMU_RTIMER4 3 ++#define RESET_RPMU_IPC2AP 4 ++#define RESET_RPMU_IPC2CP 5 ++#define RESET_RPMU_IPC2MSA 6 ++#define RESET_RPMU_RT24_CORE0 7 ++#define RESET_RPMU_RT24_CORE1 8 ++#define RESET_RPMU_GPIO 9 ++#define RESET_RPMU_GPIO_EDGE 10 ++ ++/* RCPU PWMCTRL clocks */ ++#define CLK_RCPU_PWMCTRL_RPWM0 0 ++#define CLK_RCPU_PWMCTRL_RPWM1 1 ++#define CLK_RCPU_PWMCTRL_RPWM2 2 ++#define CLK_RCPU_PWMCTRL_RPWM3 3 ++#define CLK_RCPU_PWMCTRL_RPWM4 4 ++#define CLK_RCPU_PWMCTRL_RPWM5 5 ++#define CLK_RCPU_PWMCTRL_RPWM6 6 ++#define CLK_RCPU_PWMCTRL_RPWM7 7 ++#define CLK_RCPU_PWMCTRL_RPWM8 8 ++#define CLK_RCPU_PWMCTRL_RPWM9 9 ++#define CLK_RCPU_PWMCTRL_RPWM0_BUS 10 ++#define CLK_RCPU_PWMCTRL_RPWM1_BUS 11 ++#define CLK_RCPU_PWMCTRL_RPWM2_BUS 12 ++#define CLK_RCPU_PWMCTRL_RPWM3_BUS 13 ++#define CLK_RCPU_PWMCTRL_RPWM4_BUS 14 ++#define CLK_RCPU_PWMCTRL_RPWM5_BUS 15 ++#define CLK_RCPU_PWMCTRL_RPWM6_BUS 16 ++#define CLK_RCPU_PWMCTRL_RPWM7_BUS 17 ++#define CLK_RCPU_PWMCTRL_RPWM8_BUS 18 ++#define CLK_RCPU_PWMCTRL_RPWM9_BUS 19 ++ ++/* RCPU PWMCTRL resets */ ++#define RESET_RCPU_PWMCTRL_PWM0 0 ++#define RESET_RCPU_PWMCTRL_PWM1 1 ++#define RESET_RCPU_PWMCTRL_PWM2 2 ++#define RESET_RCPU_PWMCTRL_PWM3 3 ++#define RESET_RCPU_PWMCTRL_PWM4 4 ++#define RESET_RCPU_PWMCTRL_PWM5 5 ++#define RESET_RCPU_PWMCTRL_PWM6 6 ++#define RESET_RCPU_PWMCTRL_PWM7 7 ++#define RESET_RCPU_PWMCTRL_PWM8 8 ++#define RESET_RCPU_PWMCTRL_PWM9 9 ++ ++/* APBC2 clocks */ ++#define CLK_APBC2_SEC_UART1 0 ++#define CLK_APBC2_SEC_UART1_BUS 1 ++#define CLK_APBC2_SEC_SPI2_I2S_BCLK 2 ++#define CLK_APBC2_SEC_SPI2 3 ++#define CLK_APBC2_SEC_SPI2_BUS 4 ++#define CLK_APBC2_SEC_TWSI3 5 ++#define CLK_APBC2_SEC_TWSI3_BUS 6 ++#define CLK_APBC2_SEC_RTC 7 ++#define CLK_APBC2_SEC_RTC_BUS 8 ++#define CLK_APBC2_SEC_TIMERS 9 ++#define CLK_APBC2_SEC_TIMERS_BUS 10 ++#define CLK_APBC2_SEC_GPIO 11 ++#define CLK_APBC2_SEC_GPIO_BUS 12 ++ ++/* APBC2 resets */ ++#define RESET_APBC2_SEC_UART1 0 ++#define RESET_APBC2_SEC_SPI2 1 ++#define RESET_APBC2_SEC_TWSI3 2 ++#define RESET_APBC2_SEC_RTC 3 ++#define RESET_APBC2_SEC_TIMERS 4 ++#define RESET_APBC2_SEC_GPIO 5 ++ ++#endif /* _DT_BINDINGS_SPACEMIT_CCU_K3_H_ */ diff --git a/include/dt-bindings/clock/th1520-audiosys.h b/include/dt-bindings/clock/th1520-audiosys.h new file mode 100644 index 000000000000..2001545b68b8 @@ -632075,138 +634205,6 @@ index 000000000000..9ff8ca4c3d67 +#define RST_MAX_NUM (RST_RXU31+1) + +#endif -diff --git a/include/dt-bindings/reset/spacemit-k1-reset.h b/include/dt-bindings/reset/spacemit-k1-reset.h -new file mode 100644 -index 000000000000..ced13afecf8f ---- /dev/null -+++ b/include/dt-bindings/reset/spacemit-k1-reset.h -@@ -0,0 +1,126 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* Copyright (c) 2023, spacemit Corporation. */ -+ -+#ifndef __DT_BINDINGS_RESET_SAPCEMIT_K1_H__ -+#define __DT_BINDINGS_RESET_SAPCEMIT_K1_H__ -+ -+#define RESET_UART1 1 -+#define RESET_UART2 2 -+#define RESET_GPIO 3 -+#define RESET_PWM0 4 -+#define RESET_PWM1 5 -+#define RESET_PWM2 6 -+#define RESET_PWM3 7 -+#define RESET_PWM4 8 -+#define RESET_PWM5 9 -+#define RESET_PWM6 10 -+#define RESET_PWM7 11 -+#define RESET_PWM8 12 -+#define RESET_PWM9 13 -+#define RESET_PWM10 14 -+#define RESET_PWM11 15 -+#define RESET_PWM12 16 -+#define RESET_PWM13 17 -+#define RESET_PWM14 18 -+#define RESET_PWM15 19 -+#define RESET_PWM16 20 -+#define RESET_PWM17 21 -+#define RESET_PWM18 22 -+#define RESET_PWM19 23 -+#define RESET_SSP3 24 -+#define RESET_UART3 25 -+#define RESET_RTC 26 -+#define RESET_TWSI0 27 -+#define RESET_TIMERS1 28 -+#define RESET_AIB 29 -+#define RESET_TIMERS2 30 -+#define RESET_ONEWIRE 31 -+#define RESET_SSPA0 32 -+#define RESET_SSPA1 33 -+#define RESET_DRO 34 -+#define RESET_IR 35 -+#define RESET_TWSI1 36 -+#define RESET_TSEN 37 -+#define RESET_TWSI2 38 -+#define RESET_TWSI4 39 -+#define RESET_TWSI5 40 -+#define RESET_TWSI6 41 -+#define RESET_TWSI7 42 -+#define RESET_TWSI8 43 -+#define RESET_IPC_AP2AUD 44 -+#define RESET_UART4 45 -+#define RESET_UART5 46 -+#define RESET_UART6 47 -+#define RESET_UART7 48 -+#define RESET_UART8 49 -+#define RESET_UART9 50 -+#define RESET_CAN0 51 -+#define RESET_WDT 52 -+#define RESET_JPG 53 -+#define RESET_CSI 54 -+#define RESET_CCIC2_PHY 55 -+#define RESET_CCIC3_PHY 56 -+#define RESET_ISP 57 -+#define RESET_ISP_AHB 58 -+#define RESET_ISP_CI 59 -+#define RESET_ISP_CPP 60 -+#define RESET_LCD 61 -+#define RESET_DSI_ESC 62 -+#define RESET_V2D 63 -+#define RESET_MIPI 64 -+#define RESET_LCD_SPI 65 -+#define RESET_LCD_SPI_BUS 66 -+#define RESET_LCD_SPI_HBUS 67 -+#define RESET_LCD_MCLK 68 -+#define RESET_CCIC_4X 69 -+#define RESET_CCIC1_PHY 70 -+#define RESET_SDH_AXI 71 -+#define RESET_SDH0 72 -+#define RESET_SDH1 73 -+#define RESET_USB_AXI 74 -+#define RESET_USBP1_AXI 75 -+#define RESET_USB3_0 76 -+#define RESET_QSPI 77 -+#define RESET_QSPI_BUS 78 -+#define RESET_DMA 79 -+#define RESET_AES 80 -+#define RESET_VPU 81 -+#define RESET_GPU 82 -+#define RESET_SDH2 83 -+#define RESET_MC 84 -+#define RESET_EM_AXI 85 -+#define RESET_EM 86 -+#define RESET_AUDIO_SYS 87 -+#define RESET_HDMI 88 -+#define RESET_PCIE0 89 -+#define RESET_PCIE1 90 -+#define RESET_PCIE2 91 -+#define RESET_EMAC0 92 -+#define RESET_EMAC1 93 -+#define RESET_SEC_UART1 94 -+#define RESET_SEC_SSP2 95 -+#define RESET_SEC_TWSI3 96 -+#define RESET_SEC_RTC 97 -+#define RESET_SEC_TIMERS0 98 -+#define RESET_SEC_KPC 99 -+#define RESET_SEC_GPIO 100 -+#define RESET_RCPU_HDMIAUDIO 101 -+#define RESET_RCPU_CAN 102 -+#define RESET_RCPU_I2C0 103 -+#define RESET_RCPU_SSP0 104 -+#define RESET_RCPU_IR 105 -+#define RESET_RCPU_UART0 106 -+#define RESET_RCPU_UART1 107 -+#define RESET_RCPU2_PWM0 108 -+#define RESET_RCPU2_PWM1 109 -+#define RESET_RCPU2_PWM2 110 -+#define RESET_RCPU2_PWM3 111 -+#define RESET_RCPU2_PWM4 112 -+#define RESET_RCPU2_PWM5 113 -+#define RESET_RCPU2_PWM6 114 -+#define RESET_RCPU2_PWM7 115 -+#define RESET_RCPU2_PWM8 116 -+#define RESET_RCPU2_PWM9 117 -+#define RESET_NUMBER 118 -+ -+#endif /* __DT_BINDINGS_RESET_SAPCEMIT_K1_H__ */ diff --git a/include/dt-bindings/reset/xuantie,th1520-reset.h b/include/dt-bindings/reset/xuantie,th1520-reset.h new file mode 100644 index 000000000000..44a4581cc229 @@ -634072,6 +636070,464 @@ index 000000000000..24c25e57fd34 + +#endif /* __LINUX_TH1520_RPMSG_H__*/ + +diff --git a/include/soc/spacemit/k1-syscon.h b/include/soc/spacemit/k1-syscon.h +new file mode 100644 +index 000000000000..331cc1d35bbb +--- /dev/null ++++ b/include/soc/spacemit/k1-syscon.h +@@ -0,0 +1,149 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* SpacemiT clock and reset driver definitions for the K1 SoC */ ++ ++#ifndef __SOC_K1_SYSCON_H__ ++#define __SOC_K1_SYSCON_H__ ++ ++/* APBS register offset */ ++#define APBS_PLL1_SWCR1 0x100 ++#define APBS_PLL1_SWCR2 0x104 ++#define APBS_PLL1_SWCR3 0x108 ++#define APBS_PLL2_SWCR1 0x118 ++#define APBS_PLL2_SWCR2 0x11c ++#define APBS_PLL2_SWCR3 0x120 ++#define APBS_PLL3_SWCR1 0x124 ++#define APBS_PLL3_SWCR2 0x128 ++#define APBS_PLL3_SWCR3 0x12c ++ ++/* MPMU register offset */ ++#define MPMU_POSR 0x0010 ++#define MPMU_FCCR 0x0008 ++#define POSR_PLL1_LOCK BIT(27) ++#define POSR_PLL2_LOCK BIT(28) ++#define POSR_PLL3_LOCK BIT(29) ++#define MPMU_SUCCR 0x0014 ++#define MPMU_ISCCR 0x0044 ++#define MPMU_WDTPCR 0x0200 ++#define MPMU_RIPCCR 0x0210 ++#define MPMU_ACGR 0x1024 ++#define MPMU_APBCSCR 0x1050 ++#define MPMU_SUCCR_1 0x10b0 ++ ++/* APBC register offset */ ++#define APBC_UART1_CLK_RST 0x00 ++#define APBC_UART2_CLK_RST 0x04 ++#define APBC_GPIO_CLK_RST 0x08 ++#define APBC_PWM0_CLK_RST 0x0c ++#define APBC_PWM1_CLK_RST 0x10 ++#define APBC_PWM2_CLK_RST 0x14 ++#define APBC_PWM3_CLK_RST 0x18 ++#define APBC_TWSI8_CLK_RST 0x20 ++#define APBC_UART3_CLK_RST 0x24 ++#define APBC_RTC_CLK_RST 0x28 ++#define APBC_TWSI0_CLK_RST 0x2c ++#define APBC_TWSI1_CLK_RST 0x30 ++#define APBC_TIMERS1_CLK_RST 0x34 ++#define APBC_TWSI2_CLK_RST 0x38 ++#define APBC_AIB_CLK_RST 0x3c ++#define APBC_TWSI4_CLK_RST 0x40 ++#define APBC_TIMERS2_CLK_RST 0x44 ++#define APBC_ONEWIRE_CLK_RST 0x48 ++#define APBC_TWSI5_CLK_RST 0x4c ++#define APBC_DRO_CLK_RST 0x58 ++#define APBC_IR_CLK_RST 0x5c ++#define APBC_TWSI6_CLK_RST 0x60 ++#define APBC_COUNTER_CLK_SEL 0x64 ++#define APBC_TWSI7_CLK_RST 0x68 ++#define APBC_TSEN_CLK_RST 0x6c ++#define APBC_UART4_CLK_RST 0x70 ++#define APBC_UART5_CLK_RST 0x74 ++#define APBC_UART6_CLK_RST 0x78 ++#define APBC_SSP3_CLK_RST 0x7c ++#define APBC_SSPA0_CLK_RST 0x80 ++#define APBC_SSPA1_CLK_RST 0x84 ++#define APBC_IPC_AP2AUD_CLK_RST 0x90 ++#define APBC_UART7_CLK_RST 0x94 ++#define APBC_UART8_CLK_RST 0x98 ++#define APBC_UART9_CLK_RST 0x9c ++#define APBC_CAN0_CLK_RST 0xa0 ++#define APBC_PWM4_CLK_RST 0xa8 ++#define APBC_PWM5_CLK_RST 0xac ++#define APBC_PWM6_CLK_RST 0xb0 ++#define APBC_PWM7_CLK_RST 0xb4 ++#define APBC_PWM8_CLK_RST 0xb8 ++#define APBC_PWM9_CLK_RST 0xbc ++#define APBC_PWM10_CLK_RST 0xc0 ++#define APBC_PWM11_CLK_RST 0xc4 ++#define APBC_PWM12_CLK_RST 0xc8 ++#define APBC_PWM13_CLK_RST 0xcc ++#define APBC_PWM14_CLK_RST 0xd0 ++#define APBC_PWM15_CLK_RST 0xd4 ++#define APBC_PWM16_CLK_RST 0xd8 ++#define APBC_PWM17_CLK_RST 0xdc ++#define APBC_PWM18_CLK_RST 0xe0 ++#define APBC_PWM19_CLK_RST 0xe4 ++ ++/* APMU register offset */ ++#define APMU_JPG_CLK_RES_CTRL 0x020 ++#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024 ++#define APMU_ISP_CLK_RES_CTRL 0x038 ++#define APMU_LCD_CLK_RES_CTRL1 0x044 ++#define APMU_LCD_SPI_CLK_RES_CTRL 0x048 ++#define APMU_LCD_CLK_RES_CTRL2 0x04c ++#define APMU_CCIC_CLK_RES_CTRL 0x050 ++#define APMU_SDH0_CLK_RES_CTRL 0x054 ++#define APMU_SDH1_CLK_RES_CTRL 0x058 ++#define APMU_USB_CLK_RES_CTRL 0x05c ++#define APMU_QSPI_CLK_RES_CTRL 0x060 ++#define APMU_DMA_CLK_RES_CTRL 0x064 ++#define APMU_AES_CLK_RES_CTRL 0x068 ++#define APMU_VPU_CLK_RES_CTRL 0x0a4 ++#define APMU_GPU_CLK_RES_CTRL 0x0cc ++#define APMU_SDH2_CLK_RES_CTRL 0x0e0 ++#define APMU_PMUA_MC_CTRL 0x0e8 ++#define APMU_PMU_CC2_AP 0x100 ++#define APMU_PMUA_EM_CLK_RES_CTRL 0x104 ++#define APMU_AUDIO_CLK_RES_CTRL 0x14c ++#define APMU_HDMI_CLK_RES_CTRL 0x1b8 ++#define APMU_CCI550_CLK_CTRL 0x300 ++#define APMU_ACLK_CLK_CTRL 0x388 ++#define APMU_CPU_C0_CLK_CTRL 0x38C ++#define APMU_CPU_C1_CLK_CTRL 0x390 ++#define APMU_PCIE_CLK_RES_CTRL_0 0x3cc ++#define APMU_PCIE_CLK_RES_CTRL_1 0x3d4 ++#define APMU_PCIE_CLK_RES_CTRL_2 0x3dc ++#define APMU_EMAC0_CLK_RES_CTRL 0x3e4 ++#define APMU_EMAC1_CLK_RES_CTRL 0x3ec ++ ++/* RCPU register offsets */ ++#define RCPU_SSP0_CLK_RST 0x0028 ++#define RCPU_I2C0_CLK_RST 0x0030 ++#define RCPU_UART1_CLK_RST 0x003c ++#define RCPU_CAN_CLK_RST 0x0048 ++#define RCPU_IR_CLK_RST 0x004c ++#define RCPU_UART0_CLK_RST 0x00d8 ++#define AUDIO_HDMI_CLK_CTRL 0x2044 ++ ++/* RCPU2 register offsets */ ++#define RCPU2_PWM0_CLK_RST 0x0000 ++#define RCPU2_PWM1_CLK_RST 0x0004 ++#define RCPU2_PWM2_CLK_RST 0x0008 ++#define RCPU2_PWM3_CLK_RST 0x000c ++#define RCPU2_PWM4_CLK_RST 0x0010 ++#define RCPU2_PWM5_CLK_RST 0x0014 ++#define RCPU2_PWM6_CLK_RST 0x0018 ++#define RCPU2_PWM7_CLK_RST 0x001c ++#define RCPU2_PWM8_CLK_RST 0x0020 ++#define RCPU2_PWM9_CLK_RST 0x0024 ++ ++/* APBC2 register offsets */ ++#define APBC2_UART1_CLK_RST 0x0000 ++#define APBC2_SSP2_CLK_RST 0x0004 ++#define APBC2_TWSI3_CLK_RST 0x0008 ++#define APBC2_RTC_CLK_RST 0x000c ++#define APBC2_TIMERS0_CLK_RST 0x0010 ++#define APBC2_KPC_CLK_RST 0x0014 ++#define APBC2_GPIO_CLK_RST 0x001c ++ ++#endif /* __SOC_K1_SYSCON_H__ */ +diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-syscon.h +new file mode 100644 +index 000000000000..bcc9726efaaa +--- /dev/null ++++ b/include/soc/spacemit/k3-syscon.h +@@ -0,0 +1,271 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* SpacemiT clock and reset driver definitions for the K3 SoC */ ++ ++#ifndef __SOC_K3_SYSCON_H__ ++#define __SOC_K3_SYSCON_H__ ++ ++/* APBS register offset */ ++#define APBS_PLL1_SWCR1 0x100 ++#define APBS_PLL1_SWCR2 0x104 ++#define APBS_PLL1_SWCR3 0x108 ++#define APBS_PLL2_SWCR1 0x118 ++#define APBS_PLL2_SWCR2 0x11c ++#define APBS_PLL2_SWCR3 0x120 ++#define APBS_PLL3_SWCR1 0x124 ++#define APBS_PLL3_SWCR2 0x128 ++#define APBS_PLL3_SWCR3 0x12c ++#define APBS_PLL4_SWCR1 0x130 ++#define APBS_PLL4_SWCR2 0x134 ++#define APBS_PLL4_SWCR3 0x138 ++#define APBS_PLL5_SWCR1 0x13c ++#define APBS_PLL5_SWCR2 0x140 ++#define APBS_PLL5_SWCR3 0x144 ++#define APBS_PLL6_SWCR1 0x148 ++#define APBS_PLL6_SWCR2 0x14c ++#define APBS_PLL6_SWCR3 0x150 ++#define APBS_PLL7_SWCR1 0x158 ++#define APBS_PLL7_SWCR2 0x15c ++#define APBS_PLL7_SWCR3 0x160 ++#define APBS_PLL8_SWCR1 0x180 ++#define APBS_PLL8_SWCR2 0x184 ++#define APBS_PLL8_SWCR3 0x188 ++ ++/* MPMU register offset */ ++#define MPMU_FCCR 0x0008 ++#define MPMU_POSR 0x0010 ++#define POSR_PLL1_LOCK BIT(24) ++#define POSR_PLL2_LOCK BIT(25) ++#define POSR_PLL3_LOCK BIT(26) ++#define POSR_PLL4_LOCK BIT(27) ++#define POSR_PLL5_LOCK BIT(28) ++#define POSR_PLL6_LOCK BIT(29) ++#define POSR_PLL7_LOCK BIT(30) ++#define POSR_PLL8_LOCK BIT(31) ++#define MPMU_SUCCR 0x0014 ++#define MPMU_ISCCR 0x0044 ++#define MPMU_WDTPCR 0x0200 ++#define MPMU_RIPCCR 0x0210 ++#define MPMU_ACGR 0x1024 ++#define MPMU_APBCSCR 0x1050 ++#define MPMU_SUCCR_1 0x10b0 ++ ++#define MPMU_I2S0_SYSCLK 0x1100 ++#define MPMU_I2S2_SYSCLK 0x1104 ++#define MPMU_I2S3_SYSCLK 0x1108 ++#define MPMU_I2S4_SYSCLK 0x110c ++#define MPMU_I2S5_SYSCLK 0x1110 ++#define MPMU_I2S_SYSCLK_CTRL 0x1114 ++ ++/* APBC register offset */ ++#define APBC_UART0_CLK_RST 0x00 ++#define APBC_UART2_CLK_RST 0x04 ++#define APBC_GPIO_CLK_RST 0x08 ++#define APBC_PWM0_CLK_RST 0x0c ++#define APBC_PWM1_CLK_RST 0x10 ++#define APBC_PWM2_CLK_RST 0x14 ++#define APBC_PWM3_CLK_RST 0x18 ++#define APBC_TWSI8_CLK_RST 0x20 ++#define APBC_UART3_CLK_RST 0x24 ++#define APBC_RTC_CLK_RST 0x28 ++#define APBC_TWSI0_CLK_RST 0x2c ++#define APBC_TWSI1_CLK_RST 0x30 ++#define APBC_TIMERS0_CLK_RST 0x34 ++#define APBC_TWSI2_CLK_RST 0x38 ++#define APBC_AIB_CLK_RST 0x3c ++#define APBC_TWSI4_CLK_RST 0x40 ++#define APBC_TIMERS1_CLK_RST 0x44 ++#define APBC_ONEWIRE_CLK_RST 0x48 ++#define APBC_TWSI5_CLK_RST 0x4c ++#define APBC_DRO_CLK_RST 0x58 ++#define APBC_IR0_CLK_RST 0x5c ++#define APBC_IR1_CLK_RST 0x1c ++#define APBC_TWSI6_CLK_RST 0x60 ++#define APBC_COUNTER_CLK_SEL 0x64 ++#define APBC_TSEN_CLK_RST 0x6c ++#define APBC_UART4_CLK_RST 0x70 ++#define APBC_UART5_CLK_RST 0x74 ++#define APBC_UART6_CLK_RST 0x78 ++#define APBC_SSP3_CLK_RST 0x7c ++#define APBC_SSPA0_CLK_RST 0x80 ++#define APBC_SSPA1_CLK_RST 0x84 ++#define APBC_SSPA2_CLK_RST 0x88 ++#define APBC_SSPA3_CLK_RST 0x8c ++#define APBC_IPC_AP2AUD_CLK_RST 0x90 ++#define APBC_UART7_CLK_RST 0x94 ++#define APBC_UART8_CLK_RST 0x98 ++#define APBC_UART9_CLK_RST 0x9c ++#define APBC_CAN0_CLK_RST 0xa0 ++#define APBC_CAN1_CLK_RST 0xa4 ++#define APBC_PWM4_CLK_RST 0xa8 ++#define APBC_PWM5_CLK_RST 0xac ++#define APBC_PWM6_CLK_RST 0xb0 ++#define APBC_PWM7_CLK_RST 0xb4 ++#define APBC_PWM8_CLK_RST 0xb8 ++#define APBC_PWM9_CLK_RST 0xbc ++#define APBC_PWM10_CLK_RST 0xc0 ++#define APBC_PWM11_CLK_RST 0xc4 ++#define APBC_PWM12_CLK_RST 0xc8 ++#define APBC_PWM13_CLK_RST 0xcc ++#define APBC_PWM14_CLK_RST 0xd0 ++#define APBC_PWM15_CLK_RST 0xd4 ++#define APBC_PWM16_CLK_RST 0xd8 ++#define APBC_PWM17_CLK_RST 0xdc ++#define APBC_PWM18_CLK_RST 0xe0 ++#define APBC_PWM19_CLK_RST 0xe4 ++#define APBC_TIMERS2_CLK_RST 0x11c ++#define APBC_TIMERS3_CLK_RST 0x120 ++#define APBC_TIMERS4_CLK_RST 0x124 ++#define APBC_TIMERS5_CLK_RST 0x128 ++#define APBC_TIMERS6_CLK_RST 0x12c ++#define APBC_TIMERS7_CLK_RST 0x130 ++ ++#define APBC_CAN2_CLK_RST 0x148 ++#define APBC_CAN3_CLK_RST 0x14c ++#define APBC_CAN4_CLK_RST 0x150 ++#define APBC_UART10_CLK_RST 0x154 ++#define APBC_SSP0_CLK_RST 0x158 ++#define APBC_SSP1_CLK_RST 0x15c ++#define APBC_SSPA4_CLK_RST 0x160 ++#define APBC_SSPA5_CLK_RST 0x164 ++ ++/* APMU register offset */ ++#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024 ++#define APMU_ISP_CLK_RES_CTRL 0x038 ++#define APMU_PMU_CLK_GATE_CTRL 0x040 ++#define APMU_LCD_CLK_RES_CTRL1 0x044 ++#define APMU_LCD_SPI_CLK_RES_CTRL 0x048 ++#define APMU_LCD_CLK_RES_CTRL2 0x04c ++#define APMU_CCIC_CLK_RES_CTRL 0x050 ++#define APMU_SDH0_CLK_RES_CTRL 0x054 ++#define APMU_SDH1_CLK_RES_CTRL 0x058 ++#define APMU_USB_CLK_RES_CTRL 0x05c ++#define APMU_QSPI_CLK_RES_CTRL 0x060 ++#define APMU_DMA_CLK_RES_CTRL 0x064 ++#define APMU_AES_CLK_RES_CTRL 0x068 ++#define APMU_MCB_CLK_RES_CTRL 0x06c ++#define APMU_VPU_CLK_RES_CTRL 0x0a4 ++#define APMU_DTC_CLK_RES_CTRL 0x0ac ++#define APMU_GPU_CLK_RES_CTRL 0x0cc ++#define APMU_SDH2_CLK_RES_CTRL 0x0e0 ++#define APMU_PMUA_MC_CTRL 0x0e8 ++#define APMU_PMU_CC2_AP 0x100 ++#define APMU_PMUA_EM_CLK_RES_CTRL 0x104 ++#define APMU_UCIE_CTRL 0x11c ++#define APMU_RCPU_CLK_RES_CTRL 0x14c ++#define APMU_TOP_DCLK_CTRL 0x158 ++#define APMU_LCD_EDP_CTRL 0x23c ++#define APMU_UFS_CLK_RES_CTRL 0x268 ++#define APMU_LCD_CLK_RES_CTRL3 0x26c ++#define APMU_LCD_CLK_RES_CTRL4 0x270 ++#define APMU_LCD_CLK_RES_CTRL5 0x274 ++#define APMU_CCI550_CLK_CTRL 0x300 ++#define APMU_ACLK_CLK_CTRL 0x388 ++#define APMU_CPU_C0_CLK_CTRL 0x38C ++#define APMU_CPU_C1_CLK_CTRL 0x390 ++#define APMU_CPU_C2_CLK_CTRL 0x394 ++#define APMU_CPU_C3_CLK_CTRL 0x208 ++#define APMU_PCIE_CLK_RES_CTRL_A 0x1f0 ++#define APMU_PCIE_CLK_RES_CTRL_B 0x1c8 ++#define APMU_PCIE_CLK_RES_CTRL_C 0x1d0 ++#define APMU_PCIE_CLK_RES_CTRL_D 0x1e0 ++#define APMU_PCIE_CLK_RES_CTRL_E 0x1e8 ++#define APMU_EMAC0_CLK_RES_CTRL 0x3e4 ++#define APMU_EMAC1_CLK_RES_CTRL 0x3ec ++#define APMU_EMAC2_CLK_RES_CTRL 0x248 ++#define APMU_ESPI_CLK_RES_CTRL 0x240 ++#define APMU_SNR_ISIM_VCLK_CTRL 0x3f8 ++ ++/* DCIU register offsets */ ++#define DCIU_DMASYS_CLK_EN 0x234 ++#define DCIU_DMASYS_SDMA_CLK_EN 0x238 ++#define DCIU_C2_TCM_PIPE_CLK 0x244 ++#define DCIU_C3_TCM_PIPE_CLK 0x248 ++ ++#define DCIU_DMASYS_S0_RSTN 0x204 ++#define DCIU_DMASYS_S1_RSTN 0x208 ++#define DCIU_DMASYS_A0_RSTN 0x20C ++#define DCIU_DMASYS_A1_RSTN 0x210 ++#define DCIU_DMASYS_A2_RSTN 0x214 ++#define DCIU_DMASYS_A3_RSTN 0x218 ++#define DCIU_DMASYS_A4_RSTN 0x21C ++#define DCIU_DMASYS_A5_RSTN 0x220 ++#define DCIU_DMASYS_A6_RSTN 0x224 ++#define DCIU_DMASYS_A7_RSTN 0x228 ++#define DCIU_DMASYS_RSTN 0x22C ++#define DCIU_DMASYS_SDMA_RSTN 0x230 ++ ++/* RCPU SYSCTRL register offsets */ ++#define RCPU_CAN_CLK_RST 0x4c ++#define RCPU_CAN1_CLK_RST 0xF0 ++#define RCPU_CAN2_CLK_RST 0xF4 ++#define RCPU_CAN3_CLK_RST 0xF8 ++#define RCPU_CAN4_CLK_RST 0xFC ++#define RCPU_IRC_CLK_RST 0x48 ++#define RCPU_IRC1_CLK_RST 0xEC ++#define RCPU_GMAC_CLK_RST 0xE4 ++#define RCPU_ESPI_CLK_RST 0xDC ++#define RCPU_AUDIO_I2S0_SYS_CLK_CTRL 0x70 ++#define RCPU_AUDIO_I2S1_SYS_CLK_CTRL 0x44 ++ ++/* RCPU UARTCTRL register offsets */ ++#define RCPU1_UART0_CLK_RST 0x00 ++#define RCPU1_UART1_CLK_RST 0x04 ++#define RCPU1_UART2_CLK_RST 0x08 ++#define RCPU1_UART3_CLK_RST 0x0c ++#define RCPU1_UART4_CLK_RST 0x10 ++#define RCPU1_UART5_CLK_RST 0x14 ++ ++/* RCPU I2SCTRL register offsets */ ++#define RCPU2_AUDIO_I2S0_TX_RX_CLK_CTRL 0x60 ++#define RCPU2_AUDIO_I2S1_TX_RX_CLK_CTRL 0x64 ++#define RCPU2_AUDIO_I2S2_TX_RX_CLK_CTRL 0x68 ++#define RCPU2_AUDIO_I2S3_TX_RX_CLK_CTRL 0x6C ++ ++#define RCPU2_AUDIO_I2S2_SYS_CLK_CTRL 0x44 ++#define RCPU2_AUDIO_I2S3_SYS_CLK_CTRL 0x54 ++ ++/* RCPU SPICTRL register offsets */ ++#define RCPU3_SSP0_CLK_RST 0x00 ++#define RCPU3_SSP1_CLK_RST 0x04 ++#define RCPU3_PWR_SSP_CLK_RST 0x08 ++ ++/* RCPU I2CCTRL register offsets */ ++#define RCPU4_I2C0_CLK_RST 0x00 ++#define RCPU4_I2C1_CLK_RST 0x04 ++#define RCPU4_PWR_I2C_CLK_RST 0x08 ++ ++/* RPMU register offsets */ ++#define RCPU5_AON_PER_CLK_RST_CTRL 0x2C ++#define RCPU5_TIMER1_CLK_RST 0x4C ++#define RCPU5_TIMER2_CLK_RST 0x70 ++#define RCPU5_TIMER3_CLK_RST 0x78 ++#define RCPU5_TIMER4_CLK_RST 0x7C ++#define RCPU5_GPIO_AND_EDGE_CLK_RST 0x74 ++#define RCPU5_RCPU_BUS_CLK_CTRL 0xC0 ++#define RCPU5_RT24_CORE0_CLK_CTRL 0xC4 ++#define RCPU5_RT24_CORE1_CLK_CTRL 0xC8 ++#define RCPU5_RT24_CORE0_SW_RESET 0xCC ++#define RCPU5_RT24_CORE1_SW_RESET 0xD0 ++ ++/* RCPU PWMCTRL register offsets */ ++#define RCPU6_PWM0_CLK_RST 0x00 ++#define RCPU6_PWM1_CLK_RST 0x04 ++#define RCPU6_PWM2_CLK_RST 0x08 ++#define RCPU6_PWM3_CLK_RST 0x0c ++#define RCPU6_PWM4_CLK_RST 0x10 ++#define RCPU6_PWM5_CLK_RST 0x14 ++#define RCPU6_PWM6_CLK_RST 0x18 ++#define RCPU6_PWM7_CLK_RST 0x1c ++#define RCPU6_PWM8_CLK_RST 0x20 ++#define RCPU6_PWM9_CLK_RST 0x24 ++ ++/* APBC2 SEC register offsets */ ++#define APBC2_UART1_CLK_RST 0x00 ++#define APBC2_SSP2_CLK_RST 0x04 ++#define APBC2_TWSI3_CLK_RST 0x08 ++#define APBC2_RTC_CLK_RST 0x0c ++#define APBC2_TIMERS_CLK_RST 0x10 ++#define APBC2_GPIO_CLK_RST 0x1c ++ ++#endif /* __SOC_K3_SYSCON_H__ */ +diff --git a/include/soc/spacemit/spacemit-syscon.h b/include/soc/spacemit/spacemit-syscon.h +new file mode 100644 +index 000000000000..517ccf3f928d +--- /dev/null ++++ b/include/soc/spacemit/spacemit-syscon.h +@@ -0,0 +1,20 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* SpacemiT clock and reset driver definitions for the K1 SoC */ ++ ++#ifndef __SOC_SPACEMIT_SYSCON_H__ ++#define __SOC_SPACEMIT_SYSCON_H__ ++ ++/* Auxiliary device used to represent a CCU reset controller */ ++struct spacemit_ccu_adev { ++ struct auxiliary_device adev; ++ struct regmap *regmap; ++}; ++ ++static inline struct spacemit_ccu_adev * ++to_spacemit_ccu_adev(struct auxiliary_device *adev) ++{ ++ return container_of(adev, struct spacemit_ccu_adev, adev); ++} ++ ++#endif /* __SOC_SPACEMIT_SYSCON_H__ */ diff --git a/include/soc/xuantie/th1520_system_monitor.h b/include/soc/xuantie/th1520_system_monitor.h new file mode 100644 index 000000000000..69a756b628b7 @@ -645280,6 +647736,246 @@ index 000000000000..3f9371de2af7 + } +] \ No newline at end of file +diff --git a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/metrics.json b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/metrics.json +new file mode 100644 +index 000000000000..34a39db41ecf +--- /dev/null ++++ b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/metrics.json +@@ -0,0 +1,234 @@ ++[ ++ { ++ "MetricName": "misprediction", ++ "MetricExpr": "BR_MIS_PRED / BR_PRED", ++ "BriefDescription": "Branch predictor misprediction rate. May not count branches that are never resolved because they are in the misprediction shadow of an earlier branch", ++ "MetricGroup": "Branch", ++ "ScaleUnit": "1per branch" ++ }, ++ { ++ "MetricName": "misprediction_retired", ++ "MetricExpr": "BR_MIS_PRED_RETIRED / BR_RETIRED", ++ "BriefDescription": "Branch predictor misprediction rate (retired).", ++ "MetricGroup": "Branch", ++ "ScaleUnit": "1per branch" ++ }, ++ { ++ "MetricName": "bus_utilization", ++ "MetricExpr": "BUS_ACCESS / (CPU_CYCLES * 1)", ++ "BriefDescription": "Core-to-uncore bus utilization", ++ "MetricGroup": "Bus", ++ "ScaleUnit": "1percent of bus cycles" ++ }, ++ { ++ "MetricName": "l1d_cache_miss", ++ "MetricExpr": "L1D_CACHE_REFILL / L1D_CACHE", ++ "BriefDescription": "L1D cache miss rate", ++ "MetricGroup": "Cache", ++ "ScaleUnit": "1per cache access" ++ }, ++ { ++ "MetricName": "l1d_cache_read_miss", ++ "MetricExpr": "L1D_CACHE_LMISS_RD / L1D_CACHE_RD", ++ "BriefDescription": "L1D cache read miss rate", ++ "MetricGroup": "Cache", ++ "ScaleUnit": "1per cache access" ++ }, ++ { ++ "MetricName": "l1i_cache_miss", ++ "MetricExpr": "L1I_CACHE_REFILL / L1I_CACHE", ++ "BriefDescription": "L1I cache miss rate", ++ "MetricGroup": "Cache", ++ "ScaleUnit": "1per cache access" ++ }, ++ { ++ "MetricName": "l2_cache_miss", ++ "MetricExpr": "L2_CACHE_REFILL / L2_CACHE", ++ "BriefDescription": "L2 cache miss rate", ++ "MetricGroup": "Cache", ++ "ScaleUnit": "1per cache access" ++ }, ++ { ++ "MetricName": "l1i_cache_read_miss", ++ "MetricExpr": "L1I_CACHE_LMISS / L1I_CACHE", ++ "BriefDescription": "L1I cache read miss rate", ++ "MetricGroup": "Cache", ++ "ScaleUnit": "1per cache access" ++ }, ++ { ++ "MetricName": "l2_cache_read_miss", ++ "MetricExpr": "L2_CACHE_LMISS_RD / L2_CACHE_RD", ++ "BriefDescription": "L2 cache read miss rate", ++ "MetricGroup": "Cache", ++ "ScaleUnit": "1per cache access" ++ }, ++ { ++ "MetricName": "mpki_data", ++ "MetricExpr": "(L1D_CACHE_LMISS_RD * 1000) / INST_RETIRED", ++ "BriefDescription": "Misses per thousand instructions (data)", ++ "MetricGroup": "Cache", ++ "ScaleUnit": "1MPKI" ++ }, ++ { ++ "MetricName": "mpki_instruction", ++ "MetricExpr": "(L1I_CACHE_LMISS * 1000) / INST_RETIRED", ++ "BriefDescription": "Misses per thousand instructions (instruction)", ++ "MetricGroup": "Cache", ++ "ScaleUnit": "1MPKI" ++ }, ++ { ++ "MetricName": "vector_mix", ++ "MetricExpr": "VEC_INST_SPEC / OP_SPEC", ++ "BriefDescription": "Proportion of vector data processing operations (excluding vector LD/ST_SPEC) operations", ++ "MetricGroup": "Instruction", ++ "ScaleUnit": "1percent of operations" ++ }, ++ { ++ "MetricName": "crypto_mix", ++ "MetricExpr": "CRYPTO_SPEC / OP_SPEC", ++ "BriefDescription": "Proportion of crypto data processing operations", ++ "MetricGroup": "Instruction", ++ "ScaleUnit": "1percent of operations" ++ }, ++ { ++ "MetricName": "integer_mix", ++ "MetricExpr": "DP_SPEC / OP_SPEC", ++ "BriefDescription": "Proportion of integer data processing operations", ++ "MetricGroup": "Instruction", ++ "ScaleUnit": "1percent of operations" ++ }, ++ { ++ "MetricName": "load_mix", ++ "MetricExpr": "LD_SPEC / OP_SPEC", ++ "BriefDescription": "Proportion of load operations", ++ "MetricGroup": "Instruction", ++ "ScaleUnit": "1percent of operations" ++ }, ++ { ++ "MetricName": "pc_write_mix", ++ "MetricExpr": "PC_WRITE_SPEC / OP_SPEC", ++ "BriefDescription": "Proportion of software change of PC operations", ++ "MetricGroup": "Instruction", ++ "ScaleUnit": "1percent of operations" ++ }, ++ { ++ "MetricName": "store_mix", ++ "MetricExpr": "ST_SPEC / OP_SPEC", ++ "BriefDescription": "Proportion of store operations", ++ "MetricGroup": "Instruction", ++ "ScaleUnit": "1percent of operations" ++ }, ++ { ++ "MetricName": "vfp_mix", ++ "MetricExpr": "VFP_SPEC / OP_SPEC", ++ "BriefDescription": "Proportion of FP operations", ++ "MetricGroup": "Instruction", ++ "ScaleUnit": "1percent of operations" ++ }, ++ { ++ "MetricName": "gflops_issued", ++ "MetricExpr": "VFP_SPEC / (duration_time * 1000000000)", ++ "BriefDescription": "Giga-floating point operations per second", ++ "MetricGroup": "Instruction", ++ "ScaleUnit": "1GFLOPS" ++ }, ++ { ++ "MetricName": "mips_utilization", ++ "MetricExpr": "INST_SPEC / (duration_time * 1000000)", ++ "BriefDescription": "Millions of instructions per second", ++ "MetricGroup": "Instruction", ++ "ScaleUnit": "1MIPS" ++ }, ++ { ++ "MetricName": "mips_retired", ++ "MetricExpr": "INST_RETIRED / (duration_time * 1000000)", ++ "BriefDescription": "Millions of instructions per second", ++ "MetricGroup": "Instruction", ++ "ScaleUnit": "1MIPS" ++ }, ++ { ++ "MetricName": "ipc", ++ "MetricExpr": "INST_RETIRED / CPU_CYCLES", ++ "BriefDescription": "Instructions per cycle", ++ "MetricGroup": "Instruction", ++ "ScaleUnit": "1per cycle" ++ }, ++ { ++ "MetricName": "cpu_lost", ++ "MetricExpr": "1 - (OP_RETIRED / (CPU_CYCLES * 6))", ++ "BriefDescription": "Proportion of slots lost", ++ "MetricGroup": "Speculation", ++ "ScaleUnit": "1percent of slots" ++ }, ++ { ++ "MetricName": "cpu_utilization", ++ "MetricExpr": "OP_RETIRED / (CPU_CYCLES * 6)", ++ "BriefDescription": "Proportion of slots retiring", ++ "MetricGroup": "Speculation", ++ "ScaleUnit": "1percent of slots" ++ }, ++ { ++ "MetricName": "operations_lost", ++ "MetricExpr": "OP_SPEC - OP_RETIRED", ++ "BriefDescription": "Operations lost due to misspeculation", ++ "MetricGroup": "Speculation", ++ "ScaleUnit": "1operation" ++ }, ++ { ++ "MetricName": "operations_lost_ratio", ++ "MetricExpr": "1 - (OP_RETIRED / OP_SPEC)", ++ "BriefDescription": "Proportion of operations lost", ++ "MetricGroup": "Speculation", ++ "ScaleUnit": "100%" ++ }, ++ { ++ "MetricName": "operations_retired", ++ "MetricExpr": "OP_RETIRED / OP_SPEC", ++ "BriefDescription": "Proportion of operations retired", ++ "MetricGroup": "Speculation", ++ "ScaleUnit": "100%" ++ }, ++ { ++ "MetricName": "dtlb_walks", ++ "MetricExpr": "DTLB_WALK / L1D_TLB", ++ "BriefDescription": "D-side walk per d-side translation request", ++ "MetricGroup": "TLB", ++ "ScaleUnit": "1per TLB access" ++ }, ++ { ++ "MetricName": "itlb_walks", ++ "MetricExpr": "ITLB_WALK / L1I_TLB", ++ "BriefDescription": "I-side walk per i-side translation request", ++ "MetricGroup": "TLB", ++ "ScaleUnit": "1per TLB access" ++ }, ++ { ++ "MetricName": "backend", ++ "MetricExpr": "(STALL_SLOT_BACKEND - 4 * BR_MIS_PRED) / (CPU_CYCLES * 6)", ++ "BriefDescription": "Fraction of slots backend bound", ++ "MetricGroup": "TopDownL1", ++ "ScaleUnit": "100%" ++ }, ++ { ++ "MetricName": "frontend", ++ "MetricExpr": "(STALL_SLOT_FRONTEND - 4 * BR_MIS_PRED) / (CPU_CYCLES * 6)", ++ "BriefDescription": "Fraction of slots frontend bound", ++ "MetricGroup": "TopDownL1", ++ "ScaleUnit": "100%" ++ }, ++ { ++ "MetricName": "lost", ++ "MetricExpr": "((OP_SPEC - OP_RETIRED + 8 * BR_MIS_PRED) / (CPU_CYCLES * 6))", ++ "BriefDescription": "Fraction of slots lost due to misspeculation", ++ "MetricGroup": "TopDownL1", ++ "ScaleUnit": "100%" ++ }, ++ { ++ "MetricName": "retiring", ++ "MetricExpr": "OP_RETIRED / (CPU_CYCLES * 6)", ++ "BriefDescription": "Fraction of slots retiring, useful work", ++ "MetricGroup": "TopDownL1", ++ "ScaleUnit": "100%" ++ } ++] ++ diff --git a/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/pipeline.json b/tools/perf/pmu-events/arch/riscv/lrw/lrw-core/pipeline.json new file mode 100644 index 000000000000..1773b59e4aca @@ -645619,6 +648315,32 @@ index c61b3d6ef616..325f5120d88b 100644 +0x5b7-0x0-0x0,v1,thead/c900-legacy,core +0x90c010d,v1,thead/th1520-ddr,uncore +0x0-0x8000000000000920-0x3000020240831,v1,lrw/lrw-core,core +diff --git a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json +index a9939823b14b..0c9b9a2d2958 100644 +--- a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json ++++ b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json +@@ -74,7 +74,7 @@ + { + "PublicDescription": "Sent SFENCE.VMA with ASID request to other HART event", + "ConfigCode": "0x800000000000000c", +- "EventName": "FW_SFENCE_VMA_RECEIVED", ++ "EventName": "FW_SFENCE_VMA_ASID_SENT", + "BriefDescription": "Sent SFENCE.VMA with ASID request to other HART event" + }, + { +diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json +index 9b4a032186a7..7149caec4f80 100644 +--- a/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json ++++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json +@@ -36,7 +36,7 @@ + "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" + }, + { +- "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" ++ "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" + }, + { + "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" diff --git a/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/cache.json b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/cache.json new file mode 100644 index 000000000000..2b142348d635 @@ -645694,7 +648416,7 @@ index 000000000000..2b142348d635 +] diff --git a/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json new file mode 100644 -index 000000000000..9b4a032186a7 +index 000000000000..7149caec4f80 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json @@ -0,0 +1,68 @@ @@ -645736,7 +648458,7 @@ index 000000000000..9b4a032186a7 + "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" + }, + { -+ "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" ++ "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" + }, + { + "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" diff --git a/kernel.spec b/kernel.spec index cf875e2e298bc35e2d6f820078215f057f63cdc2..e7b4db7615da5afe0ff1dfa04779608a6e843fad 100644 --- a/kernel.spec +++ b/kernel.spec @@ -42,7 +42,7 @@ rm -f test_openEuler_sign.ko test_openEuler_sign.ko.sig %global upstream_sublevel 0 %global devel_release 126 %global maintenance_release .0.0 -%global pkg_release .103 +%global pkg_release .104 %global openeuler_lts 1 %global openeuler_major 2403 @@ -1138,6 +1138,11 @@ fi %endif %changelog +* Tue Dec 09 2025 Mingzheng Xing - 6.6.0-126.0.0.104 +- Bugfix: Fix duplicate RISC-V SBI firmware event name +- Add lrw core JSON file with metric support +- Add support for Spacemit K3 + * Thu Dec 04 2025 Mingzheng Xing - 6.6.0-126.0.0.103 - RISC-V kernel upgrade to 6.6.0-126.0.0 - Add support for LRW, DP1000