From eb573ad29d466a0832be8ad47be7f216d59cbc66 Mon Sep 17 00:00:00 2001
From: vicwang-oc <vicwang-oc@zhaoxin.com>
Date: Thu, 4 Sep 2025 19:02:21 +0800
Subject: [PATCH] Add zhaoxin cpu support.

---
 openjdk-21.spec           |  7 +++-
 zhaoxin-cpu-support.patch | 81 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 87 insertions(+), 1 deletion(-)
 create mode 100644 zhaoxin-cpu-support.patch

diff --git a/openjdk-21.spec b/openjdk-21.spec
index c2e74a4..cced01a 100644
--- a/openjdk-21.spec
+++ b/openjdk-21.spec
@@ -905,7 +905,7 @@ Name:    java-21-%{origin}
 Version: %{newjavaver}.%{buildver}
 # This package needs `.rolling` as part of Release so as to not conflict on install with
 # java-X-openjdk. I.e. when latest rolling release is also an LTS release packaged as
-Release: 2
+Release: 3
 
 # java-1.5.0-ibm from jpackage.org set Epoch to 1 for unknown reasons
 # and this change was brought into RHEL-4. java-1.5.0-ibm packages
@@ -1039,6 +1039,7 @@ Patch94: huawei-AArch64-Incorrect-matching-rule.patch
 
 #21.0.8
 Patch95: huawei-remove-provides-in-kaeprovider-module-info.patch
+Patch96: zhaoxin-cpu-support.patch
 
 ############################################
 #
@@ -1343,6 +1344,7 @@ pushd %{top_level_dir_name}
 %patch93 -p1
 %patch94 -p1
 %patch95 -p1
+%patch96 -p1
 popd # openjdk
 %endif
 
@@ -1918,6 +1920,9 @@ cjc.mainProgram(args) -- the returns from copy_jdk_configs.lua should not affect
 
 
 %changelog
+* Thu Sep 4 2025 vicwang-oc <vicwang-oc@zhaoxin.com> - 1:21.0.8.9-3
+- zhaoxin-cpu-support.patch
+
 * Mon Jul 21 2025 Dingli Zhang <dingli@iscas.ac.cn> - 1:21.0.8.9-2
 - Fix build error for riscv64
 
diff --git a/zhaoxin-cpu-support.patch b/zhaoxin-cpu-support.patch
new file mode 100644
index 0000000..4b10627
--- /dev/null
+++ b/zhaoxin-cpu-support.patch
@@ -0,0 +1,81 @@
+diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp b/src/hotspot/cpu/x86/vm_version_x86.cpp
+--- a/src/hotspot/cpu/x86/vm_version_x86.cpp
++++ b/src/hotspot/cpu/x86/vm_version_x86.cpp
+@@ -873,11 +873,18 @@
+   if (UseSSE < 1)
+     _features &= ~CPU_SSE;
+ 
+-  //since AVX instructions is slower than SSE in some ZX cpus, force USEAVX=0.
+-  if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7))) {
+-    UseAVX = 0;
++  //ZX cpus specific settings
++  if (is_zx() && FLAG_IS_DEFAULT(UseAVX)) {
++    if (cpu_family() == 7) {
++      if (extended_cpu_model() == 0x5B || extended_cpu_model() == 0x6B) {
++        UseAVX = 1;
++      } else if (extended_cpu_model() == 0x1B || extended_cpu_model() == 0x3B) {
++        UseAVX = 0;
++      }
++    } else if (cpu_family() == 6) {
++      UseAVX = 0;
++    }
+   }
+-
+   // UseSSE is set to the smaller of what hardware supports and what
+   // the command line requires.  I.e., you cannot set UseSSE to 2 on
+   // older Pentiums which do not support it.
+@@ -2600,6 +2607,7 @@
+ 
+ const char* VM_Version::cpu_family_description(void) {
+   int cpu_family_id = extended_cpu_family();
++  int cpu_model_id = extended_cpu_model();
+   if (is_amd()) {
+     if (cpu_family_id < ExtendedFamilyIdLength_AMD) {
+       return _family_id_amd[cpu_family_id];
+@@ -2616,6 +2624,23 @@
+   if (is_hygon()) {
+     return "Dhyana";
+   }
++  if (is_zx()) {
++    if (cpu_family_id == 7) {
++      switch (cpu_model_id) {
++        case 0x1B:
++          return "wudaokou";
++        case 0x3B:
++          return "lujiazui";
++        case 0x5B:
++          return "yongfeng";
++        case 0x6B:
++          return "shijidadao";
++      }
++    } else if (cpu_family_id == 6) {
++        return "zhangjiang";
++    }
++  }
++
+   return "Unknown x86";
+ }
+ 
+@@ -2635,6 +2660,9 @@
+   } else if (is_hygon()) {
+     cpu_type = "Hygon";
+     x64 = cpu_is_em64t() ? " AMD64" : "";
++  } else if (is_zx()) {
++    cpu_type = "Zhaoxin";
++    x64 = cpu_is_em64t() ? "x86_64" : "";
+   } else {
+     cpu_type = "Unknown x86";
+     x64 = cpu_is_em64t() ? " x86_64" : "";
+@@ -3199,6 +3227,12 @@
+     } else {
+       return 128; // Athlon
+     }
++   } else if (is_zx()) { // ZX
++      if (supports_sse2()) {
++        return 256;
++      } else {
++        return 128;
++      }
+   } else { // Intel
+     if (supports_sse3() && cpu_family() == 6) {
+       if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus
-- 
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