# my_vortex_202212

**Repository Path**: wu-yulin-1/my_vortex_202212

## Basic Information

- **Project Name**: my_vortex_202212
- **Description**: Port  Vortex-GPGPU  to Xilinx  with uart 
- **Primary Language**: Unknown
- **License**: BSD-3-Clause
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 1
- **Created**: 2023-03-27
- **Last Updated**: 2023-03-27

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

1 add uart-sram version for xilinx

   os: ubuntu 18.04   
 
   a prepare:

	prebuild:
		链接: https://pan.baidu.com/s/1me38xI-vtsjXQJjN_66sWw  密码: 9bic
		--来自百度网盘超级会员V5的分享

		cd /opt/
		sudo  unzip *.zip    ./
		
	cd  your_wrk_path 
        git clone https://gitee.com/haoanqi/my_vortex_202212.git
        cd my_vortex_202212
        unzip hw.zip
        ./cat_file
        unzip third_party.zip
        unzip verdi_no_ccip.zip

	sudo pip3  install pyserial

	source setup.sh 
	

    b sim without uart
        cd verdi_no_ccip
        make


    c sim with uart 
        cd fpga
        modify verdi path in makefile
        make
        
        demo_data:
                ./vecadd    (opencl)    (demo_path   tests/opencl/vecadd/    )
                ./c_vecadd  (c     )    (demo_path   tests/runtime/vecadd/   )

    d fpga
        cd fpga 
        cd uart 
        cp  ../FPGA_DDR_dataa.txt   ../FPGA_DDR_r1.txt  ../FPGA_DDR_r2.txt  to ./
        generate bin file :   python3 ./gen_demo_bin.py
        start demo        :   sudo python3 ./serial_sendfile_demo.py


2 add uart-ddr  version for xilinx 




[![Build Status](https://travis-ci.com/vortexgpgpu/vortex.svg?branch=master)](https://travis-ci.com/vortexgpgpu/vortex)
[![codecov](https://codecov.io/gh/vortexgpgpu/vortex/branch/master/graph/badge.svg)](https://codecov.io/gh/vortexgpgpu/vortex)

# Vortex OpenGPU

Vortex is a full-system RISCV-based GPGPU processor.

## Specifications

- Support RISC-V RV32IMF ISA
- Performance: 
    - 1024 total threads running at 250 MHz
    - 128 Gflops of compute bandwidth
    - 16 GB/s of memory bandwidth
- Scalability: up to 64 cores with optional L2 and L3 caches
- Software: OpenCL 1.2 Support 
- Supported FPGAs: 
    - Intel Arria 10
    - Intel Stratix 10

## Directory structure

- `doc`: [Documentation](docs/index.md).
- `hw`: Hardware sources.
- `driver`: Host drivers repository.
- `runtime`: Kernel Runtime software.
- `sim`: Simulators repository.
- `tests`: Tests repository.
- `ci`: Continuous integration scripts.
- `miscs`: Miscellaneous resources.

## Build Instructions
### Supported OS Platforms
- Ubuntu 18.04
- Centos 7
### Toolchain Dependencies
- [POCL](http://portablecl.org/)
- [LLVM](https://llvm.org/)
- [RISCV-GNU-TOOLCHAIN](https://github.com/riscv-collab/riscv-gnu-toolchain)
- [Verilator](https://www.veripool.org/verilator)
### Install development tools 
    $ sudo apt-get install build-essential
    $ sudo apt-get install git
### Install Vortex codebase
    $ git clone --recursive https://github.com/vortexgpgpu/vortex.git
    $ cd Vortex
### Install prebuilt toolchain
    $ ./ci/toolchain_install.sh -all
### Build Vortex sources
    $ make -s
### Quick demo running vecadd OpenCL kernel on 2 cores
    $ ./ci/blackbox.sh --driver=rtlsim --cores=2 --app=vecadd