# 南方科技大学-CS202_214-计算机组成原理-大作业

**Repository Path**: yecanming/SUSTech-CS202_214-Computer_Organization-Project

## Basic Information

- **Project Name**: 南方科技大学-CS202_214-计算机组成原理-大作业
- **Description**: 这是南方科技大学CS202/214计算机组成原理课程的大作业——实现一个CPU。
This is the project assignment of cs202 / 214 Computer Organization course of Southern University of Science and Technology， which is to manufacture a CPU.
- **Primary Language**: Verilog
- **License**: MulanPSL-2.0
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 1
- **Forks**: 0
- **Created**: 2022-05-14
- **Last Updated**: 2022-06-06

## Categories & Tags

**Categories**: Uncategorized

**Tags**: CPU, Verilog, mips, minisys, sustech

## README

# SUSTech CS202/214 Computer Organization Project

[![](https://img.shields.io/badge/English-%E4%B8%AD%E6%96%87-green.svg)](README.md)[![](https://img.shields.io/badge/License-MulanPSL%202.0-green.svg)](LICENSE)[![](https://img.shields.io/badge/Chat-on%20QQ-green.svg?logo=tencentqq)](https://jq.qq.com/?_wv=1027&k=d02UjNgH)

This is a big assignment of cs202 / 214 computer organization course of Southern University of science and technology，which is to realize a CPU.

The basic function of this project is to realize a single cycle CPU supporting MIPS instruction set based on FPGA and Verilog language.

## Building from Source

## How to contribute