# CPEN211LAB

**Repository Path**: yuzihao1231/cpen211-lab

## Basic Information

- **Project Name**: CPEN211LAB
- **Description**: CPEN211LAB, make a RISCV computer
- **Primary Language**: Unknown
- **License**: GPL-2.0
- **Default Branch**: master
- **Homepage**: https://blog.csdn.net/qq_45467083
- **GVP Project**: No

## Statistics

- **Stars**: 8
- **Forks**: 0
- **Created**: 2021-08-07
- **Last Updated**: 2025-07-21

## Categories & Tags

**Categories**: risc-v

**Tags**: RISC-V, CPEN211

## README

# CPEN211LAB

#### 介绍
CPEN211LAB, make a RISCV computer

#### 软件架构
Only including Verilog files and testbench, you can simulate on any FPGA platform.


#### 安装教程

1.  create a project in vivado
2.  add design source with lab?.srcs/sources_1/*
3.  add testbench with lab?.srcs/sim_1/*
4.  run simulation
5.  you can also add design file in quartus II

#### 使用说明

1.  xxxx
2.  xxxx
3.  xxxx

#### 参与贡献

1.  Fork 本仓库
2.  新建 Feat_xxx 分支
3.  提交代码
4.  新建 Pull Request