# pyverilog

**Repository Path**: zhu-yangzong/pyverilog

## Basic Information

- **Project Name**: pyverilog
- **Description**: 用python写Verilog HDL
- **Primary Language**: Unknown
- **License**: MulanPSL-2.0
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 4
- **Forks**: 0
- **Created**: 2022-04-01
- **Last Updated**: 2022-04-02

## Categories & Tags

**Categories**: Uncategorized

**Tags**: Python, Verilog, pyverilog

## README

# pyverilog

#### 介绍
用python写Verilog HDL的模块，自己学习的笔记。