LogicFactory is an open-source logic synthesis platform for integrated cross-tool flow.
Automatic test pattern generation and fault simulation tool, support combination, full scan and partial scan netlist.
This project aims to develop a rectilinear Steiner tree construction algorithm designed to reduce Elmore delay meanwhile maintaining a bounded wirelength.
iEDA-课程相关的材料主仓库。目前,EDA及芯片设计门槛依然较高,亟需一项能够快速入门的EDA学习课程。本项目拟打造通用的EDA综合人才培养训练计划,适用于EDA团队技术栈培养及高校EDA课程实践,以简单易上手的方式提供EDA学习方案。学习者在完成本项目后,能够了解EDA开发的基本流程,掌握C++和EDA的基础知识,具备初步的后端开发工程实践能力。
Calibrate path delay calculation results using machine learning methods.