This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.
Made a CPU in Logisim when I was 14 (2009), and wrote a naive assembler and compiler for it in Flash. The CPU's design is inspired by Donn Stewart, http://cpuville.com.
Designing a 32-bit MIPS CPU in Logisim
Mips cpu built by logisim, include single cycle cpu, single cycle cpu with trap(interrupt), 5 stage pipeline with BHT
A 32-bit CPU wired according to the RISC-V ISA under the guidance of Carnegie Mellon PhD student Sol Boucher
BUAA Computer Organization Project3 CPU monocycle
Hello, I've been working on this project for about 3-4 weeks now. But the idea has been around for months. I've been playing around and decided to make a MIPS CPU becasause what else is there to do in Coronacation?
Register File, ALU, and 32 bit 2-cycle (Pipelined) CPU in Logisim
基于logisim实现的单周期MIPS CPU仿真：32 bits MIPS CPU processor based on logisim
ALU, Regfile and CPU simulators on Logisim.
Simulation of a RISC-V CPU, created via Logisim
